Mercurial > hg > CbC > CbC_gcc
diff gcc/config/h8300/h8300.md @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | f6334be47118 |
| children | 84e7813d76e9 |
line wrap: on
line diff
--- a/gcc/config/h8300/h8300.md Sun Aug 21 07:07:55 2011 +0900 +++ b/gcc/config/h8300/h8300.md Fri Oct 27 22:46:09 2017 +0900 @@ -1,7 +1,5 @@ ;; GCC machine description for Renesas H8/300 -;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010 -;; Free Software Foundation, Inc. +;; Copyright (C) 1992-2017 Free Software Foundation, Inc. ;; Contributed by Steve Chamberlain (sac@cygnus.com), ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). @@ -102,26 +100,21 @@ (const_int 4) (const_int 6))) (eq_attr "type" "bitbranch") - (if_then_else - (and (ge (minus (match_dup 0) (pc)) - (const_int -126)) - (le (minus (match_dup 0) (pc)) - (const_int 126))) - (plus - (symbol_ref "h8300_insn_length_from_table (insn, operands)") - (const_int 2)) - (if_then_else - (and (eq_attr "cpu" "h8300h") - (and (ge (minus (pc) (match_dup 0)) - (const_int -32000)) - (le (minus (pc) (match_dup 0)) - (const_int 32000)))) - (plus - (symbol_ref "h8300_insn_length_from_table (insn, operands)") - (const_int 4)) - (plus - (symbol_ref "h8300_insn_length_from_table (insn, operands)") - (const_int 6)))) + (if_then_else (and (ge (minus (match_dup 0) (pc)) + (const_int -126)) + (le (minus (match_dup 0) (pc)) + (const_int 126))) + (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") + (const_int 2)) + (if_then_else (and (eq_attr "cpu" "h8300h") + (and (ge (minus (pc) (match_dup 0)) + (const_int -32000)) + (le (minus (pc) (match_dup 0)) + (const_int 32000)))) + (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") + (const_int 4)) + (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") + (const_int 6)))) (eq_attr "length_table" "!none") (symbol_ref "h8300_insn_length_from_table (insn, operands)")] (const_int 200))) @@ -143,6 +136,7 @@ ;; Type of delay slot. NONE means the instruction has no delay slot. ;; JUMP means it is an unconditional jump that (if short enough) ;; could be implemented using bra/s. + (define_attr "delay_slot" "none,jump" (const_string "none")) @@ -150,6 +144,7 @@ ;; entirely clear that jsr is not valid in delay slots, but it ;; definitely doesn't have the effect of causing the called function ;; to return to the target of the delayed branch. + (define_attr "can_delay" "no,yes" (cond [(eq_attr "type" "branch,bitbranch,call") (const_string "no") @@ -160,6 +155,7 @@ ;; Only allow jumps to have a delay slot if we think they might ;; be short enough. This is just an optimization: we don't know ;; for certain whether they will be or not. + (define_delay (and (eq_attr "delay_slot" "jump") (eq (symbol_ref "get_attr_length (insn)") (const_int 2))) [(eq_attr "can_delay" "yes") @@ -171,12 +167,23 @@ (define_asm_attributes [(set (attr "length") - (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4) - (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10) - (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)] + (cond [(match_test "TARGET_H8300") (const_int 4) + (match_test "TARGET_H8300H") (const_int 10) + (match_test "TARGET_H8300S") (const_int 10)] (const_int 14)))]) (include "predicates.md") +(include "constraints.md") + +;; ---------------------------------------------------------------------- +;; MACRO DEFINITIONS +;; ---------------------------------------------------------------------- + +;; This mode iterator allows :P to be used for patterns that operate on +;; pointer-sized quantities. Exactly one of the two alternatives will match. + +(define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")]) + ;; ---------------------------------------------------------------------- ;; MOVE INSTRUCTIONS @@ -188,8 +195,7 @@ [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m") (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))] "TARGET_H8300 - && (register_operand (operands[0], QImode) - || register_operand (operands[1], QImode))" + && h8300_move_ok (operands[0], operands[1])" "@ sub.b %X0,%X0 mov.b %R1,%X0 @@ -204,8 +210,7 @@ [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m") (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))] "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX - && (register_operand (operands[0], QImode) - || register_operand (operands[1], QImode))" + && h8300_move_ok (operands[0], operands[1])" "@ sub.b %X0,%X0 mov.b %R1,%X0 @@ -231,16 +236,11 @@ [(set (match_operand:QI 0 "general_operand_dst" "") (match_operand:QI 1 "general_operand_src" ""))] "" - " -{ - /* One of the ops has to be in a register. */ - if (!TARGET_H8300SX - && !register_operand (operand0, QImode) - && !register_operand (operand1, QImode)) - { - operands[1] = copy_to_mode_reg (QImode, operand1); - } -}") + { + /* One of the ops has to be in a register. */ + if (!TARGET_H8300SX && !h8300_move_ok (operands[0], operands[1])) + operands[1] = copy_to_mode_reg (QImode, operands[1]); + }) (define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r")) @@ -259,13 +259,7 @@ [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m") (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))] "TARGET_H8300 - && (register_operand (operands[0], HImode) - || register_operand (operands[1], HImode)) - && !(GET_CODE (operands[0]) == MEM - && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC - && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG - && GET_CODE (operands[1]) == REG - && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))" + && h8300_move_ok (operands[0], operands[1])" "@ sub.w %T0,%T0 mov.w %T1,%T0 @@ -281,8 +275,7 @@ [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m") (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))] "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX - && (register_operand (operands[0], HImode) - || register_operand (operands[1], HImode))" + && h8300_move_ok (operands[0], operands[1])" "@ sub.w %T0,%T0 mov.w %T1,%T0 @@ -312,15 +305,11 @@ [(set (match_operand:HI 0 "general_operand_dst" "") (match_operand:HI 1 "general_operand_src" ""))] "" - " -{ - /* One of the ops has to be in a register. */ - if (!register_operand (operand1, HImode) - && !register_operand (operand0, HImode)) - { + { + /* One of the ops has to be in a register. */ + if (!h8300_move_ok (operands[0], operands[1])) operands[1] = copy_to_mode_reg (HImode, operand1); - } -}") + }) (define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r")) @@ -340,42 +329,36 @@ [(set (match_operand:SI 0 "general_operand_dst" "") (match_operand:SI 1 "general_operand_src" ""))] "" - " -{ - if (TARGET_H8300) - { - if (h8300_expand_movsi (operands)) - DONE; - } - else if (!TARGET_H8300SX) - { - /* One of the ops has to be in a register. */ - if (!register_operand (operand1, SImode) - && !register_operand (operand0, SImode)) - { + { + if (TARGET_H8300) + { + if (h8300_expand_movsi (operands)) + DONE; + } + else if (!TARGET_H8300SX) + { + /* One of the ops has to be in a register. */ + if (!h8300_move_ok (operands[0], operands[1])) operands[1] = copy_to_mode_reg (SImode, operand1); - } - } -}") + } + }) (define_insn "*movsi_h8300" [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r") (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))] "TARGET_H8300 - && (register_operand (operands[0], SImode) - || register_operand (operands[1], SImode))" - "* + && h8300_move_ok (operands[0], operands[1])" { unsigned int rn = -1; switch (which_alternative) { case 0: - return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; + return "sub.w %e0,%e0\;sub.w %f0,%f0"; case 1: if (REGNO (operands[0]) < REGNO (operands[1])) - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + return "mov.w %e1,%e0\;mov.w %f1,%f0"; else - return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; + return "mov.w %f1,%f0\;mov.w %e1,%e0"; case 2: /* Make sure we don't trample the register we index with. */ if (GET_CODE (operands[1]) == MEM) @@ -396,7 +379,7 @@ if (rn == REGNO (operands[0])) { /* Move the second word first. */ - return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; + return "mov.w %f1,%f0\;mov.w %e1,%e0"; } else { @@ -405,27 +388,27 @@ /* If either half is zero, use sub.w to clear that half. */ if ((INTVAL (operands[1]) & 0xffff) == 0) - return \"mov.w %e1,%e0\;sub.w %f0,%f0\"; + return "mov.w %e1,%e0\;sub.w %f0,%f0"; if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0) - return \"sub.w %e0,%e0\;mov.w %f1,%f0\"; + return "sub.w %e0,%e0\;mov.w %f1,%f0"; /* If the upper half and the lower half are the same, copy one half to the other. */ if ((INTVAL (operands[1]) & 0xffff) == ((INTVAL (operands[1]) >> 16) & 0xffff)) - return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\"; + return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0"; } - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + return "mov.w %e1,%e0\;mov.w %f1,%f0"; } case 3: - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + return "mov.w %e1,%e0\;mov.w %f1,%f0"; case 4: - return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; + return "mov.w %f1,%T0\;mov.w %e1,%T0"; case 5: - return \"mov.w %T1,%e0\;mov.w %T1,%f0\"; + return "mov.w %T1,%e0\;mov.w %T1,%f0"; default: gcc_unreachable (); } -}" +} [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))]) @@ -433,25 +416,18 @@ [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r") (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))] "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX - && (register_operand (operands[0], SImode) - || register_operand (operands[1], SImode)) - && !(GET_CODE (operands[0]) == MEM - && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC - && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG - && GET_CODE (operands[1]) == REG - && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))" - "* + && h8300_move_ok (operands[0], operands[1])" { switch (which_alternative) { case 0: - return \"sub.l %S0,%S0\"; + return "sub.l %S0,%S0"; case 7: - return \"clrmac\"; + return "clrmac"; case 8: - return \"clrmac\;ldmac %1,macl\"; + return "clrmac\;ldmac %1,macl"; case 9: - return \"stmac macl,%0\"; + return "stmac macl,%0"; default: if (GET_CODE (operands[1]) == CONST_INT) { @@ -462,13 +438,13 @@ if (val == (val & 0xff)) { operands[1] = GEN_INT ((char) val & 0xff); - return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\"; + return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0"; } if (val == (val & 0xff00)) { operands[1] = GEN_INT ((char) (val >> 8) & 0xff); - return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\"; + return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0"; } /* Look for constants that can be obtained by subs, inc, and @@ -476,31 +452,31 @@ switch (val & 0xffffffff) { case 0xffffffff: - return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\"; + return "sub.l\\t%S0,%S0\;subs\\t#1,%S0"; case 0xfffffffe: - return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\"; + return "sub.l\\t%S0,%S0\;subs\\t#2,%S0"; case 0xfffffffc: - return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\"; + return "sub.l\\t%S0,%S0\;subs\\t#4,%S0"; case 0x0000ffff: - return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\"; + return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0"; case 0x0000fffe: - return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\"; + return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0"; case 0xffff0000: - return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\"; + return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0"; case 0xfffe0000: - return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\"; + return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0"; case 0x00010000: - return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\"; + return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0"; case 0x00020000: - return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\"; + return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0"; } } } - return \"mov.l %S1,%S0\"; -}" + return "mov.l %S1,%S0"; +} [(set (attr "length") (symbol_ref "compute_mov_length (operands)")) (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")]) @@ -535,6 +511,7 @@ ;; Implement block moves using movmd. Defining movmemsi allows the full ;; range of constant lengths (up to 0x40000 bytes when using movmd.l). ;; See h8sx_emit_movmd for details. + (define_expand "movmemsi" [(use (match_operand:BLK 0 "memory_operand" "")) (use (match_operand:BLK 1 "memory_operand" "")) @@ -542,8 +519,7 @@ (use (match_operand:SI 3 "const_int_operand" ""))] "TARGET_H8300SX" { - if (h8sx_emit_movmd (operands[0], operands[1], operands[2], - INTVAL (operands[3]))) + if (h8sx_emit_movmd (operands[0], operands[1], operands[2], INTVAL (operands[3]))) DONE; else FAIL; @@ -552,25 +528,26 @@ ;; Expander for generating movmd insns. Operand 0 is the destination ;; memory region, operand 1 is the source, operand 2 is the counter ;; register and operand 3 is the chunk size (1, 2 or 4). + (define_expand "movmd" [(parallel - [(set (match_operand:BLK 0 "memory_operand" "") - (match_operand:BLK 1 "memory_operand" "")) - (unspec [(match_operand:HI 2 "register_operand" "") - (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (set (match_dup 2) - (const_int 0))])] + [(set (match_operand:BLK 0 "memory_operand" "") + (match_operand:BLK 1 "memory_operand" "")) + (unspec [(match_operand:HI 2 "register_operand" "") + (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (set (match_dup 2) + (const_int 0))])] "TARGET_H8300SX" { operands[4] = copy_rtx (XEXP (operands[0], 0)); operands[5] = copy_rtx (XEXP (operands[1], 0)); }) - ;; This is a difficult instruction to reload since operand 0 must be the ;; frame pointer. See h8300_reg_class_from_letter for an explanation. + (define_insn "movmd_internal_normal" [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r")) (mem:BLK (match_operand:HI 4 "register_operand" "1,1"))) @@ -616,6 +593,7 @@ ;; ;; where <dest> is the current destination register (operand 4). ;; The fourth instruction will be deleted if <dest> dies here. + (define_split [(set (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" "")) @@ -625,8 +603,7 @@ (clobber (match_operand:HI 5 "register_operand" "")) (set (match_dup 2) (const_int 0))] - "TARGET_H8300SX && TARGET_NORMAL_MODE - && reload_completed + "TARGET_H8300SX && TARGET_NORMAL_MODE && reload_completed && REGNO (operands[4]) != DESTINATION_REG" [(const_int 0)] { @@ -648,8 +625,7 @@ (clobber (match_operand:SI 5 "register_operand" "")) (set (match_dup 2) (const_int 0))] - "TARGET_H8300SX && !TARGET_NORMAL_MODE - && reload_completed + "TARGET_H8300SX && !TARGET_NORMAL_MODE && reload_completed && REGNO (operands[4]) != DESTINATION_REG" [(const_int 0)] { @@ -665,6 +641,7 @@ ;; Expand a call to stpcpy() using movsd. Operand 0 should point to ;; the final character, but movsd leaves it pointing to the character ;; after that. + (define_expand "movstr" [(use (match_operand 0 "register_operand" "")) (use (match_operand:BLK 1 "memory_operand" "")) @@ -676,23 +653,22 @@ operands[2] = replace_equiv_address (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0))); emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode))); - emit_insn (gen_add3_insn (operands[0], - XEXP (operands[1], 0), - constm1_rtx)); + emit_insn (gen_add3_insn (operands[0], XEXP (operands[1], 0), constm1_rtx)); DONE; }) ;; Expander for generating a movsd instruction. Operand 0 is the ;; destination string, operand 1 is the source string and operand 2 ;; is a scratch register. + (define_expand "movsd" [(parallel - [(set (match_operand:BLK 0 "memory_operand" "") - (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] - UNSPEC_STPCPY)) - (clobber (match_dup 3)) - (clobber (match_dup 4)) - (clobber (match_operand 2 "register_operand" ""))])] + [(set (match_operand:BLK 0 "memory_operand" "") + (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] + UNSPEC_STPCPY)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) + (clobber (match_operand 2 "register_operand" ""))])] "TARGET_H8300SX" { operands[3] = copy_rtx (XEXP (operands[0], 0)); @@ -700,10 +676,11 @@ }) ;; See comments above memcpy_internal(). + (define_insn "stpcpy_internal_normal" [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r")) (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))] - UNSPEC_STPCPY)) + UNSPEC_STPCPY)) (clobber (match_operand:HI 0 "register_operand" "=d,??D")) (clobber (match_operand:HI 1 "register_operand" "=f,f")) (clobber (match_operand:HI 2 "register_operand" "=c,c"))] @@ -717,7 +694,7 @@ (define_insn "stpcpy_internal" [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r")) (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))] - UNSPEC_STPCPY)) + UNSPEC_STPCPY)) (clobber (match_operand:SI 0 "register_operand" "=d,??D")) (clobber (match_operand:SI 1 "register_operand" "=f,f")) (clobber (match_operand:SI 2 "register_operand" "=c,c"))] @@ -730,14 +707,14 @@ ;; Split the above instruction if the destination isn't er6. This works ;; in the same way as the movmd splitter. + (define_split [(set (match_operand:BLK 0 "memory_operand" "") (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY)) (clobber (match_operand:HI 2 "register_operand" "")) (clobber (match_operand:HI 3 "register_operand" "")) (clobber (match_operand:HI 4 "register_operand" ""))] - "TARGET_H8300SX && TARGET_NORMAL_MODE - && reload_completed + "TARGET_H8300SX && TARGET_NORMAL_MODE && reload_completed && REGNO (operands[2]) != DESTINATION_REG" [(const_int 0)] { @@ -756,8 +733,7 @@ (clobber (match_operand:SI 2 "register_operand" "")) (clobber (match_operand:SI 3 "register_operand" "")) (clobber (match_operand:SI 4 "register_operand" ""))] - "TARGET_H8300SX && !TARGET_NORMAL_MODE - && reload_completed + "TARGET_H8300SX && !TARGET_NORMAL_MODE && reload_completed && REGNO (operands[2]) != DESTINATION_REG" [(const_int 0)] { @@ -776,23 +752,22 @@ [(set (match_operand:SF 0 "general_operand_dst" "") (match_operand:SF 1 "general_operand_src" ""))] "" - " -{ - if (TARGET_H8300) - { - if (h8300_expand_movsi (operands)) - DONE; - } - else if (!TARGET_H8300SX) - { - /* One of the ops has to be in a register. */ - if (!register_operand (operand1, SFmode) - && !register_operand (operand0, SFmode)) - { - operands[1] = copy_to_mode_reg (SFmode, operand1); - } - } -}") + { + if (TARGET_H8300) + { + if (h8300_expand_movsi (operands)) + DONE; + } + else if (!TARGET_H8300SX) + { + /* One of the ops has to be in a register. */ + if (!register_operand (operand1, SFmode) + && !register_operand (operand0, SFmode)) + { + operands[1] = copy_to_mode_reg (SFmode, operand1); + } + } + }) (define_insn "*movsf_h8300" [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r") @@ -800,19 +775,18 @@ "TARGET_H8300 && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode))" - "* { /* Copy of the movsi stuff. */ unsigned int rn = -1; switch (which_alternative) { case 0: - return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; + return "sub.w %e0,%e0\;sub.w %f0,%f0"; case 1: if (REGNO (operands[0]) < REGNO (operands[1])) - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + return "mov.w %e1,%e0\;mov.w %f1,%f0"; else - return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; + return "mov.w %f1,%f0\;mov.w %e1,%e0"; case 2: /* Make sure we don't trample the register we index with. */ if (GET_CODE (operands[1]) == MEM) @@ -832,21 +806,21 @@ } if (rn == REGNO (operands[0])) /* Move the second word first. */ - return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; + return "mov.w %f1,%f0\;mov.w %e1,%e0"; else /* Move the first word first. */ - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + return "mov.w %e1,%e0\;mov.w %f1,%f0"; case 3: - return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; + return "mov.w %e1,%e0\;mov.w %f1,%f0"; case 4: - return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; + return "mov.w %f1,%T0\;mov.w %e1,%T0"; case 5: - return \"mov.w %T1,%e0\;mov.w %T1,%f0\"; + return "mov.w %T1,%e0\;mov.w %T1,%f0"; default: gcc_unreachable (); } -}" +} [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))]) @@ -854,8 +828,8 @@ [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r") (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))] "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX - && (register_operand (operands[0], SFmode) - || register_operand (operands[1], SFmode))" + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode))" "@ sub.l %S0,%S0 mov.l %S1,%S0 @@ -871,131 +845,76 @@ ;; PUSH INSTRUCTIONS ;; ---------------------------------------------------------------------- -(define_insn "pushqi1_h8300" - [(set (reg:HI SP_REG) - (plus:HI (reg:HI SP_REG) (const_int -2))) - (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1))) - (match_operand:QI 0 "register_operand" "r"))] - "TARGET_H8300 - && operands[0] != stack_pointer_rtx" +(define_insn "*pushqi1_h8300" + [(set (mem:QI + (pre_modify:HI + (reg:HI SP_REG) + (plus:HI (reg:HI SP_REG) (const_int -2)))) + (match_operand:QI 0 "register_no_sp_elim_operand" "r"))] + "TARGET_H8300" "mov.w\\t%T0,@-r7" [(set_attr "length" "2")]) -(define_insn "pushqi1_h8300hs_advanced" - [(set (reg:SI SP_REG) - (plus:SI (reg:SI SP_REG) (const_int -4))) - (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3))) - (match_operand:QI 0 "register_operand" "r"))] - "(TARGET_H8300H || TARGET_H8300S) - && operands[0] != stack_pointer_rtx" - "mov.l\\t%S0,@-er7" - [(set_attr "length" "4")]) - -(define_insn "pushqi1_h8300hs_normal" - [(set (reg:HI SP_REG) - (plus:HI (reg:HI SP_REG) (const_int -4))) - (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3))) - (match_operand:QI 0 "register_operand" "r"))] - "(TARGET_H8300H || TARGET_H8300S) - && operands[0] != stack_pointer_rtx" +(define_insn "*pushqi1_h8300hs_<mode>" + [(set (mem:QI + (pre_modify:P + (reg:P SP_REG) + (plus:P (reg:P SP_REG) (const_int -4)))) + (match_operand:QI 0 "register_no_sp_elim_operand" "r"))] + "TARGET_H8300H || TARGET_H8300S" "mov.l\\t%S0,@-er7" [(set_attr "length" "4")]) -(define_expand "pushqi1" - [(match_operand:QI 0 "register_operand" "")] - "" - " -{ - if (TARGET_H8300) - emit_insn (gen_pushqi1_h8300 (operands[0])); - else if (!TARGET_NORMAL_MODE) - emit_insn (gen_pushqi1_h8300hs_advanced (operands[0])); - else - emit_insn (gen_pushqi1_h8300hs_normal (operands[0])); - DONE; -}") - -(define_expand "pushhi1_h8300" - [(set (mem:HI (pre_dec:HI (reg:HI SP_REG))) - (match_operand:HI 0 "register_operand" ""))] - "TARGET_H8300 - && operands[0] != stack_pointer_rtx" - "") - -(define_insn "pushhi1_h8300hs_advanced" - [(set (reg:SI SP_REG) - (plus:SI (reg:SI SP_REG) (const_int -4))) - (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2))) - (match_operand:HI 0 "register_operand" "r"))] - "(TARGET_H8300H || TARGET_H8300S) - && operands[0] != stack_pointer_rtx" +(define_insn "*pushhi1_h8300hs_<mode>" + [(set (mem:HI + (pre_modify:P + (reg:P SP_REG) + (plus:P (reg:P SP_REG) (const_int -4)))) + (match_operand:HI 0 "register_no_sp_elim_operand" "r"))] + "TARGET_H8300H || TARGET_H8300S" "mov.l\\t%S0,@-er7" [(set_attr "length" "4")]) - -(define_insn "pushhi1_h8300hs_normal" - [(set (reg:HI SP_REG) - (plus:HI (reg:HI SP_REG) (const_int -4))) - (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2))) - (match_operand:HI 0 "register_operand" "r"))] - "(TARGET_H8300H || TARGET_H8300S) - && operands[0] != stack_pointer_rtx" - "mov.l\\t%S0,@-er7" - [(set_attr "length" "4")]) - -(define_expand "pushhi1" - [(match_operand:HI 0 "register_operand" "")] - "" - " -{ - if (TARGET_H8300) - emit_insn (gen_pushhi1_h8300 (operands[0])); - else if (!TARGET_NORMAL_MODE) - emit_insn (gen_pushhi1_h8300hs_advanced (operands[0])); - else - emit_insn (gen_pushhi1_h8300hs_normal (operands[0])); - DONE; -}") ;; ---------------------------------------------------------------------- ;; TEST INSTRUCTIONS ;; ---------------------------------------------------------------------- (define_insn "" - [(set (cc0) (compare - (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U") - (const_int 1) - (match_operand 1 "const_int_operand" "n,n")) - (const_int 0)))] + [(set (cc0) + (compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U") + (const_int 1) + (match_operand 1 "const_int_operand" "n,n")) + (const_int 0)))] "TARGET_H8300" "btst %Z1,%Y0" [(set_attr "length" "2,4") (set_attr "cc" "set_zn,set_zn")]) (define_insn "" - [(set (cc0) (compare - (zero_extract:HI (match_operand:HI 0 "register_operand" "r") - (const_int 1) - (match_operand 1 "const_int_operand" "n")) - (const_int 0)))] + [(set (cc0) + (compare (zero_extract:HI (match_operand:HI 0 "register_operand" "r") + (const_int 1) + (match_operand 1 "const_int_operand" "n")) + (const_int 0)))] "TARGET_H8300" "btst %Z1,%Y0" [(set_attr "length" "2") (set_attr "cc" "set_zn")]) (define_insn_and_split "*tst_extzv_1_n" - [(set (cc0) (compare - (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>") - (const_int 1) - (match_operand 1 "const_int_operand" "n,n,n")) - (const_int 0))) + [(set (cc0) + (compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>") + (const_int 1) + (match_operand 1 "const_int_operand" "n,n,n")) + (const_int 0))) (clobber (match_scratch:QI 2 "=X,X,&r"))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "@ btst\\t%Z1,%Y0 btst\\t%Z1,%Y0 #" "&& reload_completed - && !OK_FOR_U (operands[0])" + && !satisfies_constraint_U (operands[0])" [(set (match_dup 2) (match_dup 0)) (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2) @@ -1008,24 +927,26 @@ (set_attr "cc" "set_zn,set_zn,set_zn")]) (define_insn "" - [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") - (const_int 1) - (match_operand 1 "const_int_operand" "n")) - (const_int 0)))] + [(set (cc0) + (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") + (const_int 1) + (match_operand 1 "const_int_operand" "n")) + (const_int 0)))] "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) <= 15" + && INTVAL (operands[1]) <= 15" "btst %Z1,%Y0" [(set_attr "length" "2") (set_attr "cc" "set_zn")]) (define_insn_and_split "*tstsi_upper_bit" - [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") - (const_int 1) - (match_operand 1 "const_int_operand" "n")) - (const_int 0))) + [(set (cc0) + (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") + (const_int 1) + (match_operand 1 "const_int_operand" "n")) + (const_int 0))) (clobber (match_scratch:SI 2 "=&r"))] "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) >= 16" + && INTVAL (operands[1]) >= 16" "#" "&& reload_completed" [(set (match_dup 2) @@ -1033,18 +954,22 @@ (const_int -65536)) (lshiftrt:SI (match_dup 0) (const_int 16)))) - (set (cc0) (compare (zero_extract:SI (match_dup 2) - (const_int 1) - (match_dup 3)) - (const_int 0)))] - "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);") + (set (cc0) + (compare (zero_extract:SI (match_dup 2) + (const_int 1) + (match_dup 3)) + (const_int 0)))] + { + operands[3] = GEN_INT (INTVAL (operands[1]) - 16); + }) (define_insn "*tstsi_variable_bit" - [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") - (const_int 1) - (and:SI (match_operand:SI 1 "register_operand" "r") - (const_int 7))) - (const_int 0)))] + [(set (cc0) + (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") + (const_int 1) + (and:SI (match_operand:SI 1 "register_operand" "r") + (const_int 7))) + (const_int 0)))] "TARGET_H8300H || TARGET_H8300S" "btst %w1,%w0" [(set_attr "length" "2") @@ -1052,69 +977,74 @@ (define_insn_and_split "*tstsi_variable_bit_qi" [(set (cc0) - (compare - (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")) - (const_int 1) - (and:SI (match_operand:SI 1 "register_operand" "r,r,r") - (const_int 7))) - (const_int 0))) + (compare (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")) + (const_int 1) + (and:SI (match_operand:SI 1 "register_operand" "r,r,r") + (const_int 7))) + (const_int 0))) (clobber (match_scratch:QI 2 "=X,X,&r"))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "@ btst\\t%w1,%X0 btst\\t%w1,%X0 #" "&& reload_completed - && !OK_FOR_U (operands[0])" + && !satisfies_constraint_U (operands[0])" [(set (match_dup 2) (match_dup 0)) - (parallel [(set (cc0) (compare (zero_extract:SI (zero_extend:SI (match_dup 2)) - (const_int 1) - (and:SI (match_dup 1) - (const_int 7))) - (const_int 0))) + (parallel [(set (cc0) + (compare (zero_extract:SI (zero_extend:SI (match_dup 2)) + (const_int 1) + (and:SI (match_dup 1) + (const_int 7))) + (const_int 0))) (clobber (scratch:QI))])] "" [(set_attr "length" "2,8,10") (set_attr "cc" "set_zn,set_zn,set_zn")]) (define_insn "*tstqi" - [(set (cc0) (compare (match_operand:QI 0 "register_operand" "r") - (const_int 0)))] + [(set (cc0) + (compare (match_operand:QI 0 "register_operand" "r") + (const_int 0)))] "" "mov.b %X0,%X0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) (define_insn "*tsthi" - [(set (cc0) (compare (match_operand:HI 0 "register_operand" "r") - (const_int 0)))] + [(set (cc0) + (compare (match_operand:HI 0 "register_operand" "r") + (const_int 0)))] "" "mov.w %T0,%T0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) (define_insn "*tsthi_upper" - [(set (cc0) (compare (and:HI (match_operand:HI 0 "register_operand" "r") - (const_int -256)) - (const_int 0)))] + [(set (cc0) + (compare (and:HI (match_operand:HI 0 "register_operand" "r") + (const_int -256)) + (const_int 0)))] "" "mov.b %t0,%t0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) (define_insn "*tstsi" - [(set (cc0) (compare (match_operand:SI 0 "register_operand" "r") - (const_int 0)))] + [(set (cc0) + (compare (match_operand:SI 0 "register_operand" "r") + (const_int 0)))] "TARGET_H8300H || TARGET_H8300S" "mov.l %S0,%S0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) (define_insn "*tstsi_upper" - [(set (cc0) (compare (and:SI (match_operand:SI 0 "register_operand" "r") - (const_int -65536)) - (const_int 0)))] + [(set (cc0) + (compare (and:SI (match_operand:SI 0 "register_operand" "r") + (const_int -65536)) + (const_int 0)))] "" "mov.w %e0,%e0" [(set_attr "length" "2") @@ -1143,21 +1073,20 @@ (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ") (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))] "TARGET_H8300H || TARGET_H8300S" - "* { switch (which_alternative) { case 0: if (!TARGET_H8300SX) - return \"cmp.w %T1,%T0\"; + return "cmp.w %T1,%T0"; else - return \"cmp.w %T1:3,%T0\"; + return "cmp.w %T1:3,%T0"; case 1: - return \"cmp.w %T1,%T0\"; + return "cmp.w %T1,%T0"; default: gcc_unreachable (); } -}" +} [(set_attr "length_table" "short_immediate,addw") (set_attr "cc" "compare,compare")]) @@ -1166,21 +1095,20 @@ (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ") (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))] "TARGET_H8300H || TARGET_H8300S" - "* { switch (which_alternative) { case 0: if (!TARGET_H8300SX) - return \"cmp.l %S1,%S0\"; + return "cmp.l %S1,%S0"; else - return \"cmp.l %S1:3,%S0\"; + return "cmp.l %S1:3,%S0"; case 1: - return \"cmp.l %S1,%S0\"; + return "cmp.l %S1,%S0"; default: gcc_unreachable (); } -}" +} [(set_attr "length" "2,*") (set_attr "length_table" "*,addl") (set_attr "cc" "compare,compare")]) @@ -1240,7 +1168,10 @@ (match_operand 1 "const_int_gt_2_operand" "")))] "TARGET_H8300 && epilogue_completed" [(const_int 0)] - "split_adds_subs (HImode, operands); DONE;") + { + split_adds_subs (HImode, operands); + DONE; + }) (define_peephole2 [(match_scratch:HI 2 "r") @@ -1301,7 +1232,10 @@ (match_operand:HI 1 "two_insn_adds_subs_operand" "")))] "" [(const_int 0)] - "split_adds_subs (HImode, operands); DONE;") + { + split_adds_subs (HImode, operands); + DONE; + }) (define_expand "addsi3" [(set (match_operand:SI 0 "register_operand" "") @@ -1315,7 +1249,9 @@ (plus:SI (match_operand:SI 1 "register_operand" "%0,0") (match_operand:SI 2 "h8300_src_operand" "n,r")))] "TARGET_H8300" - "* return output_plussi (operands);" +{ + return output_plussi (operands); +} [(set (attr "length") (symbol_ref "compute_plussi_length (operands)")) (set (attr "cc") @@ -1326,7 +1262,9 @@ (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0") (match_operand:SI 2 "h8300_src_operand" "i,rQ")))] "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" - "* return output_plussi (operands);" +{ + return output_plussi (operands); +} [(set (attr "length") (symbol_ref "compute_plussi_length (operands)")) (set (attr "cc") @@ -1350,7 +1288,10 @@ (match_operand:SI 1 "two_insn_adds_subs_operand" "")))] "TARGET_H8300H || TARGET_H8300S" [(const_int 0)] - "split_adds_subs (SImode, operands); DONE;") + { + split_adds_subs (SImode, operands); + DONE; + }) ;; ---------------------------------------------------------------------- ;; SUBTRACT INSTRUCTIONS @@ -1406,10 +1347,10 @@ (minus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "h8300_src_operand" "")))] "" -{ - if (TARGET_H8300) - operands[2] = force_reg (SImode, operands[2]); -}) + { + if (TARGET_H8300) + operands[2] = force_reg (SImode, operands[2]); + }) (define_insn "*subsi3_h8300" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1442,11 +1383,10 @@ ;; intentionally-mismatched modes (match_operand:QI 2 "reg_or_nibble_operand" "")))] "TARGET_H8300H || TARGET_H8300S" - " -{ - if (GET_MODE (operands[2]) != VOIDmode) - operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); -}") + { + if (GET_MODE (operands[2]) != VOIDmode) + operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); + }) (define_insn "*mulqihi3_const" [(set (match_operand:HI 0 "register_operand" "=r") @@ -1472,11 +1412,10 @@ ;; intentionally-mismatched modes (match_operand:HI 2 "reg_or_nibble_operand" "")))] "TARGET_H8300H || TARGET_H8300S" - " -{ - if (GET_MODE (operands[2]) != VOIDmode) - operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); -}") + { + if (GET_MODE (operands[2]) != VOIDmode) + operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); + }) (define_insn "*mulhisi3_const" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1502,11 +1441,10 @@ ;; intentionally-mismatched modes (match_operand:QI 2 "reg_or_nibble_operand" "")))] "TARGET_H8300H || TARGET_H8300S" - " -{ - if (GET_MODE (operands[2]) != VOIDmode) - operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); -}") + { + if (GET_MODE (operands[2]) != VOIDmode) + operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); + }) (define_insn "*umulqihi3_const" [(set (match_operand:HI 0 "register_operand" "=r") @@ -1532,11 +1470,10 @@ ;; intentionally-mismatched modes (match_operand:HI 2 "reg_or_nibble_operand" "")))] "TARGET_H8300H || TARGET_H8300S" - " -{ - if (GET_MODE (operands[2]) != VOIDmode) - operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); -}") + { + if (GET_MODE (operands[2]) != VOIDmode) + operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); + }) (define_insn "*umulhisi3_const" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1559,6 +1496,7 @@ ;; We could have used mulu.[wl] here, but mulu.[lw] is only available ;; on a H8SX with a multiplier, whereas muls.w seems to be available ;; on all H8SX variants. + (define_insn "mulhi3" [(set (match_operand:HI 0 "register_operand" "=r") (mult:HI (match_operand:HI 1 "register_operand" "%0") @@ -1593,11 +1531,11 @@ (define_insn "umulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI - (ashiftrt:DI - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) - (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X"))) - (const_int 32))))] + (ashiftrt:DI + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X"))) + (const_int 32))))] "TARGET_H8300SX" "mulu/u.l\\t%S2,%S0" [(set_attr "length" "2") @@ -1610,6 +1548,7 @@ ;; ;; Unfortunately, if combine doesn't create a MAC instruction, this ;; insn must generate reasonably correct code. Egad. + (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a") (mult:SI @@ -1641,36 +1580,32 @@ (define_insn "udivhi3" [(set (match_operand:HI 0 "register_operand" "=r") - (udiv:HI - (match_operand:HI 1 "register_operand" "0") - (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))] + (udiv:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))] "TARGET_H8300SX" "divu.w\\t%T2,%T0" [(set_attr "length" "2")]) (define_insn "divhi3" [(set (match_operand:HI 0 "register_operand" "=r") - (div:HI - (match_operand:HI 1 "register_operand" "0") - (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))] + (div:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))] "TARGET_H8300SX" "divs.w\\t%T2,%T0" [(set_attr "length" "2")]) (define_insn "udivsi3" [(set (match_operand:SI 0 "register_operand" "=r") - (udiv:SI - (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))] + (udiv:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))] "TARGET_H8300SX" "divu.l\\t%S2,%S0" [(set_attr "length" "2")]) (define_insn "divsi3" [(set (match_operand:SI 0 "register_operand" "=r") - (div:SI - (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))] + (div:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))] "TARGET_H8300SX" "divs.l\\t%S2,%S0" [(set_attr "length" "2")]) @@ -1687,13 +1622,12 @@ (match_dup 1) (zero_extend:HI (match_dup 2)))))] "" - "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) - return \"divxu.b\\t%X2,%T0\"; + return "divxu.b\\t%X2,%T0"; else - return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\"; -}" + return "divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3"; +} [(set_attr "length" "4")]) (define_insn "divmodqi4" @@ -1708,13 +1642,12 @@ (match_dup 1) (sign_extend:HI (match_dup 2)))))] "TARGET_H8300H || TARGET_H8300S" - "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) - return \"divxs.b\\t%X2,%T0\"; + return "divxs.b\\t%X2,%T0"; else - return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\"; -}" + return "divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3"; +} [(set_attr "length" "6")]) (define_insn "udivmodhi4" @@ -1729,13 +1662,12 @@ (match_dup 1) (zero_extend:SI (match_dup 2)))))] "TARGET_H8300H || TARGET_H8300S" - "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) - return \"divxu.w\\t%T2,%S0\"; + return "divxu.w\\t%T2,%S0"; else - return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\"; -}" + return "divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3"; +} [(set_attr "length" "4")]) (define_insn "divmodhi4" @@ -1750,47 +1682,47 @@ (match_dup 1) (sign_extend:SI (match_dup 2)))))] "TARGET_H8300H || TARGET_H8300S" - "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) - return \"divxs.w\\t%T2,%S0\"; + return "divxs.w\\t%T2,%S0"; else - return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\"; -}" + return "divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3"; +} [(set_attr "length" "6")]) ;; ---------------------------------------------------------------------- ;; AND INSTRUCTIONS ;; ---------------------------------------------------------------------- + (define_insn "bclrqi_msx" [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU") (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") (match_operand:QI 2 "single_zero_operand" "Y0")))] - "TARGET_H8300SX" + "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])" "bclr\\t%W2,%0" [(set_attr "length" "8")]) (define_split - [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U") - (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") - (match_operand:HI 2 "single_zero_operand" "Y0")))] + [(set (match_operand:HI 0 "bit_register_indirect_operand") + (and:HI (match_operand:HI 1 "bit_register_indirect_operand") + (match_operand:HI 2 "single_zero_operand")))] "TARGET_H8300SX" [(set (match_dup 0) (and:QI (match_dup 1) (match_dup 2)))] -{ - if (abs (INTVAL (operands[2])) > 0xFF) - { - operands[0] = adjust_address (operands[0], QImode, 0); - operands[1] = adjust_address (operands[1], QImode, 0); - operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); - } - else - { - operands[0] = adjust_address (operands[0], QImode, 1); - operands[1] = adjust_address (operands[1], QImode, 1); - } -}) + { + if (abs (INTVAL (operands[2])) > 0xFF) + { + operands[0] = adjust_address (operands[0], QImode, 0); + operands[1] = adjust_address (operands[1], QImode, 0); + operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); + } + else + { + operands[0] = adjust_address (operands[0], QImode, 1); + operands[1] = adjust_address (operands[1], QImode, 1); + } + }) (define_insn "bclrhi_msx" [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m") @@ -1799,29 +1731,31 @@ "TARGET_H8300SX" "bclr\\t%W2,%0" [(set_attr "length" "8")]) + (define_insn "*andqi3_2" - [(set (match_operand:QI 0 "bit_operand" "=rQ,r") - (and:QI (match_operand:QI 1 "bit_operand" "%0,WU") - (match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))] + [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r") + (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU") + (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))] "TARGET_H8300SX" "@ - and %X2,%X0 - bfld %2,%1,%R0" - [(set_attr "length" "*,8") - (set_attr "length_table" "logicb,*") - (set_attr "cc" "set_znv,none_0hit")]) + bclr\\t %W2,%R0 + and %X2,%X0 + bfld %2,%1,%R0" + [(set_attr "length" "8,*,8") + (set_attr "length_table" "*,logicb,*") + (set_attr "cc" "none_0hit,set_znv,none_0hit")]) (define_insn "andqi3_1" - [(set (match_operand:QI 0 "bit_operand" "=r,U") + [(set (match_operand:QI 0 "bit_operand" "=U,r") (and:QI (match_operand:QI 1 "bit_operand" "%0,0") - (match_operand:QI 2 "h8300_src_operand" "rn,n")))] + (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))] "register_operand (operands[0], QImode) || single_zero_operand (operands[2], QImode)" "@ - and %X2,%X0 - bclr %W2,%R0" + bclr %W2,%R0 + and %X2,%X0" [(set_attr "length" "2,8") - (set_attr "cc" "set_znv,none_0hit")]) + (set_attr "cc" "none_0hit,set_znv")]) (define_expand "andqi3" [(set (match_operand:QI 0 "register_operand" "") @@ -1852,16 +1786,15 @@ (match_operand:HI 3 "single_one_operand" "n")) (match_operand:HI 1 "register_operand" "0")))] "" - "* { operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff); if (INTVAL (operands[3]) > 128) { operands[3] = GEN_INT (INTVAL (operands[3]) >> 8); - return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\"; + return "bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0"; } - return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\"; -}" + return "bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0"; +} [(set_attr "length" "6")]) (define_insn "*andorsi3" @@ -1870,16 +1803,15 @@ (match_operand:SI 3 "single_one_operand" "n")) (match_operand:SI 1 "register_operand" "0")))] "(INTVAL (operands[3]) & 0xffff) != 0" - "* { operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff); if (INTVAL (operands[3]) > 128) { operands[3] = GEN_INT (INTVAL (operands[3]) >> 8); - return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\"; + return "bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0"; } - return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\"; -}" + return "bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0"; +} [(set_attr "length" "6")]) (define_insn "*andorsi3_shift_8" @@ -1902,35 +1834,36 @@ ;; ---------------------------------------------------------------------- ;; OR INSTRUCTIONS ;; ---------------------------------------------------------------------- + (define_insn "bsetqi_msx" [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU") (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") (match_operand:QI 2 "single_one_operand" "Y2")))] - "TARGET_H8300SX" + "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])" "bset\\t%V2,%0" [(set_attr "length" "8")]) (define_split - [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U") - (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") - (match_operand:HI 2 "single_one_operand" "Y2")))] + [(set (match_operand:HI 0 "bit_register_indirect_operand") + (ior:HI (match_operand:HI 1 "bit_register_indirect_operand") + (match_operand:HI 2 "single_one_operand")))] "TARGET_H8300SX" [(set (match_dup 0) (ior:QI (match_dup 1) (match_dup 2)))] -{ - if (abs (INTVAL (operands[2])) > 0xFF) - { - operands[0] = adjust_address (operands[0], QImode, 0); - operands[1] = adjust_address (operands[1], QImode, 0); - operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); - } - else - { - operands[0] = adjust_address (operands[0], QImode, 1); - operands[1] = adjust_address (operands[1], QImode, 1); - } -}) + { + if (abs (INTVAL (operands[2])) > 0xFF) + { + operands[0] = adjust_address (operands[0], QImode, 0); + operands[1] = adjust_address (operands[1], QImode, 0); + operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); + } + else + { + operands[0] = adjust_address (operands[0], QImode, 1); + operands[1] = adjust_address (operands[1], QImode, 1); + } + }) (define_insn "bsethi_msx" [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m") @@ -1941,17 +1874,18 @@ [(set_attr "length" "8")]) (define_insn "iorqi3_1" - [(set (match_operand:QI 0 "bit_operand" "=rQ,U") + [(set (match_operand:QI 0 "bit_operand" "=U,rQ") (ior:QI (match_operand:QI 1 "bit_operand" "%0,0") - (match_operand:QI 2 "h8300_src_operand" "rQi,n")))] + (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))] "TARGET_H8300SX || register_operand (operands[0], QImode) || single_one_operand (operands[2], QImode)" "@ - or\\t%X2,%X0 - bset\\t%V2,%R0" - [(set_attr "length" "*,8") - (set_attr "length_table" "logicb,*") - (set_attr "cc" "set_znv,none_0hit")]) + bset\\t%V2,%R0 + or\\t%X2,%X0" + [(set_attr "length" "8,*") + (set_attr "length_table" "*,logicb") + (set_attr "cc" "none_0hit,set_znv")]) + (define_expand "iorqi3" [(set (match_operand:QI 0 "register_operand" "") @@ -1977,35 +1911,37 @@ ;; ---------------------------------------------------------------------- ;; XOR INSTRUCTIONS ;; ---------------------------------------------------------------------- + (define_insn "bnotqi_msx" [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU") (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") (match_operand:QI 2 "single_one_operand" "Y2")))] - "TARGET_H8300SX" + "TARGET_H8300SX + && rtx_equal_p (operands[0], operands[1])" "bnot\\t%V2,%0" [(set_attr "length" "8")]) (define_split - [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U") - (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") - (match_operand:HI 2 "single_one_operand" "Y2")))] + [(set (match_operand:HI 0 "bit_register_indirect_operand") + (xor:HI (match_operand:HI 1 "bit_register_indirect_operand") + (match_operand:HI 2 "single_one_operand")))] "TARGET_H8300SX" [(set (match_dup 0) (xor:QI (match_dup 1) (match_dup 2)))] -{ - if (abs (INTVAL (operands[2])) > 0xFF) - { - operands[0] = adjust_address (operands[0], QImode, 0); - operands[1] = adjust_address (operands[1], QImode, 0); - operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); - } - else - { - operands[0] = adjust_address (operands[0], QImode, 1); - operands[1] = adjust_address (operands[1], QImode, 1); - } -}) + { + if (abs (INTVAL (operands[2])) > 0xFF) + { + operands[0] = adjust_address (operands[0], QImode, 0); + operands[1] = adjust_address (operands[1], QImode, 0); + operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); + } + else + { + operands[0] = adjust_address (operands[0], QImode, 1); + operands[1] = adjust_address (operands[1], QImode, 1); + } + }) (define_insn "bnothi_msx" [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m") @@ -2016,17 +1952,17 @@ [(set_attr "length" "8")]) (define_insn "xorqi3_1" - [(set (match_operand:QI 0 "bit_operand" "=r,U") + [(set (match_operand:QI 0 "bit_operand" "=U,r") (xor:QI (match_operand:QI 1 "bit_operand" "%0,0") - (match_operand:QI 2 "h8300_src_operand" "rQi,n")))] + (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))] "TARGET_H8300SX || register_operand (operands[0], QImode) || single_one_operand (operands[2], QImode)" "@ - xor\\t%X2,%X0 - bnot\\t%V2,%R0" - [(set_attr "length" "*,8") - (set_attr "length_table" "logicb,*") - (set_attr "cc" "set_znv,none_0hit")]) + bnot\\t%V2,%R0 + xor\\t%X2,%X0" + [(set_attr "length" "8,*") + (set_attr "length_table" "*,logicb") + (set_attr "cc" "none_0hit,set_znv")]) (define_expand "xorqi3" [(set (match_operand:QI 0 "register_operand" "") @@ -2057,13 +1993,16 @@ ;; original H8300 don't have to split the 16-bit operand into a pair ;; of high/low instructions, so we can accept literal addresses, that ;; have to be loaded into a register on H8300. + (define_insn "*logicalhi3_sn" [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") (match_operator:HI 3 "bit_operator" - [(match_operand:HI 1 "h8300_dst_operand" "%0") - (match_operand:HI 2 "h8300_src_operand" "rQi")]))] + [(match_operand:HI 1 "h8300_dst_operand" "%0") + (match_operand:HI 2 "h8300_src_operand" "rQi")]))] "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)" - "* return output_logical_op (HImode, operands);" +{ + return output_logical_op (HImode, operands); +} [(set (attr "length") (symbol_ref "compute_logical_op_length (HImode, operands)")) (set (attr "cc") @@ -2072,10 +2011,12 @@ (define_insn "*logicalsi3_sn" [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") (match_operator:SI 3 "bit_operator" - [(match_operand:SI 1 "h8300_dst_operand" "%0") - (match_operand:SI 2 "h8300_src_operand" "rQi")]))] + [(match_operand:SI 1 "h8300_dst_operand" "%0") + (match_operand:SI 2 "h8300_src_operand" "rQi")]))] "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)" - "* return output_logical_op (SImode, operands);" +{ + return output_logical_op (SImode, operands); +} [(set (attr "length") (symbol_ref "compute_logical_op_length (SImode, operands)")) (set (attr "cc") @@ -2087,7 +2028,9 @@ [(match_operand:HI 1 "h8300_dst_operand" "%0") (match_operand:HI 2 "h8300_src_operand" "rQi")]))] "h8300_operands_match_p (operands)" - "* return output_logical_op (HImode, operands);" +{ + return output_logical_op (HImode, operands); +} [(set (attr "length") (symbol_ref "compute_logical_op_length (HImode, operands)")) (set (attr "cc") @@ -2096,10 +2039,12 @@ (define_insn "*logicalsi3" [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") (match_operator:SI 3 "bit_operator" - [(match_operand:SI 1 "h8300_dst_operand" "%0") - (match_operand:SI 2 "h8300_src_operand" "rQi")]))] + [(match_operand:SI 1 "h8300_dst_operand" "%0") + (match_operand:SI 2 "h8300_src_operand" "rQi")]))] "h8300_operands_match_p (operands)" - "* return output_logical_op (SImode, operands);" +{ + return output_logical_op (SImode, operands); +} [(set (attr "length") (symbol_ref "compute_logical_op_length (SImode, operands)")) (set (attr "cc") @@ -2127,14 +2072,13 @@ [(set (match_operand:HI 0 "register_operand" "") (neg:HI (match_operand:HI 1 "register_operand" "")))] "" - " -{ - if (TARGET_H8300) - { - emit_insn (gen_neghi2_h8300 (operands[0], operands[1])); - DONE; - } -}") + { + if (TARGET_H8300) + { + emit_insn (gen_neghi2_h8300 (operands[0], operands[1])); + DONE; + } + }) (define_expand "neghi2_h8300" [(set (match_dup 2) @@ -2143,7 +2087,9 @@ (set (match_operand:HI 0 "register_operand" "") (match_dup 2))] "" - "operands[2] = gen_reg_rtx (HImode);") + { + operands[2] = gen_reg_rtx (HImode); + }) (define_insn "*neghi2_h8300hs" [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") @@ -2157,14 +2103,13 @@ [(set (match_operand:SI 0 "register_operand" "") (neg:SI (match_operand:SI 1 "register_operand" "")))] "" - " -{ - if (TARGET_H8300) - { - emit_insn (gen_negsi2_h8300 (operands[0], operands[1])); - DONE; - } -}") + { + if (TARGET_H8300) + { + emit_insn (gen_negsi2_h8300 (operands[0], operands[1])); + DONE; + } + }) (define_expand "negsi2_h8300" [(set (match_dup 2) @@ -2173,7 +2118,9 @@ (set (match_operand:SI 0 "register_operand" "") (match_dup 2))] "" - "operands[2] = gen_reg_rtx (SImode);") + { + operands[2] = gen_reg_rtx (SImode); + }) (define_insn "*negsi2_h8300hs" [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") @@ -2299,7 +2246,10 @@ (match_operand:QI 2 "h8300_src_operand" "")])) (use (match_operand 3 ""))] "" - "h8300_expand_branch (operands); DONE;") + { + h8300_expand_branch (operands); + DONE; + }) (define_expand "cbranchhi4" [(use (match_operator 0 "ordered_comparison_operator" @@ -2307,15 +2257,15 @@ (match_operand:HI 2 "h8300_src_operand" "")])) (use (match_operand 3 ""))] "" - " -{ - /* Force operand1 into a register if we're compiling - for the H8/300. */ - if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx) - && TARGET_H8300) - operands[2] = force_reg (HImode, operands[2]); - h8300_expand_branch (operands); DONE; -}") + { + /* Force operand1 into a register if we're compiling + for the H8/300. */ + if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx) + && TARGET_H8300) + operands[2] = force_reg (HImode, operands[2]); + h8300_expand_branch (operands); + DONE; + }) (define_expand "cbranchsi4" [(use (match_operator 0 "ordered_comparison_operator" @@ -2323,16 +2273,18 @@ (match_operand:SI 2 "h8300_src_operand" "")])) (use (match_operand 3 ""))] "TARGET_H8300H || TARGET_H8300S" - "h8300_expand_branch (operands); DONE;") + { + h8300_expand_branch (operands); + DONE; + }) (define_insn "branch_true" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "" - "* { if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 && (GET_CODE (operands[1]) == GT @@ -2345,23 +2297,22 @@ } if (get_attr_length (insn) == 2) - return \"b%j1 %l0\"; + return "b%j1 %l0"; else if (get_attr_length (insn) == 4) - return \"b%j1 %l0:16\"; + return "b%j1 %l0:16"; else - return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\"; -}" + return "b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:"; +} [(set_attr "type" "branch") (set_attr "cc" "none")]) (define_insn "branch_false" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "" - "* { if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 && (GET_CODE (operands[1]) == GT @@ -2374,69 +2325,61 @@ } if (get_attr_length (insn) == 2) - return \"b%k1 %l0\"; + return "b%k1 %l0"; else if (get_attr_length (insn) == 4) - return \"b%k1 %l0:16\"; + return "b%k1 %l0:16"; else - return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\"; -}" + return "b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:"; +} [(set_attr "type" "branch") (set_attr "cc" "none")]) (define_insn "*brabc" [(set (pc) - (if_then_else - (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU") - (const_int 1) - (match_operand:QI 2 "immediate_operand" "n")) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] + (if_then_else (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU") + (const_int 1) + (match_operand:QI 2 "immediate_operand" "n")) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] "TARGET_H8300SX" - "* { switch (get_attr_length (insn) - h8300_insn_length_from_table (insn, operands)) { case 2: - return \"bra/bc %2,%R1,%l0\"; - + return "bra/bc %2,%R1,%l0"; case 4: - return \"bra/bc %2,%R1,%l0:16\"; - + return "bra/bc %2,%R1,%l0:16"; default: - return \"bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\"; + return "bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:"; } -}" +} [(set_attr "type" "bitbranch") (set_attr "length_table" "bitbranch") (set_attr "cc" "none")]) (define_insn "*brabs" [(set (pc) - (if_then_else - (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU") - (const_int 1) - (match_operand:QI 2 "immediate_operand" "n")) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] + (if_then_else (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU") + (const_int 1) + (match_operand:QI 2 "immediate_operand" "n")) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] "TARGET_H8300SX" - "* { switch (get_attr_length (insn) - h8300_insn_length_from_table (insn, operands)) { case 2: - return \"bra/bs %2,%R1,%l0\"; - + return "bra/bs %2,%R1,%l0"; case 4: - return \"bra/bs %2,%R1,%l0:16\"; - + return "bra/bs %2,%R1,%l0:16"; default: - return \"bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\"; + return "bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:"; } -}" +} [(set_attr "type" "bitbranch") (set_attr "length_table" "bitbranch") (set_attr "cc" "none")]) @@ -2447,12 +2390,11 @@ [(set (pc) (label_ref (match_operand 0 "" "")))] "" - "* { if (final_sequence != 0) { if (get_attr_length (insn) == 2) - return \"bra/s %l0\"; + return "bra/s %l0"; else { /* The branch isn't short enough to use bra/s. Output the @@ -2462,27 +2404,27 @@ bytes further than previously thought. The length-based test for bra vs. jump is very conservative though, so the branch will still be within range. */ - rtvec vec; + rtx_sequence *seq; int seen; - vec = XVEC (final_sequence, 0); + seq = final_sequence; final_sequence = 0; - final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 1, & seen); - final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 1, & seen); - INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1; - return \"\"; + final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, & seen); + final_scan_insn (seq->insn (0), asm_out_file, optimize, 1, & seen); + seq->insn (1)->set_deleted (); + return ""; } } else if (get_attr_length (insn) == 2) - return \"bra %l0\"; + return "bra %l0"; else if (get_attr_length (insn) == 4) - return \"bra %l0:16\"; + return "bra %l0:16"; else - return \"jmp @%l0\"; -}" + return "jmp @%l0"; +} [(set_attr "type" "branch") (set (attr "delay_slot") - (if_then_else (ne (symbol_ref "TARGET_H8300SX") (const_int 0)) + (if_then_else (match_test "TARGET_H8300SX") (const_string "jump") (const_string "none"))) (set_attr "cc" "none")]) @@ -2555,14 +2497,13 @@ [(call (match_operand:QI 0 "call_insn_operand" "or") (match_operand:HI 1 "general_operand" "g"))] "" - "* { if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF - && SYMBOL_REF_FLAG (XEXP (operands[0], 0))) - return \"jsr\\t@%0:8\"; + && (SYMBOL_REF_FLAGS (XEXP (operands[0], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) + return "jsr\\t@%0:8"; else - return \"jsr\\t%0\"; -}" + return "jsr\\t%0"; +} [(set_attr "type" "call") (set (attr "length") (if_then_else (match_operand:QI 0 "small_call_insn_operand" "") @@ -2579,14 +2520,13 @@ (call (match_operand:QI 1 "call_insn_operand" "or") (match_operand:HI 2 "general_operand" "g")))] "" - "* { if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF - && SYMBOL_REF_FLAG (XEXP (operands[1], 0))) - return \"jsr\\t@%1:8\"; + && (SYMBOL_REF_FLAGS (XEXP (operands[1], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) + return "jsr\\t@%1:8"; else - return \"jsr\\t%1\"; -}" + return "jsr\\t%1"; +} [(set_attr "type" "call") (set (attr "length") (if_then_else (match_operand:QI 0 "small_call_insn_operand" "") @@ -2642,44 +2582,45 @@ (define_insn "ldm_h8300sx" [(match_parallel 0 "h8300_ldm_parallel" - [(set (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "memory_operand" ""))])] + [(set (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "memory_operand" ""))])] "TARGET_H8300S" - { - operands[3] = SET_DEST (XVECEXP (operands[0], 0, - XVECLEN (operands[0], 0) - 2)); - return "ldm.l\t@er7+,%S1-%S3"; - } +{ + operands[3] = SET_DEST (XVECEXP (operands[0], 0, + XVECLEN (operands[0], 0) - 2)); + return "ldm.l\t@er7+,%S1-%S3"; +} [(set_attr "cc" "none") (set_attr "length" "4")]) (define_insn "stm_h8300sx" [(match_parallel 0 "h8300_stm_parallel" - [(set (match_operand:SI 1 "memory_operand" "") - (match_operand:SI 2 "register_operand" ""))])] + [(set (match_operand:SI 1 "memory_operand" "") + (match_operand:SI 2 "register_operand" ""))])] "TARGET_H8300S" - { - operands[3] = SET_SRC (XVECEXP (operands[0], 0, - XVECLEN (operands[0], 0) - 2)); - return "stm.l\t%S2-%S3,@-er7"; - } +{ + operands[3] = SET_SRC (XVECEXP (operands[0], 0, + XVECLEN (operands[0], 0) - 2)); + return "stm.l\t%S2-%S3,@-er7"; +} [(set_attr "cc" "none") (set_attr "length" "4")]) (define_insn "return_h8sx" [(match_parallel 0 "h8300_return_parallel" - [(return) - (set (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "memory_operand" ""))])] + [(return) + (set (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "memory_operand" ""))])] "TARGET_H8300SX" - { - operands[3] = SET_DEST (XVECEXP (operands[0], 0, - XVECLEN (operands[0], 0) - 2)); - if (h8300_current_function_interrupt_function_p ()) - return "rte/l\t%S1-%S3"; - else - return "rts/l\t%S1-%S3"; - } +{ + operands[3] = SET_DEST (XVECEXP (operands[0], 0, + XVECLEN (operands[0], 0) - 2)); + if (h8300_current_function_interrupt_function_p () + || h8300_current_function_monitor_function_p ()) + return "rte/l\t%S1-%S3"; + else + return "rts/l\t%S1-%S3"; +} [(set_attr "cc" "none") (set_attr "can_delay" "no") (set_attr "length" "2")]) @@ -2692,13 +2633,13 @@ (define_insn "*return_1" [(return)] "reload_completed" - "* { - if (h8300_current_function_interrupt_function_p ()) - return \"rte\"; + if (h8300_current_function_interrupt_function_p () + || h8300_current_function_monitor_function_p ()) + return "rte"; else - return \"rts\"; -}" + return "rts"; +} [(set_attr "cc" "none") (set_attr "can_delay" "no") (set_attr "length" "2")]) @@ -2706,26 +2647,39 @@ (define_expand "prologue" [(const_int 0)] "" - "h8300_expand_prologue (); DONE;") + { + h8300_expand_prologue (); + DONE; + }) (define_expand "epilogue" [(return)] "" - "h8300_expand_epilogue (); DONE;") + { + h8300_expand_epilogue (); + DONE; + }) (define_insn "monitor_prologue" [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)] "" - "* { if (TARGET_H8300) - return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\"; + return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr"; + else if (TARGET_H8300H && TARGET_NORMAL_MODE) + return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr"; else if (TARGET_H8300H) - return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\"; + return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr"; + else if (TARGET_H8300S && TARGET_NEXR ) + return "mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr"; + else if (TARGET_H8300S && TARGET_NEXR && TARGET_NORMAL_MODE) + return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr"; + else if (TARGET_H8300S && TARGET_NORMAL_MODE) + return "subs\\t#2,er7\;stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr"; else if (TARGET_H8300S) - return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\"; + return "stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr"; gcc_unreachable (); -}" +} [(set_attr "length" "20")]) ;; ---------------------------------------------------------------------- @@ -2770,7 +2724,9 @@ (match_dup 1)) (set (match_dup 0) (zero_extend:HI (match_dup 2)))] - "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));") + { + operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); + }) (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "") @@ -2800,28 +2756,32 @@ [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))] "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX - && reg_overlap_mentioned_p (operands[0], operands[1]) - && reload_completed" + && reg_overlap_mentioned_p (operands[0], operands[1]) + && reload_completed" [(set (match_dup 2) (match_dup 1)) (set (match_dup 3) (zero_extend:HI (match_dup 2))) (set (match_dup 0) (zero_extend:SI (match_dup 3)))] - "operands[2] = gen_lowpart (QImode, operands[0]); - operands[3] = gen_lowpart (HImode, operands[0]);") + { + operands[2] = gen_lowpart (QImode, operands[0]); + operands[3] = gen_lowpart (HImode, operands[0]); + }) (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))] "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX - && !reg_overlap_mentioned_p (operands[0], operands[1]) - && reload_completed" + && !reg_overlap_mentioned_p (operands[0], operands[1]) + && reload_completed" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) (match_dup 1))] - "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));") + { + operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); + }) (define_insn "*zero_extendqisi2_h8sx" [(set (match_operand:SI 0 "register_operand" "=r") @@ -2908,7 +2868,9 @@ (sign_extend:HI (match_dup 1))) (set (match_dup 0) (sign_extend:SI (match_dup 2)))] - "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));") + { + operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); + }) (define_insn "*extendqisi2_h8sx" [(set (match_operand:SI 0 "register_operand" "=r") @@ -2967,50 +2929,65 @@ (ashift:QI (match_operand:QI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;") + { + if (expand_a_shift (QImode, ASHIFT, operands)) + DONE; + }) (define_expand "ashrqi3" [(set (match_operand:QI 0 "register_operand" "") (ashiftrt:QI (match_operand:QI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;") + { + if (expand_a_shift (QImode, ASHIFTRT, operands)) + DONE; + }) (define_expand "lshrqi3" [(set (match_operand:QI 0 "register_operand" "") (lshiftrt:QI (match_operand:QI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;") + { + if (expand_a_shift (QImode, LSHIFTRT, operands)) + DONE; + }) (define_insn "" [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ") (match_operator:QI 3 "h8sx_unary_shift_operator" - [(match_operand:QI 1 "h8300_dst_operand" "0") - (match_operand:QI 2 "const_int_operand" "")]))] + [(match_operand:QI 1 "h8300_dst_operand" "0") + (match_operand:QI 2 "const_int_operand" "")]))] "h8300_operands_match_p (operands)" - { return output_h8sx_shift (operands, 'b', 'X'); } +{ + return output_h8sx_shift (operands, 'b', 'X'); +} [(set_attr "length_table" "unary") (set_attr "cc" "set_znv")]) (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (match_operator:QI 3 "h8sx_binary_shift_operator" - [(match_operand:QI 1 "register_operand" "0") - (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))] + [(match_operand:QI 1 "register_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))] "" - { return output_h8sx_shift (operands, 'b', 'X'); } +{ + return output_h8sx_shift (operands, 'b', 'X'); +} [(set_attr "length" "4") (set_attr "cc" "set_znv")]) (define_insn "*shiftqi" [(set (match_operand:QI 0 "register_operand" "=r,r") (match_operator:QI 3 "nshift_operator" - [ (match_operand:QI 1 "register_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "R,rn")])) + [(match_operand:QI 1 "register_operand" "0,0") + (match_operand:QI 2 "nonmemory_operand" "R,rn")])) (clobber (match_scratch:QI 4 "=X,&r"))] "" - "* return output_a_shift (operands);" +{ + return output_a_shift (operands); +} [(set (attr "length") (symbol_ref "compute_a_shift_length (insn, operands)")) (set (attr "cc") @@ -3023,50 +3000,65 @@ (ashift:HI (match_operand:HI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;") + { + if (expand_a_shift (HImode, ASHIFT, operands)) + DONE; + }) (define_expand "lshrhi3" [(set (match_operand:HI 0 "register_operand" "") (lshiftrt:HI (match_operand:HI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;") + { + if (expand_a_shift (HImode, LSHIFTRT, operands)) + DONE; + }) (define_expand "ashrhi3" [(set (match_operand:HI 0 "register_operand" "") (ashiftrt:HI (match_operand:HI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;") + { + if (expand_a_shift (HImode, ASHIFTRT, operands)) + DONE; + }) (define_insn "" [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") (match_operator:HI 3 "h8sx_unary_shift_operator" - [(match_operand:HI 1 "h8300_dst_operand" "0") - (match_operand:QI 2 "const_int_operand" "")]))] + [(match_operand:HI 1 "h8300_dst_operand" "0") + (match_operand:QI 2 "const_int_operand" "")]))] "h8300_operands_match_p (operands)" - { return output_h8sx_shift (operands, 'w', 'T'); } +{ + return output_h8sx_shift (operands, 'w', 'T'); +} [(set_attr "length_table" "unary") (set_attr "cc" "set_znv")]) (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (match_operator:HI 3 "h8sx_binary_shift_operator" - [(match_operand:HI 1 "register_operand" "0") - (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))] + [(match_operand:HI 1 "register_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))] "" - { return output_h8sx_shift (operands, 'w', 'T'); } +{ + return output_h8sx_shift (operands, 'w', 'T'); +} [(set_attr "length" "4") (set_attr "cc" "set_znv")]) (define_insn "*shifthi" [(set (match_operand:HI 0 "register_operand" "=r,r") (match_operator:HI 3 "nshift_operator" - [ (match_operand:HI 1 "register_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "S,rn")])) + [(match_operand:HI 1 "register_operand" "0,0") + (match_operand:QI 2 "nonmemory_operand" "S,rn")])) (clobber (match_scratch:QI 4 "=X,&r"))] "" - "* return output_a_shift (operands);" +{ + return output_a_shift (operands); +} [(set (attr "length") (symbol_ref "compute_a_shift_length (insn, operands)")) (set (attr "cc") @@ -3079,50 +3071,65 @@ (ashift:SI (match_operand:SI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;") + { + if (expand_a_shift (SImode, ASHIFT, operands)) + DONE; + }) (define_expand "lshrsi3" [(set (match_operand:SI 0 "register_operand" "") (lshiftrt:SI (match_operand:SI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;") + { + if (expand_a_shift (SImode, LSHIFTRT, operands)) + DONE; + }) (define_expand "ashrsi3" [(set (match_operand:SI 0 "register_operand" "") (ashiftrt:SI (match_operand:SI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;") + { + if (expand_a_shift (SImode, ASHIFTRT, operands)) + DONE; + }) (define_insn "" [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") (match_operator:SI 3 "h8sx_unary_shift_operator" - [(match_operand:SI 1 "h8300_dst_operand" "0") - (match_operand:QI 2 "const_int_operand" "")]))] + [(match_operand:SI 1 "h8300_dst_operand" "0") + (match_operand:QI 2 "const_int_operand" "")]))] "h8300_operands_match_p (operands)" - { return output_h8sx_shift (operands, 'l', 'S'); } +{ + return output_h8sx_shift (operands, 'l', 'S'); +} [(set_attr "length_table" "unary") (set_attr "cc" "set_znv")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 3 "h8sx_binary_shift_operator" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))] + [(match_operand:SI 1 "register_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))] "" - { return output_h8sx_shift (operands, 'l', 'S'); } +{ + return output_h8sx_shift (operands, 'l', 'S'); +} [(set_attr "length" "4") (set_attr "cc" "set_znv")]) (define_insn "*shiftsi" [(set (match_operand:SI 0 "register_operand" "=r,r") (match_operator:SI 3 "nshift_operator" - [ (match_operand:SI 1 "register_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "T,rn")])) + [(match_operand:SI 1 "register_operand" "0,0") + (match_operand:QI 2 "nonmemory_operand" "T,rn")])) (clobber (match_scratch:QI 4 "=X,&r"))] "" - "* return output_a_shift (operands);" +{ + return output_a_shift (operands); +} [(set (attr "length") (symbol_ref "compute_a_shift_length (insn, operands)")) (set (attr "cc") @@ -3134,13 +3141,12 @@ (define_split [(set (match_operand 0 "register_operand" "") (match_operator 2 "nshift_operator" - [(match_dup 0) - (match_operand:QI 1 "register_operand" "")])) + [(match_dup 0) + (match_operand:QI 1 "register_operand" "")])) (clobber (match_operand:QI 3 "register_operand" ""))] "epilogue_completed && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))" - [(set (cc0) (compare (match_dup 1) - (const_int 0))) + [(set (cc0) (compare (match_dup 1) (const_int 0))) (set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_dup 5)) @@ -3150,30 +3156,29 @@ [(set (match_dup 0) (match_op_dup 2 [(match_dup 0) (const_int 1)])) (clobber (scratch:QI))]) - (set (match_dup 1) - (plus:QI (match_dup 1) (const_int -1))) - (set (cc0) (compare (match_dup 1) - (const_int 0))) + (set (match_dup 1) (plus:QI (match_dup 1) (const_int -1))) + (set (cc0) (compare (match_dup 1) (const_int 0))) (set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_dup 4)) (pc))) (match_dup 5)] - "operands[4] = gen_label_rtx (); - operands[5] = gen_label_rtx ();") + { + operands[4] = gen_label_rtx (); + operands[5] = gen_label_rtx (); + }) (define_split [(set (match_operand 0 "register_operand" "") (match_operator 2 "nshift_operator" - [(match_dup 0) - (match_operand:QI 1 "register_operand" "")])) + [(match_dup 0) + (match_operand:QI 1 "register_operand" "")])) (clobber (match_operand:QI 3 "register_operand" ""))] "epilogue_completed && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))" [(set (match_dup 3) (match_dup 1)) - (set (cc0) (compare (match_dup 3) - (const_int 0))) + (set (cc0) (compare (match_dup 3) (const_int 0))) (set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_dup 5)) @@ -3183,17 +3188,17 @@ [(set (match_dup 0) (match_op_dup 2 [(match_dup 0) (const_int 1)])) (clobber (scratch:QI))]) - (set (match_dup 3) - (plus:QI (match_dup 3) (const_int -1))) - (set (cc0) (compare (match_dup 3) - (const_int 0))) + (set (match_dup 3) (plus:QI (match_dup 3) (const_int -1))) + (set (cc0) (compare (match_dup 3) (const_int 0))) (set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_dup 4)) (pc))) (match_dup 5)] - "operands[4] = gen_label_rtx (); - operands[5] = gen_label_rtx ();") + { + operands[4] = gen_label_rtx (); + operands[5] = gen_label_rtx (); + }) ;; ---------------------------------------------------------------------- ;; ROTATIONS @@ -3204,14 +3209,19 @@ (rotate:QI (match_operand:QI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_rotate (operands)) DONE;") + { + if (expand_a_rotate (operands)) + DONE; + }) (define_insn "rotlqi3_1" [(set (match_operand:QI 0 "register_operand" "=r") (rotate:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "immediate_operand" "")))] "" - "* return output_a_rotate (ROTATE, operands);" +{ + return output_a_rotate (ROTATE, operands); +} [(set (attr "length") (symbol_ref "compute_a_rotate_length (operands)"))]) @@ -3220,14 +3230,19 @@ (rotate:HI (match_operand:HI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" - "if (expand_a_rotate (operands)) DONE;") + { + if (expand_a_rotate (operands)) + DONE; + }) (define_insn "rotlhi3_1" [(set (match_operand:HI 0 "register_operand" "=r") (rotate:HI (match_operand:HI 1 "register_operand" "0") (match_operand:QI 2 "immediate_operand" "")))] "" - "* return output_a_rotate (ROTATE, operands);" +{ + return output_a_rotate (ROTATE, operands); +} [(set (attr "length") (symbol_ref "compute_a_rotate_length (operands)"))]) @@ -3236,14 +3251,19 @@ (rotate:SI (match_operand:SI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "TARGET_H8300H || TARGET_H8300S" - "if (expand_a_rotate (operands)) DONE;") + { + if (expand_a_rotate (operands)) + DONE; + }) (define_insn "rotlsi3_1" [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "0") (match_operand:QI 2 "immediate_operand" "")))] "TARGET_H8300H || TARGET_H8300S" - "* return output_a_rotate (ROTATE, operands);" +{ + return output_a_rotate (ROTATE, operands); +} [(set (attr "length") (symbol_ref "compute_a_rotate_length (operands)"))]) @@ -3284,7 +3304,7 @@ (const_int 1) (match_operand:HI 2 "const_int_operand" "n")))] "(TARGET_H8300 || TARGET_H8300SX) - && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" + && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0" [(set_attr "length" "8")]) @@ -3297,9 +3317,10 @@ (zero_extract:SI (match_operand:HI 1 "register_operand" "r") (const_int 1) (match_operand 2 "const_int_operand" "n")))] - "TARGET_H8300 - && INTVAL (operands[2]) < 16" - "* return output_simode_bld (0, operands);" + "TARGET_H8300 && INTVAL (operands[2]) < 16" +{ + return output_simode_bld (0, operands); +} [(set_attr "length" "8")]) (define_insn "*extzv_1_r_h8300hs" @@ -3307,9 +3328,10 @@ (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r") (const_int 1) (match_operand 2 "const_int_operand" "n,n")))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[2]) < 16" - "* return output_simode_bld (0, operands);" + "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16" +{ + return output_simode_bld (0, operands); +} [(set_attr "cc" "set_znv,set_znv") (set_attr "length" "8,6")]) @@ -3323,10 +3345,11 @@ (match_operand:HI 3 "const_int_operand" "n")) (const_int 1) (match_operand 2 "const_int_operand" "n")))] - "TARGET_H8300 - && INTVAL (operands[2]) < 16 + "TARGET_H8300 && INTVAL (operands[2]) < 16 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" - "* return output_simode_bld (1, operands);" +{ + return output_simode_bld (1, operands); +} [(set_attr "length" "8")]) (define_insn "*extzv_1_r_inv_h8300hs" @@ -3335,10 +3358,11 @@ (match_operand 3 "const_int_operand" "n,n")) (const_int 1) (match_operand 2 "const_int_operand" "n,n")))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[2]) < 16 - && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" - "* return output_simode_bld (1, operands);" + "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16 + && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" +{ + return output_simode_bld (1, operands); +} [(set_attr "cc" "set_znv,set_znv") (set_attr "length" "8,6")]) @@ -3348,65 +3372,61 @@ (match_operand:HI 2 "general_operand" "")) (match_operand:HI 3 "general_operand" ""))] "TARGET_H8300 || TARGET_H8300SX" - " -{ - if (TARGET_H8300SX) - { - if (GET_CODE (operands[1]) == CONST_INT - && GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[1]) <= 8 - && INTVAL (operands[2]) >= 0 - && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8 - && memory_operand (operands[0], GET_MODE (operands[0]))) - { - /* If the source operand is zero, it's better to use AND rather - than BFST. Likewise OR if the operand is all ones. */ - if (GET_CODE (operands[3]) == CONST_INT) - { - HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1; - if ((INTVAL (operands[3]) & mask) == 0) - FAIL; - if ((INTVAL (operands[3]) & mask) == mask) - FAIL; - } - if (! bit_memory_operand (operands[0], GET_MODE (operands[0]))) - { - if (!can_create_pseudo_p ()) - FAIL; - operands[0] = - replace_equiv_address (operands[0], - force_reg (Pmode, - XEXP (operands[0], 0))); - } - operands[3] = gen_lowpart (QImode, operands[3]); - if (! operands[3]) - FAIL; - if (! register_operand (operands[3], QImode)) - { - if (!can_create_pseudo_p ()) - FAIL; - operands[3] = force_reg (QImode, operands[3]); - } - emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0), - operands[3], operands[1], operands[2])); - DONE; - } - + { + if (TARGET_H8300SX) + { + if (GET_CODE (operands[1]) == CONST_INT + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[1]) <= 8 + && INTVAL (operands[2]) >= 0 + && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8 + && memory_operand (operands[0], GET_MODE (operands[0]))) + { + /* If the source operand is zero, it's better to use AND rather + than BFST. Likewise OR if the operand is all ones. */ + if (GET_CODE (operands[3]) == CONST_INT) + { + HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1; + if ((INTVAL (operands[3]) & mask) == 0) + FAIL; + if ((INTVAL (operands[3]) & mask) == mask) + FAIL; + } + if (! bit_memory_operand (operands[0], GET_MODE (operands[0]))) + { + if (!can_create_pseudo_p ()) + FAIL; + operands[0] = replace_equiv_address (operands[0], force_reg (Pmode, + XEXP (operands[0], 0))); + } + operands[3] = gen_lowpart (QImode, operands[3]); + if (! operands[3]) + FAIL; + if (! register_operand (operands[3], QImode)) + { + if (!can_create_pseudo_p ()) + FAIL; + operands[3] = force_reg (QImode, operands[3]); + } + emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0), + operands[3], operands[1], operands[2])); + DONE; + } + FAIL; + } + + /* We only have single bit bit-field instructions. */ + if (INTVAL (operands[1]) != 1) FAIL; - } - - /* We only have single bit bit-field instructions. */ - if (INTVAL (operands[1]) != 1) - FAIL; - - /* For now, we don't allow memory operands. */ - if (GET_CODE (operands[0]) == MEM - || GET_CODE (operands[3]) == MEM) - FAIL; - - if (GET_CODE (operands[3]) != REG) - operands[3] = force_reg (HImode, operands[3]); -}") + + /* For now, we don't allow memory operands. */ + if (GET_CODE (operands[0]) == MEM + || GET_CODE (operands[3]) == MEM) + FAIL; + + if (GET_CODE (operands[3]) != REG) + operands[3] = force_reg (HImode, operands[3]); + }) (define_insn "" [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r") @@ -3423,69 +3443,66 @@ (match_operand:HI 2 "general_operand" "") (match_operand:HI 3 "general_operand" "")))] "TARGET_H8300 || TARGET_H8300SX" - " -{ - if (TARGET_H8300SX) - { - if (GET_CODE (operands[2]) == CONST_INT - && GET_CODE (operands[3]) == CONST_INT - && INTVAL (operands[2]) <= 8 - && INTVAL (operands[3]) >= 0 - && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8 - && memory_operand (operands[1], QImode)) - { - rtx temp; - - /* Optimize the case where we're extracting into a paradoxical - subreg. It's only necessary to extend to the inner reg. */ - if (GET_CODE (operands[0]) == SUBREG - && subreg_lowpart_p (operands[0]) - && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) - < GET_MODE_SIZE (GET_MODE (operands[0]))) - && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) - == MODE_INT)) - operands[0] = SUBREG_REG (operands[0]); - - if (!can_create_pseudo_p ()) - temp = gen_lowpart (QImode, operands[0]); - else - temp = gen_reg_rtx (QImode); - if (! temp) - FAIL; - if (! bit_memory_operand (operands[1], QImode)) - { - if (!can_create_pseudo_p ()) - FAIL; - operands[1] = - replace_equiv_address (operands[1], - force_reg (Pmode, - XEXP (operands[1], 0))); - } - emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3])); - convert_move (operands[0], temp, 1); - DONE; - } + { + if (TARGET_H8300SX) + { + if (GET_CODE (operands[2]) == CONST_INT + && GET_CODE (operands[3]) == CONST_INT + && INTVAL (operands[2]) <= 8 + && INTVAL (operands[3]) >= 0 + && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8 + && memory_operand (operands[1], QImode)) + { + rtx temp; + + /* Optimize the case where we're extracting into a paradoxical + subreg. It's only necessary to extend to the inner reg. */ + if (GET_CODE (operands[0]) == SUBREG + && subreg_lowpart_p (operands[0]) + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) + < GET_MODE_SIZE (GET_MODE (operands[0]))) + && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) + == MODE_INT)) + operands[0] = SUBREG_REG (operands[0]); + + if (!can_create_pseudo_p ()) + temp = gen_lowpart (QImode, operands[0]); + else + temp = gen_reg_rtx (QImode); + if (! temp) + FAIL; + if (! bit_memory_operand (operands[1], QImode)) + { + if (!can_create_pseudo_p ()) + FAIL; + operands[1] = replace_equiv_address (operands[1], + force_reg (Pmode, XEXP (operands[1], 0))); + } + emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3])); + convert_move (operands[0], temp, 1); + DONE; + } + FAIL; + } + + /* We only have single bit bit-field instructions. */ + if (INTVAL (operands[2]) != 1) FAIL; - } - - /* We only have single bit bit-field instructions. */ - if (INTVAL (operands[2]) != 1) - FAIL; - - /* For now, we don't allow memory operands. */ - if (GET_CODE (operands[1]) == MEM) - FAIL; -}") + + /* For now, we don't allow memory operands. */ + if (GET_CODE (operands[1]) == MEM) + FAIL; + }) ;; BAND, BOR, and BXOR patterns (define_insn "" [(set (match_operand:HI 0 "bit_operand" "=Ur") (match_operator:HI 4 "bit_operator" - [(zero_extract:HI (match_operand:HI 1 "register_operand" "r") - (const_int 1) - (match_operand:HI 2 "immediate_operand" "n")) - (match_operand:HI 3 "bit_operand" "0")]))] + [(zero_extract:HI (match_operand:HI 1 "register_operand" "r") + (const_int 1) + (match_operand:HI 2 "immediate_operand" "n")) + (match_operand:HI 3 "bit_operand" "0")]))] "" "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1" [(set_attr "length" "6")]) @@ -3493,12 +3510,12 @@ (define_insn "" [(set (match_operand:HI 0 "bit_operand" "=Ur") (match_operator:HI 5 "bit_operator" - [(zero_extract:HI (match_operand:HI 1 "register_operand" "r") - (const_int 1) - (match_operand:HI 2 "immediate_operand" "n")) - (zero_extract:HI (match_operand:HI 3 "register_operand" "r") - (const_int 1) - (match_operand:HI 4 "immediate_operand" "n"))]))] + [(zero_extract:HI (match_operand:HI 1 "register_operand" "r") + (const_int 1) + (match_operand:HI 2 "immediate_operand" "n")) + (zero_extract:HI (match_operand:HI 3 "register_operand" "r") + (const_int 1) + (match_operand:HI 4 "immediate_operand" "n"))]))] "" "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3" [(set_attr "length" "6")]) @@ -3509,12 +3526,11 @@ (match_operand:QI 2 "immediate_operand" "n") (match_operand:QI 3 "immediate_operand" "n")))] "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8" - "* { operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3]))) - (1 << INTVAL (operands[3]))); - return \"bfld %2,%1,%R0\"; -}" + return "bfld %2,%1,%R0"; +} [(set_attr "cc" "none_0hit") (set_attr "length_table" "bitfield")]) @@ -3524,12 +3540,11 @@ (match_operand:QI 3 "immediate_operand" "n")) (match_operand:QI 1 "register_operand" "r"))] "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8" - "* { operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3]))) - (1 << INTVAL (operands[3]))); - return \"bfst %R1,%2,%0\"; -}" + return "bfst %R1,%2,%0"; +} [(set_attr "cc" "none_0hit") (set_attr "length_table" "bitfield")]) @@ -3539,7 +3554,10 @@ (match_operand:QI 3 "h8300_src_operand" "")])) (clobber (match_operand:HI 0 "register_operand"))] "TARGET_H8300SX" - "h8300_expand_store (operands); DONE;") + { + h8300_expand_store (operands); + DONE; + }) (define_expand "cstorehi4" [(use (match_operator 1 "eqne_operator" @@ -3547,7 +3565,10 @@ (match_operand:HI 3 "h8300_src_operand" "")])) (clobber (match_operand:HI 0 "register_operand"))] "TARGET_H8300SX" - "h8300_expand_store (operands); DONE;") + { + h8300_expand_store (operands); + DONE; + }) (define_expand "cstoresi4" [(use (match_operator 1 "eqne_operator" @@ -3555,7 +3576,10 @@ (match_operand:SI 3 "h8300_src_operand" "")])) (clobber (match_operand:HI 0 "register_operand"))] "TARGET_H8300SX" - "h8300_expand_store (operands); DONE;") + { + h8300_expand_store (operands); + DONE; + }) (define_insn "*bstzhireg" [(set (match_operand:HI 0 "register_operand" "=r") @@ -3565,12 +3589,10 @@ [(set_attr "cc" "clobber")]) (define_insn_and_split "*cmpstz" - [(set (zero_extract:QI - (match_operand:QI 0 "bit_memory_operand" "+WU,+WU") - (const_int 1) - (match_operand:QI 1 "immediate_operand" "n,n")) - (match_operator:QI - 2 "eqne_operator" + [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,WU") + (const_int 1) + (match_operand:QI 1 "immediate_operand" "n,n")) + (match_operator:QI 2 "eqne_operator" [(match_operand 3 "h8300_dst_operand" "r,rQ") (match_operand 4 "h8300_src_operand" "I,rQi")]))] "TARGET_H8300SX @@ -3583,7 +3605,9 @@ [(set (cc0) (match_dup 5)) (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1)) (match_op_dup:QI 2 [(cc0) (const_int 0)]))] - "operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);" + { + operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]); + } [(set_attr "cc" "set_znv,compare")]) (define_insn "*bstz" @@ -3608,35 +3632,32 @@ (define_insn_and_split "*cmpcondbset" [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU") - (if_then_else:QI - (match_operator - 1 "eqne_operator" - [(match_operand 2 "h8300_dst_operand" "r,rQ") - (match_operand 3 "h8300_src_operand" "I,rQi")]) - (ior:QI - (match_operand:QI 4 "bit_memory_operand" "0,0") - (match_operand:QI 5 "single_one_operand" "n,n")) - (match_dup 4)))] + (if_then_else:QI (match_operator 1 "eqne_operator" + [(match_operand 2 "h8300_dst_operand" "r,rQ") + (match_operand 3 "h8300_src_operand" "I,rQi")]) + (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0") + (match_operand:QI 5 "single_one_operand" "n,n")) + (match_dup 4)))] "TARGET_H8300SX" "#" "reload_completed" [(set (cc0) (match_dup 6)) (set (match_dup 0) - (if_then_else:QI - (match_op_dup 1 [(cc0) (const_int 0)]) - (ior:QI (match_dup 4) (match_dup 5)) (match_dup 4)))] - "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);" + (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)]) + (ior:QI (match_dup 4) (match_dup 5)) + (match_dup 4)))] + { + operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]); + } [(set_attr "cc" "set_znv,compare")]) (define_insn "*condbset" [(set (match_operand:QI 0 "bit_memory_operand" "=WU") - (if_then_else:QI - (match_operator:QI 2 "eqne_operator" - [(cc0) (const_int 0)]) - (ior:QI - (match_operand:QI 3 "bit_memory_operand" "0") - (match_operand:QI 1 "single_one_operand" "n")) - (match_dup 3)))] + (if_then_else:QI (match_operator:QI 2 "eqne_operator" + [(cc0) (const_int 0)]) + (ior:QI (match_operand:QI 3 "bit_memory_operand" "0") + (match_operand:QI 1 "single_one_operand" "n")) + (match_dup 3)))] "TARGET_H8300SX && reload_completed" "bset/%j2\t%V1,%0" [(set_attr "cc" "none_0hit") @@ -3644,35 +3665,32 @@ (define_insn_and_split "*cmpcondbclr" [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU") - (if_then_else:QI - (match_operator - 1 "eqne_operator" - [(match_operand 2 "h8300_dst_operand" "r,rQ") - (match_operand 3 "h8300_src_operand" "I,rQi")]) - (and:QI - (match_operand:QI 4 "bit_memory_operand" "0,0") - (match_operand:QI 5 "single_zero_operand" "n,n")) - (match_dup 4)))] + (if_then_else:QI (match_operator 1 "eqne_operator" + [(match_operand 2 "h8300_dst_operand" "r,rQ") + (match_operand 3 "h8300_src_operand" "I,rQi")]) + (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0") + (match_operand:QI 5 "single_zero_operand" "n,n")) + (match_dup 4)))] "TARGET_H8300SX" "#" "reload_completed" [(set (cc0) (match_dup 6)) (set (match_dup 0) - (if_then_else:QI - (match_op_dup 1 [(cc0) (const_int 0)]) - (and:QI (match_dup 4) (match_dup 5)) (match_dup 4)))] - "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);" + (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)]) + (and:QI (match_dup 4) (match_dup 5)) + (match_dup 4)))] + { + operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]); + } [(set_attr "cc" "set_znv,compare")]) (define_insn "*condbclr" [(set (match_operand:QI 0 "bit_memory_operand" "=WU") - (if_then_else:QI - (match_operator:QI 2 "eqne_operator" - [(cc0) (const_int 0)]) - (and:QI - (match_operand:QI 3 "bit_memory_operand" "0") - (match_operand:QI 1 "single_zero_operand" "n")) - (match_dup 3)))] + (if_then_else:QI (match_operator:QI 2 "eqne_operator" + [(cc0) (const_int 0)]) + (and:QI (match_operand:QI 3 "bit_memory_operand" "0") + (match_operand:QI 1 "single_zero_operand" "n")) + (match_dup 3)))] "TARGET_H8300SX && reload_completed" "bclr/%j2\t%W1,%0" [(set_attr "cc" "none_0hit") @@ -3680,40 +3698,36 @@ (define_insn_and_split "*cmpcondbsetreg" [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU") - (if_then_else:QI - (match_operator - 1 "eqne_operator" - [(match_operand 2 "h8300_dst_operand" "r,rQ") - (match_operand 3 "h8300_src_operand" "I,rQi")]) - (ior:QI - (match_operand:QI 4 "bit_memory_operand" "0,0") - (ashift:QI (const_int 1) - (match_operand:QI 5 "register_operand" "r,r"))) - (match_dup 4)))] + (if_then_else:QI (match_operator 1 "eqne_operator" + [(match_operand 2 "h8300_dst_operand" "r,rQ") + (match_operand 3 "h8300_src_operand" "I,rQi")]) + (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0") + (ashift:QI (const_int 1) + (match_operand:QI 5 "register_operand" "r,r"))) + (match_dup 4)))] "TARGET_H8300SX" "#" "reload_completed" [(set (cc0) (match_dup 6)) (set (match_dup 0) - (if_then_else:QI - (match_op_dup 1 [(cc0) (const_int 0)]) - (ior:QI (match_dup 4) - (ashift:QI (const_int 1) - (match_operand:QI 5 "register_operand" "r,r"))) - (match_dup 4)))] - "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);" + (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)]) + (ior:QI (match_dup 4) + (ashift:QI (const_int 1) + (match_operand:QI 5 "register_operand" "r,r"))) + (match_dup 4)))] + { + operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]); + } [(set_attr "cc" "set_znv,compare")]) (define_insn "*condbsetreg" [(set (match_operand:QI 0 "bit_memory_operand" "=WU") - (if_then_else:QI - (match_operator:QI 2 "eqne_operator" - [(cc0) (const_int 0)]) - (ior:QI - (match_operand:QI 3 "bit_memory_operand" "0") - (ashift:QI (const_int 1) - (match_operand:QI 1 "register_operand" "r"))) - (match_dup 3)))] + (if_then_else:QI (match_operator:QI 2 "eqne_operator" + [(cc0) (const_int 0)]) + (ior:QI (match_operand:QI 3 "bit_memory_operand" "0") + (ashift:QI (const_int 1) + (match_operand:QI 1 "register_operand" "r"))) + (match_dup 3)))] "TARGET_H8300SX && reload_completed" "bset/%j2\t%R1,%0" [(set_attr "cc" "none_0hit") @@ -3721,40 +3735,36 @@ (define_insn_and_split "*cmpcondbclrreg" [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU") - (if_then_else:QI - (match_operator - 1 "eqne_operator" - [(match_operand 2 "h8300_dst_operand" "r,rQ") - (match_operand 3 "h8300_src_operand" "I,rQi")]) - (and:QI - (match_operand:QI 4 "bit_memory_operand" "0,0") - (ashift:QI (const_int 1) - (match_operand:QI 5 "register_operand" "r,r"))) - (match_dup 4)))] + (if_then_else:QI (match_operator 1 "eqne_operator" + [(match_operand 2 "h8300_dst_operand" "r,rQ") + (match_operand 3 "h8300_src_operand" "I,rQi")]) + (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0") + (ashift:QI (const_int 1) + (match_operand:QI 5 "register_operand" "r,r"))) + (match_dup 4)))] "TARGET_H8300SX" "#" "reload_completed" [(set (cc0) (match_dup 6)) (set (match_dup 0) - (if_then_else:QI - (match_op_dup 1 [(cc0) (const_int 0)]) - (and:QI (match_dup 4) - (ashift:QI (const_int 1) - (match_operand:QI 5 "register_operand" "r,r"))) - (match_dup 4)))] - "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);" + (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)]) + (and:QI (match_dup 4) + (ashift:QI (const_int 1) + (match_operand:QI 5 "register_operand" "r,r"))) + (match_dup 4)))] + { + operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]); + } [(set_attr "cc" "set_znv,compare")]) (define_insn "*condbclrreg" [(set (match_operand:QI 0 "bit_memory_operand" "=WU") - (if_then_else:QI - (match_operator:QI 2 "eqne_operator" - [(cc0) (const_int 0)]) - (and:QI - (match_operand:QI 3 "bit_memory_operand" "0") - (ashift:QI (const_int 1) - (match_operand:QI 1 "register_operand" "r"))) - (match_dup 3)))] + (if_then_else:QI (match_operator:QI 2 "eqne_operator" + [(cc0) (const_int 0)]) + (and:QI (match_operand:QI 3 "bit_memory_operand" "0") + (ashift:QI (const_int 1) + (match_operand:QI 1 "register_operand" "r"))) + (match_dup 3)))] "TARGET_H8300SX && reload_completed" "bclr/%j2\t%R1,%0" [(set_attr "cc" "none_0hit") @@ -3772,8 +3782,7 @@ (const_int 1) (match_operand:SI 1 "const_int_operand" "n")) (match_operand:SI 2 "register_operand" "r"))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) < 16" + "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16" "bld\\t#0,%w2\;bst\\t%Z1,%Y0" [(set_attr "length" "4")]) @@ -3784,8 +3793,8 @@ (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (match_operand:SI 3 "const_int_operand" "n")))] "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) < 16 - && INTVAL (operands[3]) < 16" + && INTVAL (operands[1]) < 16 + && INTVAL (operands[3]) < 16" "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0" [(set_attr "length" "4")]) @@ -3795,8 +3804,7 @@ (match_operand:SI 1 "const_int_operand" "n")) (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16)))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) < 16" + "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16" "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0" [(set_attr "length" "6")]) @@ -3905,8 +3913,9 @@ (match_operand:SI 3 "const_int_operand" "n,n"))) (clobber (match_scratch:QI 4 "=X,&r"))] "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[2]) <= 15 - && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)" + && INTVAL (operands[2]) <= 15 + && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2])) + & 0xffff)" "#" "&& reload_completed" [(parallel [(set (match_dup 5) @@ -3915,7 +3924,9 @@ (clobber (match_dup 4))]) (set (match_dup 0) (zero_extend:SI (match_dup 5)))] - "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));") + { + operands[5] = gen_rtx_REG (HImode, REGNO (operands[0])); + }) ;; Accept (A >> 30) & 2 and the like. @@ -3925,13 +3936,12 @@ (match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 3 "single_one_operand" "n")))] "(TARGET_H8300H || TARGET_H8300S) - && exact_log2 (INTVAL (operands[3])) < 16 - && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31" - "* + && exact_log2 (INTVAL (operands[3])) < 16 + && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31" { operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); - return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\"; -}" + return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0"; +} [(set_attr "length" "8")]) (define_insn_and_split "*andsi3_lshiftrt_9_sb" @@ -3939,7 +3949,7 @@ (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (const_int 9)) (const_int 4194304)))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "#" "&& reload_completed" [(set (match_dup 0) @@ -3977,7 +3987,7 @@ (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r") (const_int 1)) (match_operand:SI 2 "register_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "#" "&& reload_completed" [(set (cc0) (compare (zero_extract:SI (match_dup 1) @@ -3993,14 +4003,16 @@ (plus:SI (match_dup 2) (const_int 1))) (match_dup 3)] - "operands[3] = gen_label_rtx ();") + { + operands[3] = gen_label_rtx (); + }) (define_insn_and_split "*addsi3_and_not_r_1" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r")) (const_int 1)) (match_operand:SI 2 "register_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "#" "&& reload_completed" [(set (cc0) (compare (zero_extract:SI (match_dup 1) @@ -4016,15 +4028,17 @@ (plus:SI (match_dup 2) (const_int 1))) (match_dup 3)] - "operands[3] = gen_label_rtx ();") + { + operands[3] = gen_label_rtx (); + }) ;; [ix]or:HI (define_insn "*ixorhi3_zext" [(set (match_operand:HI 0 "register_operand" "=r") (match_operator:HI 1 "iorxor_operator" - [(zero_extend:HI (match_operand:QI 2 "register_operand" "r")) - (match_operand:HI 3 "register_operand" "0")]))] + [(zero_extend:HI (match_operand:QI 2 "register_operand" "r")) + (match_operand:HI 3 "register_operand" "0")]))] "" "%c1.b\\t%X2,%s0" [(set_attr "length" "2")]) @@ -4034,8 +4048,8 @@ (define_insn "*ixorsi3_zext_qi" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "iorxor_operator" - [(zero_extend:SI (match_operand:QI 2 "register_operand" "r")) - (match_operand:SI 3 "register_operand" "0")]))] + [(zero_extend:SI (match_operand:QI 2 "register_operand" "r")) + (match_operand:SI 3 "register_operand" "0")]))] "" "%c1.b\\t%X2,%w0" [(set_attr "length" "2")]) @@ -4043,8 +4057,8 @@ (define_insn "*ixorsi3_zext_hi" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "iorxor_operator" - [(zero_extend:SI (match_operand:HI 2 "register_operand" "r")) - (match_operand:SI 3 "register_operand" "0")]))] + [(zero_extend:SI (match_operand:HI 2 "register_operand" "r")) + (match_operand:SI 3 "register_operand" "0")]))] "TARGET_H8300H || TARGET_H8300S" "%c1.w\\t%T2,%f0" [(set_attr "length" "2")]) @@ -4052,9 +4066,9 @@ (define_insn "*ixorsi3_ashift_16" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "iorxor_operator" - [(ashift:SI (match_operand:SI 2 "register_operand" "r") - (const_int 16)) - (match_operand:SI 3 "register_operand" "0")]))] + [(ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 16)) + (match_operand:SI 3 "register_operand" "0")]))] "TARGET_H8300H || TARGET_H8300S" "%c1.w\\t%f2,%e0" [(set_attr "length" "2")]) @@ -4062,9 +4076,9 @@ (define_insn "*ixorsi3_lshiftrt_16" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "iorxor_operator" - [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r") - (const_int 16)) - (match_operand:SI 3 "register_operand" "0")]))] + [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r") + (const_int 16)) + (match_operand:SI 3 "register_operand" "0")]))] "TARGET_H8300H || TARGET_H8300S" "%c1.w\\t%e2,%f0" [(set_attr "length" "2")]) @@ -4113,11 +4127,13 @@ (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0) (const_int 8))))] "(TARGET_H8300H || TARGET_H8300S) - && reload_completed - && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))" + && reload_completed + && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))" [(set (match_dup 0) (match_dup 3))] - "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));") + { + operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0)); + }) ;; ior:SI @@ -4133,11 +4149,10 @@ (define_insn_and_split "*iorsi3_two_qi_zext" [(set (match_operand:SI 0 "register_operand" "=&r") (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")) - (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0) (const_int 8)) (const_int 65280))))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "#" "&& reload_completed" [(set (match_dup 3) @@ -4146,7 +4161,9 @@ (const_int 8)))) (set (match_dup 0) (zero_extend:SI (match_dup 3)))] - "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));") + { + operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); + }) (define_insn "*iorsi3_e2f" [(set (match_operand:SI 0 "register_operand" "=r") @@ -4163,7 +4180,7 @@ (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0")) (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r")) (const_int 8))))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "#" "&& reload_completed" [(set (match_dup 3) @@ -4172,8 +4189,10 @@ (const_int 8)))) (set (match_dup 0) (sign_extend:SI (match_dup 3)))] - "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); - operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));") + { + operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); + operands[4] = gen_rtx_REG (HImode, REGNO (operands[2])); + }) (define_insn "*iorsi3_w" [(set (match_operand:SI 0 "register_operand" "=r,&r") @@ -4201,16 +4220,15 @@ (match_operand:SI 3 "single_one_operand" "n")) (match_operand:SI 4 "register_operand" "0")))] "(TARGET_H8300H || TARGET_H8300S) - && (INTVAL (operands[3]) & ~0xffff) == 0" - "* + && (INTVAL (operands[3]) & ~0xffff) == 0" { rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3])) - INTVAL (operands[2])); rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3]))); operands[2] = srcpos; operands[3] = dstpos; - return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\"; -}" + return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0"; +} [(set_attr "length" "6")]) (define_insn "*iorsi3_and_lshiftrt" @@ -4220,16 +4238,15 @@ (match_operand:SI 3 "single_one_operand" "n")) (match_operand:SI 4 "register_operand" "0")))] "(TARGET_H8300H || TARGET_H8300S) - && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0" - "* + && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0" { rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3])) + INTVAL (operands[2])); rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3]))); operands[2] = srcpos; operands[3] = dstpos; - return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\"; -}" + return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0"; +} [(set_attr "length" "6")]) (define_insn "*iorsi3_zero_extract" @@ -4238,8 +4255,7 @@ (const_int 1) (match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 3 "register_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[2]) < 16" + "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16" "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0" [(set_attr "length" "6")]) @@ -4249,7 +4265,7 @@ (const_int 30)) (const_int 2)) (match_operand:SI 2 "register_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0" [(set_attr "length" "8")]) @@ -4260,14 +4276,13 @@ (const_int 4194304)) (match_operand:SI 2 "register_operand" "0"))) (clobber (match_scratch:HI 3 "=&r"))] - "(TARGET_H8300H || TARGET_H8300S)" - "* + "TARGET_H8300H || TARGET_H8300S" { if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) - return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\"; + return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0"; else - return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\"; -}" + return "rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0"; +} [(set_attr "length" "10")]) ;; Used to OR the exponent of a float. @@ -4288,9 +4303,9 @@ (match_dup 0))) (clobber (match_operand:SI 2 "register_operand" ""))] "(TARGET_H8300H || TARGET_H8300S) - && epilogue_completed - && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[0]) != REGNO (operands[1])" + && epilogue_completed + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1])" [(parallel [(set (match_dup 3) (ashift:HI (match_dup 3) (const_int 7))) @@ -4299,7 +4314,9 @@ (ior:SI (ashift:SI (match_dup 1) (const_int 16)) (match_dup 0)))] - "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));") + { + operands[3] = gen_rtx_REG (HImode, REGNO (operands[1])); + }) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -4308,9 +4325,9 @@ (match_dup 0))) (clobber (match_operand:SI 2 "register_operand" ""))] "(TARGET_H8300H || TARGET_H8300S) - && epilogue_completed - && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[0]) != REGNO (operands[1]))" + && epilogue_completed + && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1]))" [(set (match_dup 2) (match_dup 1)) (parallel [(set (match_dup 3) @@ -4321,7 +4338,9 @@ (ior:SI (ashift:SI (match_dup 2) (const_int 16)) (match_dup 0)))] - "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));") + { + operands[3] = gen_rtx_REG (HImode, REGNO (operands[2])); + }) (define_insn "*iorsi2_and_1_lshiftrt_1" [(set (match_operand:SI 0 "register_operand" "=r") @@ -4339,7 +4358,7 @@ (const_int 16)) (ashift:SI (match_operand:SI 2 "register_operand" "r") (const_int 24))))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "#" "&& reload_completed" [(set (match_dup 3) @@ -4350,8 +4369,10 @@ (ashift:SI (match_dup 0) (const_int 16))) (clobber (scratch:QI))])] - "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); - operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));") + { + operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); + operands[4] = gen_rtx_REG (HImode, REGNO (operands[2])); + }) (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem" [(set (match_operand:SI 0 "register_operand" "=&r") @@ -4360,7 +4381,7 @@ (const_int 16711680)) (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0) (const_int 24))))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "#" "&& reload_completed" [(set (match_dup 3) @@ -4371,7 +4392,9 @@ (ashift:SI (match_dup 0) (const_int 16))) (clobber (scratch:QI))])] - "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));") + { + operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); + }) ;; Used to add the exponent of a float. @@ -4391,9 +4414,9 @@ (match_dup 0))) (clobber (match_operand:SI 2 "register_operand" ""))] "(TARGET_H8300H || TARGET_H8300S) - && epilogue_completed - && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[0]) != REGNO (operands[1])" + && epilogue_completed + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1])" [(parallel [(set (match_dup 3) (ashift:HI (match_dup 3) (const_int 7))) @@ -4402,7 +4425,9 @@ (plus:SI (mult:SI (match_dup 1) (const_int 65536)) (match_dup 0)))] - "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));") + { + operands[3] = gen_rtx_REG (HImode, REGNO (operands[1])); + }) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -4411,9 +4436,9 @@ (match_dup 0))) (clobber (match_operand:SI 2 "register_operand" ""))] "(TARGET_H8300H || TARGET_H8300S) - && epilogue_completed - && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[0]) != REGNO (operands[1]))" + && epilogue_completed + && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1]))" [(set (match_dup 2) (match_dup 1)) (parallel [(set (match_dup 3) @@ -4424,7 +4449,9 @@ (plus:SI (mult:SI (match_dup 2) (const_int 65536)) (match_dup 0)))] - "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));") + { + operands[3] = gen_rtx_REG (HImode, REGNO (operands[2])); + }) ;; ashift:SI @@ -4432,7 +4459,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0")) (const_int 7)))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" "#" "&& reload_completed" [(parallel [(set (match_dup 2) @@ -4445,7 +4472,9 @@ (ashiftrt:SI (match_dup 0) (const_int 1))) (clobber (scratch:QI))])] - "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));") + { + operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); + }) ;; Storing a part of HImode to QImode. @@ -4547,11 +4576,9 @@ [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255))) - (parallel - [(set (match_dup 0) - (lshiftrt:HI (match_dup 0) - (match_dup 1))) - (clobber (match_dup 2))])] + (parallel [(set (match_dup 0) + (lshiftrt:HI (match_dup 0) (match_dup 1))) + (clobber (match_dup 2))])] "") ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B. @@ -4568,11 +4595,9 @@ [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255))) - (parallel - [(set (match_dup 0) - (ashift:HI (match_dup 0) - (match_dup 1))) - (clobber (match_dup 2))])] + (parallel [(set (match_dup 0) + (ashift:HI (match_dup 0) (match_dup 1))) + (clobber (match_dup 2))])] "") ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B. @@ -4589,11 +4614,9 @@ [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255))) - (parallel - [(set (match_dup 0) - (lshiftrt:SI (match_dup 0) - (match_dup 1))) - (clobber (match_dup 2))])] + (parallel [(set (match_dup 0) + (lshiftrt:SI (match_dup 0) (match_dup 1))) + (clobber (match_dup 2))])] "") ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B. @@ -4610,11 +4633,9 @@ [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255))) - (parallel - [(set (match_dup 0) - (ashift:SI (match_dup 0) - (match_dup 1))) - (clobber (match_dup 2))])] + (parallel [(set (match_dup 0) + (ashift:SI (match_dup 0) (match_dup 1))) + (clobber (match_dup 2))])] "") ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B. @@ -4631,11 +4652,9 @@ [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) - (parallel - [(set (match_dup 0) - (lshiftrt:SI (match_dup 0) - (match_dup 1))) - (clobber (match_dup 2))])] + (parallel [(set (match_dup 0) + (lshiftrt:SI (match_dup 0) (match_dup 1))) + (clobber (match_dup 2))])] "") ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B. @@ -4652,11 +4671,9 @@ [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) - (parallel - [(set (match_dup 0) - (ashift:SI (match_dup 0) - (match_dup 1))) - (clobber (match_dup 2))])] + (parallel [(set (match_dup 0) + (ashift:SI (match_dup 0) (match_dup 1))) + (clobber (match_dup 2))])] "") ;; Convert a QImode push into an SImode push so that the @@ -4670,7 +4687,9 @@ "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))] - "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") + { + operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); + }) (define_peephole2 [(parallel [(set (reg:HI SP_REG) @@ -4680,7 +4699,9 @@ "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" [(set (mem:SI (pre_dec:HI (reg:HI SP_REG))) (match_dup 0))] - "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") + { + operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); + }) ;; Convert a HImode push into an SImode push so that the ;; define_peephole2 below can cram multiple pushes into one stm.l. @@ -4693,7 +4714,9 @@ "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))] - "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") + { + operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); + }) (define_peephole2 [(parallel [(set (reg:HI SP_REG) @@ -4703,7 +4726,9 @@ "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" [(set (mem:SI (pre_dec:HI (reg:HI SP_REG))) (match_dup 0))] - "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") + { + operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); + }) ;; Cram four pushes into stm.l. @@ -4867,9 +4892,9 @@ (match_operand:HI 2 "register_operand" "")))] "REG_P (operands[0]) && REG_P (operands[2]) && REGNO (operands[0]) != REGNO (operands[2]) - && (CONST_OK_FOR_J (INTVAL (operands[1])) - || CONST_OK_FOR_L (INTVAL (operands[1])) - || CONST_OK_FOR_N (INTVAL (operands[1])))" + && (satisfies_constraint_J (operands[1]) + || satisfies_constraint_L (operands[1]) + || satisfies_constraint_N (operands[1]))" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) @@ -4895,10 +4920,10 @@ (plus:SI (match_dup 0) (match_operand:SI 2 "register_operand" "")))] "(TARGET_H8300H || TARGET_H8300S) - && REG_P (operands[0]) && REG_P (operands[2]) - && REGNO (operands[0]) != REGNO (operands[2]) - && (CONST_OK_FOR_L (INTVAL (operands[1])) - || CONST_OK_FOR_N (INTVAL (operands[1])))" + && REG_P (operands[0]) && REG_P (operands[2]) + && REGNO (operands[0]) != REGNO (operands[2]) + && (satisfies_constraint_L (operands[1]) + || satisfies_constraint_N (operands[1]))" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) @@ -4924,14 +4949,14 @@ (plus:SI (match_dup 0) (match_operand:SI 2 "const_int_operand" "")))] "(TARGET_H8300H || TARGET_H8300S) - && REG_P (operands[0]) && REG_P (operands[1]) - && REGNO (operands[0]) != REGNO (operands[1]) - && !CONST_OK_FOR_L (INTVAL (operands[2])) - && !CONST_OK_FOR_N (INTVAL (operands[2])) - && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2]) - || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2]) - || INTVAL (operands[2]) == 0xffff - || INTVAL (operands[2]) == 0xfffe)" + && REG_P (operands[0]) && REG_P (operands[1]) + && REGNO (operands[0]) != REGNO (operands[1]) + && !satisfies_constraint_L (operands[2]) + && !satisfies_constraint_N (operands[2]) + && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2]) + || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2]) + || INTVAL (operands[2]) == 0xffff + || INTVAL (operands[2]) == 0xfffe)" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) @@ -4958,7 +4983,7 @@ (const_int 0))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_H8300H || TARGET_H8300S" @@ -4984,7 +5009,7 @@ (const_int 0))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_H8300H || TARGET_H8300S" @@ -5009,19 +5034,21 @@ (clobber (scratch:QI))]) (set (pc) (if_then_else (match_operator 1 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" [(set (cc0) (compare (match_dup 0) (const_int 0))) (set (pc) (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[3] = ((GET_CODE (operands[1]) == EQ) - ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx) - : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));") + { + operands[3] = ((GET_CODE (operands[1]) == EQ) + ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx) + : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx)); + }) ;; The next three peephole2's will try to transform ;; @@ -5041,8 +5068,8 @@ (and:SI (match_dup 2) (const_int 255)))] "(TARGET_H8300H || TARGET_H8300S) - && !reg_overlap_mentioned_p (operands[2], operands[1]) - && REGNO (operands[0]) == REGNO (operands[2])" + && !reg_overlap_mentioned_p (operands[2], operands[1]) + && REGNO (operands[0]) == REGNO (operands[2])" [(set (match_dup 2) (const_int 0)) (set (strict_low_part (match_dup 0)) @@ -5056,15 +5083,17 @@ (and:SI (match_dup 0) (const_int 255)))] "(TARGET_H8300H || TARGET_H8300S) - && !reg_overlap_mentioned_p (operands[0], operands[1]) - && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1])) - && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))" + && !reg_overlap_mentioned_p (operands[0], operands[1]) + && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1])) + && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) (match_dup 3))] - "operands[2] = gen_lowpart (QImode, operands[0]); - operands[3] = gen_lowpart (QImode, operands[1]);") + { + operands[2] = gen_lowpart (QImode, operands[0]); + operands[3] = gen_lowpart (QImode, operands[1]); + }) (define_peephole2 [(set (match_operand 0 "register_operand" "") @@ -5073,18 +5102,18 @@ (and:SI (match_dup 2) (match_operand:SI 3 "const_int_qi_operand" "")))] "(TARGET_H8300H || TARGET_H8300S) - && (GET_MODE (operands[0]) == QImode - || GET_MODE (operands[0]) == HImode - || GET_MODE (operands[0]) == SImode) - && GET_MODE (operands[0]) == GET_MODE (operands[1]) - && REGNO (operands[0]) == REGNO (operands[2]) - && !reg_overlap_mentioned_p (operands[2], operands[1]) - && !(GET_MODE (operands[1]) != QImode - && GET_CODE (operands[1]) == MEM - && !offsettable_memref_p (operands[1])) - && !(GET_MODE (operands[1]) != QImode - && GET_CODE (operands[1]) == MEM - && MEM_VOLATILE_P (operands[1]))" + && (GET_MODE (operands[0]) == QImode + || GET_MODE (operands[0]) == HImode + || GET_MODE (operands[0]) == SImode) + && GET_MODE (operands[0]) == GET_MODE (operands[1]) + && REGNO (operands[0]) == REGNO (operands[2]) + && !reg_overlap_mentioned_p (operands[2], operands[1]) + && !(GET_MODE (operands[1]) != QImode + && GET_CODE (operands[1]) == MEM + && !offsettable_memref_p (operands[1])) + && !(GET_MODE (operands[1]) != QImode + && GET_CODE (operands[1]) == MEM + && MEM_VOLATILE_P (operands[1]))" [(set (match_dup 2) (const_int 0)) (set (strict_low_part (match_dup 4)) @@ -5092,9 +5121,11 @@ (set (match_dup 2) (and:SI (match_dup 2) (match_dup 6)))] - "operands[4] = gen_lowpart (QImode, operands[0]); - operands[5] = gen_lowpart (QImode, operands[1]); - operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));") + { + operands[4] = gen_lowpart (QImode, operands[0]); + operands[5] = gen_lowpart (QImode, operands[1]); + operands[6] = GEN_INT (~0xff | INTVAL (operands[3])); + }) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -5123,17 +5154,19 @@ (and:SI (match_dup 0) (match_operand:SI 2 "const_int_operand" "")))] "(TARGET_H8300H || TARGET_H8300S) - && !MEM_VOLATILE_P (operands[1]) - && offsettable_memref_p (operands[1]) - && (INTVAL (operands[2]) & ~0xffff) == 0 - && INTVAL (operands[2]) != 255" + && !MEM_VOLATILE_P (operands[1]) + && offsettable_memref_p (operands[1]) + && (INTVAL (operands[2]) & ~0xffff) == 0 + && INTVAL (operands[2]) != 255" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))] - "operands[3] = gen_lowpart (HImode, operands[0]); - operands[4] = gen_lowpart (HImode, operands[1]);") + { + operands[3] = gen_lowpart (HImode, operands[0]); + operands[4] = gen_lowpart (HImode, operands[1]); + }) ;; Convert a memory comparison to a move if there is a scratch register. @@ -5154,7 +5187,7 @@ (set (cc0) (compare (match_operand:HI 0 "memory_operand" "") (const_int 0)))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" [(set (match_dup 1) (match_dup 0)) (set (cc0) (compare (match_dup 1) @@ -5166,7 +5199,7 @@ (set (cc0) (compare (match_operand:SI 0 "memory_operand" "") (const_int 0)))] - "(TARGET_H8300H || TARGET_H8300S)" + "TARGET_H8300H || TARGET_H8300S" [(set (match_dup 1) (match_dup 0)) (set (cc0) (compare (match_dup 1) @@ -5211,12 +5244,12 @@ (match_operand:HI 1 "incdec_operand" ""))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) != 0 - && peep2_reg_dead_p (1, operands[0])" + && INTVAL (operands[1]) != 0 + && peep2_reg_dead_p (1, operands[0])" [(set (match_dup 0) (unspec:HI [(match_dup 0) (match_dup 4)] @@ -5227,7 +5260,9 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[4] = GEN_INT (- INTVAL (operands[1]));") + { + operands[4] = GEN_INT (- INTVAL (operands[1])); + }) ;; Transform ;; @@ -5245,12 +5280,12 @@ (match_operand:HI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 2 "gtle_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 + && peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 || (TARGET_H8300S && INTVAL (operands[1]) == 3))" [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 0) @@ -5262,7 +5297,9 @@ (if_then_else (match_dup 2) (label_ref (match_dup 3)) (pc)))] - "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));") + { + operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); + }) ;; Transform ;; @@ -5280,12 +5317,12 @@ (match_operand:HI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 2 "gtuleu_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 + && peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 || (TARGET_H8300S && INTVAL (operands[1]) == 3))" [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 0) @@ -5297,13 +5334,11 @@ (if_then_else (match_dup 5) (label_ref (match_dup 3)) (pc)))] -{ - operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, - VOIDmode, - cc0_rtx, - const0_rtx); -}) + { + operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); + operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, + VOIDmode, cc0_rtx, const0_rtx); + }) ;; Transform ;; @@ -5321,7 +5356,7 @@ (const_int 255))) (set (pc) (if_then_else (match_operator 1 "gtle_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_H8300H || TARGET_H8300S" @@ -5350,7 +5385,7 @@ (const_int 255))) (set (pc) (if_then_else (match_operator 1 "gtuleu_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_H8300H || TARGET_H8300S" @@ -5361,12 +5396,10 @@ (if_then_else (match_dup 3) (label_ref (match_dup 2)) (pc)))] -{ - operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ, - VOIDmode, - cc0_rtx, - const0_rtx); -}) + { + operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ, + VOIDmode, cc0_rtx, const0_rtx); + }) ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve ;; the equivalent with shorter sequences. Here is the summary. Cases @@ -5446,12 +5479,12 @@ (match_operand:SI 1 "incdec_operand" ""))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) != 0 - && peep2_reg_dead_p (1, operands[0])" + && INTVAL (operands[1]) != 0 + && peep2_reg_dead_p (1, operands[0])" [(set (match_dup 0) (unspec:SI [(match_dup 0) (match_dup 4)] @@ -5462,7 +5495,9 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[4] = GEN_INT (- INTVAL (operands[1]));") + { + operands[4] = GEN_INT (- INTVAL (operands[1])); + }) ;; Transform ;; @@ -5480,15 +5515,15 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == -131072 - || INTVAL (operands[1]) == -65536 - || INTVAL (operands[1]) == 65536 - || INTVAL (operands[1]) == 131072)" + && peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == -131072 + || INTVAL (operands[1]) == -65536 + || INTVAL (operands[1]) == 65536 + || INTVAL (operands[1]) == 131072)" [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4))) @@ -5498,7 +5533,9 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[4] = GEN_INT (- INTVAL (operands[1]));") + { + operands[4] = GEN_INT (- INTVAL (operands[1])); + }) ;; Transform ;; @@ -5517,17 +5554,17 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1]) - || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1]) - || INTVAL (operands[1]) == 0x0000ffff) - && INTVAL (operands[1]) != 0 - && INTVAL (operands[1]) != 1 - && INTVAL (operands[1]) != 2" + && peep2_reg_dead_p (1, operands[0]) + && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1]) + || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1]) + || INTVAL (operands[1]) == 0x0000ffff) + && INTVAL (operands[1]) != 0 + && INTVAL (operands[1]) != 1 + && INTVAL (operands[1]) != 2" [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) @@ -5556,15 +5593,15 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && ((INTVAL (operands[1]) | 0x00ff) == -1 + && peep2_reg_dead_p (1, operands[0]) + && ((INTVAL (operands[1]) | 0x00ff) == -1 || (INTVAL (operands[1]) | 0xff00) == -1) - && INTVAL (operands[1]) != -1 - && INTVAL (operands[1]) != -2" + && INTVAL (operands[1]) != -1 + && INTVAL (operands[1]) != -2" [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4))) @@ -5576,7 +5613,9 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);") + { + operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1); + }) ;; Transform ;; @@ -5595,13 +5634,13 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == -2147483647 - 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))" + && peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == -2147483647 - 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))" [(set (match_dup 0) (rotate:SI (match_dup 0) (match_dup 4))) @@ -5615,7 +5654,9 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);") + { + operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2); + }) ;; Transform ;; @@ -5638,14 +5679,14 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 2 "gtle_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && !peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 + && !peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 || (TARGET_H8300S && INTVAL (operands[1]) == 3)) - && !same_cmp_preceding_p (insn)" + && !same_cmp_preceding_p (insn)" [(set (match_dup 4) (match_dup 0)) (parallel [(set (match_dup 4) @@ -5658,7 +5699,9 @@ (if_then_else (match_dup 2) (label_ref (match_dup 3)) (pc)))] - "operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));") + { + operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); + }) ;; Transform ;; @@ -5681,14 +5724,14 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 2 "gtuleu_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && !peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 + && !peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 || (TARGET_H8300S && INTVAL (operands[1]) == 3)) - && !same_cmp_preceding_p (insn)" + && !same_cmp_preceding_p (insn)" [(set (match_dup 4) (match_dup 0)) (parallel [(set (match_dup 4) @@ -5701,13 +5744,11 @@ (if_then_else (match_dup 6) (label_ref (match_dup 3)) (pc)))] -{ - operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); - operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, - VOIDmode, - cc0_rtx, - const0_rtx); -}) + { + operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, + VOIDmode, cc0_rtx, const0_rtx); + }) ;; Transform ;; @@ -5725,13 +5766,13 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 2 "gtle_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 3))" + && peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 3))" [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 4))) @@ -5742,7 +5783,9 @@ (if_then_else (match_dup 2) (label_ref (match_dup 3)) (pc)))] - "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));") + { + operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); + }) ;; Transform ;; @@ -5760,12 +5803,12 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 2 "gtuleu_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 + && peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 || (TARGET_H8300S && INTVAL (operands[1]) == 3))" [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) @@ -5777,13 +5820,11 @@ (if_then_else (match_dup 5) (label_ref (match_dup 3)) (pc)))] -{ - operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, - VOIDmode, - cc0_rtx, - const0_rtx); -}) + { + operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); + operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, + VOIDmode, cc0_rtx, const0_rtx); + }) ;; Transform ;; @@ -5802,18 +5843,18 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 2 "gtle_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && ((TARGET_H8300H && INTVAL (operands[1]) == 3) - || INTVAL (operands[1]) == 7 - || INTVAL (operands[1]) == 15 - || INTVAL (operands[1]) == 31 - || INTVAL (operands[1]) == 63 - || INTVAL (operands[1]) == 127 - || INTVAL (operands[1]) == 255)" + && peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 3 + || INTVAL (operands[1]) == 7 + || INTVAL (operands[1]) == 15 + || INTVAL (operands[1]) == 31 + || INTVAL (operands[1]) == 63 + || INTVAL (operands[1]) == 127 + || INTVAL (operands[1]) == 255)" [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 4))) @@ -5823,7 +5864,9 @@ (if_then_else (match_dup 2) (label_ref (match_dup 3)) (pc)))] - "operands[4] = GEN_INT (~INTVAL (operands[1]));") + { + operands[4] = GEN_INT (~INTVAL (operands[1])); + }) ;; Transform ;; @@ -5842,18 +5885,18 @@ (match_operand:SI 1 "const_int_operand" ""))) (set (pc) (if_then_else (match_operator 2 "gtuleu_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && ((TARGET_H8300H && INTVAL (operands[1]) == 3) - || INTVAL (operands[1]) == 7 - || INTVAL (operands[1]) == 15 - || INTVAL (operands[1]) == 31 - || INTVAL (operands[1]) == 63 - || INTVAL (operands[1]) == 127 - || INTVAL (operands[1]) == 255)" + && peep2_reg_dead_p (1, operands[0]) + && ((TARGET_H8300H && INTVAL (operands[1]) == 3) + || INTVAL (operands[1]) == 7 + || INTVAL (operands[1]) == 15 + || INTVAL (operands[1]) == 31 + || INTVAL (operands[1]) == 63 + || INTVAL (operands[1]) == 127 + || INTVAL (operands[1]) == 255)" [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 4))) @@ -5863,13 +5906,11 @@ (if_then_else (match_dup 5) (label_ref (match_dup 3)) (pc)))] -{ - operands[4] = GEN_INT (~INTVAL (operands[1])); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, - VOIDmode, - cc0_rtx, - const0_rtx); -}) + { + operands[4] = GEN_INT (~INTVAL (operands[1])); + operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, + VOIDmode, cc0_rtx, const0_rtx); + }) ;; Transform ;; @@ -5887,7 +5928,7 @@ (const_int 65535))) (set (pc) (if_then_else (match_operator 1 "gtle_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_H8300H || TARGET_H8300S" @@ -5916,7 +5957,7 @@ (const_int 65535))) (set (pc) (if_then_else (match_operator 1 "gtuleu_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_H8300H || TARGET_H8300S" @@ -5927,12 +5968,10 @@ (if_then_else (match_dup 3) (label_ref (match_dup 2)) (pc)))] -{ - operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ, - VOIDmode, - cc0_rtx, - const0_rtx); -}) + { + operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ, + VOIDmode, cc0_rtx, const0_rtx); + }) ;; Transform ;; @@ -5955,13 +5994,13 @@ (match_operand:SI 1 "incdec_operand" ""))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) != 0 - && !peep2_reg_dead_p (1, operands[0]) - && !same_cmp_following_p (insn)" + && INTVAL (operands[1]) != 0 + && !peep2_reg_dead_p (1, operands[0]) + && !same_cmp_following_p (insn)" [(set (match_dup 4) (match_dup 0)) (set (match_dup 4) @@ -5974,8 +6013,9 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[5] = GEN_INT (- INTVAL (operands[1]));") - + { + operands[5] = GEN_INT (- INTVAL (operands[1])); + }) ;; Narrow the mode of testing if possible. (define_peephole2 @@ -5986,7 +6026,7 @@ (const_int 0))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "peep2_reg_dead_p (2, operands[0])" @@ -5999,8 +6039,10 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0])); - operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);") + { + operands[4] = gen_rtx_REG (QImode, REGNO (operands[0])); + operands[5] = gen_int_mode (INTVAL (operands[1]), QImode); + }) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -6010,7 +6052,7 @@ (const_int 0))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "peep2_reg_dead_p (2, operands[0])" @@ -6023,8 +6065,10 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0])); - operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);") + { + operands[4] = gen_rtx_REG (QImode, REGNO (operands[0])); + operands[5] = gen_int_mode (INTVAL (operands[1]), QImode); + }) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -6034,7 +6078,7 @@ (const_int 0))) (set (pc) (if_then_else (match_operator 3 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "peep2_reg_dead_p (2, operands[0])" @@ -6047,8 +6091,10 @@ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) (label_ref (match_dup 2)) (pc)))] - "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0])); - operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);") + { + operands[4] = gen_rtx_REG (HImode, REGNO (operands[0])); + operands[5] = gen_int_mode (INTVAL (operands[1]), HImode); + }) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -6061,7 +6107,7 @@ (const_int 0))) (set (pc) (if_then_else (match_operator 4 "eqne_operator" - [(cc0) (const_int 0)]) + [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "peep2_reg_dead_p (3, operands[0]) @@ -6078,9 +6124,11 @@ (if_then_else (match_op_dup 4 [(cc0) (const_int 0)]) (label_ref (match_dup 3)) (pc)))] - "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0])); - operands[6] = gen_int_mode (INTVAL (operands[1]), QImode); - operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);") + { + operands[5] = gen_rtx_REG (QImode, REGNO (operands[0])); + operands[6] = gen_int_mode (INTVAL (operands[1]), QImode); + operands[7] = gen_int_mode (INTVAL (operands[2]), QImode); + }) ;; These triggers right at the end of allocation of locals in the ;; prologue (and possibly at other places). @@ -6097,7 +6145,7 @@ (set (mem:SI (reg:SI SP_REG)) (match_operand:SI 0 "register_operand" ""))] "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE - && REGNO (operands[0]) != SP_REG" + && REGNO (operands[0]) != SP_REG" [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))] "") @@ -6114,7 +6162,7 @@ (set (mem:SI (reg:SI SP_REG)) (match_operand:SI 0 "register_operand" ""))] "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE - && REGNO (operands[0]) != SP_REG" + && REGNO (operands[0]) != SP_REG" [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4))) @@ -6136,13 +6184,14 @@ ;; op src,dst ;; ;; if "reg" dies at the end of the sequence. + (define_peephole2 [(set (match_operand 0 "register_operand" "") (match_operand 1 "memory_operand" "")) (set (match_dup 0) (match_operator 2 "h8sx_binary_memory_operator" - [(match_dup 0) - (match_operand 3 "h8300_src_operand" "")])) + [(match_dup 0) + (match_operand 3 "h8300_src_operand" "")])) (set (match_operand 4 "memory_operand" "") (match_dup 0))] "0 /* Disable because it breaks compiling fp-bit.c. */ @@ -6168,13 +6217,14 @@ ;; op src,dst ;; ;; if "reg" dies in the second insn. + (define_peephole2 [(set (match_operand 0 "register_operand" "") (match_operand 1 "h8300_src_operand" "")) (set (match_operand 2 "h8300_dst_operand" "") (match_operator 3 "h8sx_binary_memory_operator" - [(match_operand 4 "h8300_dst_operand" "") - (match_dup 0)]))] + [(match_operand 4 "h8300_dst_operand" "") + (match_dup 0)]))] "0 /* Disable because it breaks compiling fp-bit.c. */ && TARGET_H8300SX && peep2_reg_dead_p (2, operands[0]) @@ -6197,12 +6247,13 @@ ;; op dst ;; ;; if "reg" dies at the end of the sequence. + (define_peephole2 [(set (match_operand 0 "register_operand" "") (match_operand 1 "memory_operand" "")) (set (match_dup 0) (match_operator 2 "h8sx_unary_memory_operator" - [(match_dup 0)])) + [(match_dup 0)])) (set (match_operand 3 "memory_operand" "") (match_dup 0))] "TARGET_H8300SX @@ -6226,6 +6277,7 @@ ;; cmp src1,src2 ;; ;; if "reg" dies in the comparison. + (define_peephole2 [(set (match_operand 0 "register_operand" "") (match_operand 1 "h8300_dst_operand" "")) @@ -6241,6 +6293,7 @@ (match_dup 2)))]) ;; Likewise for the second operand. + (define_peephole2 [(set (match_operand 0 "register_operand" "") (match_operand 1 "h8300_src_operand" "")) @@ -6255,6 +6308,7 @@ (match_dup 1)))]) ;; Combine two moves. + (define_peephole2 [(set (match_operand 0 "register_operand" "") (match_operand 1 "h8300_src_operand" "")) @@ -6265,3 +6319,5 @@ && !reg_overlap_mentioned_p (operands[0], operands[2])" [(set (match_dup 2) (match_dup 1))]) + +