--- a/gcc/config/iq2000/iq2000.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/iq2000/iq2000.md	Fri Oct 27 22:46:09 2017 +0900
@@ -1,5 +1,5 @@
 ;;  iq2000.md	     Machine Description for Vitesse IQ2000 processors
-;;  Copyright (C) 2003, 2004, 2005, 2007, 2010 Free Software Foundation, Inc.
+;;  Copyright (C) 2003-2017 Free Software Foundation, Inc.
 
 ;; This file is part of GCC.
 
@@ -133,7 +133,7 @@
 ;; instruction takes a 28-bit value, but that value is not an offset.
 ;; Instead, it's bitwise-ored with the high-order four bits of the
 ;; instruction in the delay slot, which means it cannot be used to
-;; cross a 256MB boundary.  We could fall back back on the jr,
+;; cross a 256MB boundary.  We could fall back on the jr
 ;; instruction which allows full access to the entire address space,
 ;; but we do not do so at present.
 
@@ -161,7 +161,7 @@
 
 (define_attr "branch_likely" "no,yes"
   (const
-   (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
+   (if_then_else (match_test "GENERATE_BRANCHLIKELY")
 		 (const_string "yes")
 		 (const_string "no"))))
 
@@ -260,7 +260,7 @@
   "")
 
 (define_insn "addsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
 		 (match_operand:SI 2 "arith_operand" "d,I")))]
   ""
@@ -286,7 +286,7 @@
   "")
 
 (define_insn "subsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
 		  (match_operand:SI 2 "arith_operand" "d,I")))]
   ""
@@ -691,12 +691,11 @@
 {
   if (iq2000_check_split (operands[1], SImode))
     {
-      enum machine_mode mode = GET_MODE (operands[0]);
+      machine_mode mode = GET_MODE (operands[0]);
       rtx tem = ((reload_in_progress | reload_completed)
 		 ? operands[0] : gen_reg_rtx (mode));
 
-      emit_insn (gen_rtx_SET (VOIDmode, tem,
-			      gen_rtx_HIGH (mode, operands[1])));
+      emit_insn (gen_rtx_SET (tem, gen_rtx_HIGH (mode, operands[1])));
 
       operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
     }
@@ -722,8 +721,7 @@
       rtx tem = ((reload_in_progress | reload_completed)
 		 ? operands[0] : gen_reg_rtx (SImode));
 
-      emit_insn (gen_rtx_SET (VOIDmode, tem,
-			      gen_rtx_HIGH (SImode, operands[1])));
+      emit_insn (gen_rtx_SET (tem, gen_rtx_HIGH (SImode, operands[1])));
       operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]);
     }
 }")
@@ -851,11 +849,9 @@
   ""
   "*
 {
-  REAL_VALUE_TYPE r;
   long i;
 
-  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
-  REAL_VALUE_TO_TARGET_SINGLE (r, i);
+  REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[2]), i);
   operands[2] = GEN_INT (i);
   return \"addiu\\t%0,%1,%%lo(%2) # low\";
 }"
@@ -868,11 +864,9 @@
   ""
   "*
 {
-  REAL_VALUE_TYPE r;
   long i;
 
-  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-  REAL_VALUE_TO_TARGET_SINGLE (r, i);
+  REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), i);
   operands[1] = GEN_INT (i);
   return \"lui\\t%0,%%hi(%1) # high\";
 }"
@@ -1001,10 +995,10 @@
 (define_expand "cbranchsi4"
   [(set (pc)
         (if_then_else
-         (match_operator:SI 0 "ordered_comparison_operator"
-                            [(match_operand:SI 1 "register_operand")
-                             (match_operand:SI 2 "reg_or_const_operand")])
-	 (label_ref (match_operand:SI 3 ""))
+         (match_operator 0 "ordered_comparison_operator"
+			 [(match_operand:SI 1 "register_operand")
+			  (match_operand:SI 2 "reg_or_const_operand")])
+	 (label_ref (match_operand 3 ""))
 	 (pc)))]
   ""
   "
@@ -1019,9 +1013,9 @@
 (define_insn "branch_zero"
   [(set (pc)
 	(if_then_else
-         (match_operator:SI 0 "cmp_op"
-			    [(match_operand:SI 2 "register_operand" "d")
-			     (const_int 0)])
+         (match_operator 0 "cmp_op"
+			 [(match_operand:SI 2 "register_operand" "d")
+			  (const_int 0)])
         (label_ref (match_operand 1 "" ""))
         (pc)))]
   ""
@@ -1040,9 +1034,9 @@
 (define_insn "branch_zero_inverted"
   [(set (pc)
 	(if_then_else
-         (match_operator:SI 0 "cmp_op"
-		            [(match_operand:SI 2 "register_operand" "d")
-			     (const_int 0)])
+         (match_operator 0 "cmp_op"
+			 [(match_operand:SI 2 "register_operand" "d")
+			  (const_int 0)])
         (pc)
         (label_ref (match_operand 1 "" ""))))]
   ""
@@ -1063,9 +1057,9 @@
 (define_insn "branch_equality"
   [(set (pc)
 	(if_then_else
-         (match_operator:SI 0 "equality_op"
-		   	    [(match_operand:SI 2 "register_operand" "d")
-			     (match_operand:SI 3 "register_operand" "d")])
+         (match_operator 0 "equality_op"
+			 [(match_operand:SI 2 "register_operand" "d")
+			  (match_operand:SI 3 "register_operand" "d")])
          (label_ref (match_operand 1 "" ""))
          (pc)))]
   ""
@@ -1084,9 +1078,9 @@
 (define_insn "branch_equality_inverted"
   [(set (pc)
 	(if_then_else
-         (match_operator:SI 0 "equality_op"
-		   	    [(match_operand:SI 2 "register_operand" "d")
-			     (match_operand:SI 3 "register_operand" "d")])
+         (match_operator 0 "equality_op"
+			 [(match_operand:SI 2 "register_operand" "d")
+			  (match_operand:SI 3 "register_operand" "d")])
          (pc)
          (label_ref (match_operand 1 "" ""))))]
   ""
@@ -1145,7 +1139,7 @@
 	     (const_int 0))
 	 (match_operand 2 "pc_or_label_operand" "")
 	 (match_operand 3 "pc_or_label_operand" "")))]
-  ""
+  "0"
   "bb%A2\\t%0(31-%1),%P2%P3"
   [(set_attr "length" "4")
    (set_attr "type" "branch")])
@@ -1159,7 +1153,7 @@
 	     (const_int 0))
 	 (match_operand 2 "pc_or_label_operand" "")
 	 (match_operand 3 "pc_or_label_operand" "")))]
-  ""
+  "0"
   "bb%A3\\t%0(31-%1),%P2%P3"
   [(set_attr "length" "4")
    (set_attr "type" "branch")])
@@ -1229,7 +1223,7 @@
    (set_attr "mode"	"SI")])
 
 (define_insn "sgt_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(gt:SI (match_operand:SI 1 "register_operand" "d,d")
 	       (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
   ""
@@ -1240,7 +1234,7 @@
    (set_attr "mode"	"SI,SI")])
 
 (define_insn "slt_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(lt:SI (match_operand:SI 1 "register_operand" "d,d")
 	       (match_operand:SI 2 "arith_operand" "d,I")))]
   ""
@@ -1273,7 +1267,7 @@
    (set_attr "mode"	"SI")])
 
 (define_insn "sltu_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(ltu:SI (match_operand:SI 1 "register_operand" "d,d")
 		(match_operand:SI 2 "arith_operand" "d,I")))]
   ""
@@ -1398,9 +1392,8 @@
 	(plus:SI (match_operand:SI 0 "register_operand" "d")
 		 (label_ref:SI (match_operand 1 "" ""))))
    (use (label_ref:SI (match_dup 1)))]
-  "!(Pmode == DImode) && next_active_insn (insn) != 0
-   && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
-   && PREV_INSN (next_active_insn (insn)) == operands[1]"
+  "!(Pmode == DImode) && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
+   && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC"
   "*
 {
   return \"j\\t%0\";
@@ -1711,7 +1704,7 @@
     {
       int i;
 
-      emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
+      emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
 
       for (i = 0; i < XVECLEN (operands[2], 0); i++)
 	{