--- a/gcc/config/mips/10000.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/mips/10000.md	Fri Oct 27 22:46:09 2017 +0900
@@ -1,5 +1,5 @@
 ;; DFA-based pipeline description for the VR1x000.
-;;   Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
+;;   Copyright (C) 2005-2017 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 
@@ -68,21 +68,19 @@
 ;; Miscellaneous arith goes here too (this is a guess).
 (define_insn_reservation "r10k_arith" 1
   (and (eq_attr "cpu" "r10000")
-       (eq_attr "type" "arith,mthilo,slt,clz,const,nop,trap,logical"))
+       (eq_attr "type" "arith,mthi,mtlo,slt,clz,const,nop,trap,logical"))
   "r10k_alu1 | r10k_alu2")
 
 ;; We treat mfhilo differently, because we need to know when
 ;; it's HI and when it's LO.
 (define_insn_reservation "r10k_mfhi" 1
   (and (eq_attr "cpu" "r10000")
-       (and (eq_attr "type" "mfhilo")
-            (not (match_operand 1 "lo_operand"))))
+       (eq_attr "type" "mfhi"))
   "r10k_alu1 | r10k_alu2")
 
 (define_insn_reservation "r10k_mflo" 1
   (and (eq_attr "cpu" "r10000")
-       (and (eq_attr "type" "mfhilo")
-            (match_operand 1 "lo_operand")))
+       (eq_attr "type" "mflo"))
   "r10k_alu1 | r10k_alu2")
 
 
@@ -249,5 +247,5 @@
 ;; Handle unknown/multi insns here (this is a guess).
 (define_insn_reservation "r10k_unknown" 1
   (and (eq_attr "cpu" "r10000")
-       (eq_attr "type" "unknown,multi"))
+       (eq_attr "type" "unknown,multi,atomic,syncloop"))
   "r10k_alu1 + r10k_alu2")