Mercurial > hg > CbC > CbC_gcc
diff gcc/config/rs6000/6xx.md @ 111:04ced10e8804
gcc 7
author | kono |
---|---|
date | Fri, 27 Oct 2017 22:46:09 +0900 |
parents | 77e2b8dfacca |
children | 84e7813d76e9 |
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--- a/gcc/config/rs6000/6xx.md Sun Aug 21 07:07:55 2011 +0900 +++ b/gcc/config/rs6000/6xx.md Fri Oct 27 22:46:09 2017 +0900 @@ -1,6 +1,6 @@ ;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620, ;; and PowerPC 630 processors. -;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. +;; Copyright (C) 2003-2017 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -48,17 +48,17 @@ ;; Four insns can be dispatched per cycle. (define_insn_reservation "ppc604-load" 2 - (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") + (and (eq_attr "type" "load") (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) "lsu_6xx") (define_insn_reservation "ppc604-fpload" 3 - (and (eq_attr "type" "fpload,fpload_ux,fpload_u") + (and (eq_attr "type" "fpload") (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) "lsu_6xx") (define_insn_reservation "ppc604-store" 3 - (and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u") + (and (eq_attr "type" "store,fpstore") (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) "lsu_6xx") @@ -73,8 +73,9 @@ "lsu_6xx") (define_insn_reservation "ppc604-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts,isel") + (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel") + (and (eq_attr "type" "add,logical,shift,exts") + (eq_attr "dot" "no"))) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) "iu1_6xx|iu2_6xx") @@ -89,58 +90,66 @@ "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx") (define_insn_reservation "ppc604-imul" 4 - (and (eq_attr "type" "imul,imul2,imul3,imul_compare") + (and (eq_attr "type" "mul") (eq_attr "cpu" "ppc604")) "mciu_6xx*2") (define_insn_reservation "ppc604e-imul" 2 - (and (eq_attr "type" "imul,imul2,imul3,imul_compare") + (and (eq_attr "type" "mul") (eq_attr "cpu" "ppc604e")) "mciu_6xx") (define_insn_reservation "ppc620-imul" 5 - (and (eq_attr "type" "imul,imul_compare") + (and (eq_attr "type" "mul") + (eq_attr "size" "32") (eq_attr "cpu" "ppc620,ppc630")) "mciu_6xx*3") (define_insn_reservation "ppc620-imul2" 4 - (and (eq_attr "type" "imul2") + (and (eq_attr "type" "mul") + (eq_attr "size" "16") (eq_attr "cpu" "ppc620,ppc630")) "mciu_6xx*3") (define_insn_reservation "ppc620-imul3" 3 - (and (eq_attr "type" "imul3") + (and (eq_attr "type" "mul") + (eq_attr "size" "8") (eq_attr "cpu" "ppc620,ppc630")) "mciu_6xx*3") (define_insn_reservation "ppc620-lmul" 7 - (and (eq_attr "type" "lmul,lmul_compare") + (and (eq_attr "type" "mul") + (eq_attr "size" "64") (eq_attr "cpu" "ppc620,ppc630")) "mciu_6xx*5") (define_insn_reservation "ppc604-idiv" 20 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc604,ppc604e")) "mciu_6xx*19") (define_insn_reservation "ppc620-idiv" 37 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "ppc620")) "mciu_6xx*36") (define_insn_reservation "ppc630-idiv" 21 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "ppc630")) "mciu_6xx*20") (define_insn_reservation "ppc620-ldiv" 37 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "ppc620,ppc630")) "mciu_6xx*36") (define_insn_reservation "ppc604-compare" 3 - (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\ - var_delayed_compare") + (and (ior (eq_attr "type" "cmp") + (and (eq_attr "type" "add,logical,shift,exts") + (eq_attr "dot" "yes"))) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) "(iu1_6xx|iu2_6xx)") @@ -151,7 +160,7 @@ "fpu_6xx") (define_insn_reservation "ppc604-fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc604,ppc604e,ppc620")) "fpu_6xx")