Mercurial > hg > CbC > CbC_gcc
diff gcc/config/sh/sh4-300.md @ 111:04ced10e8804
gcc 7
author | kono |
---|---|
date | Fri, 27 Oct 2017 22:46:09 +0900 |
parents | a06113de4d67 |
children | 84e7813d76e9 |
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--- a/gcc/config/sh/sh4-300.md Sun Aug 21 07:07:55 2011 +0900 +++ b/gcc/config/sh/sh4-300.md Fri Oct 27 22:46:09 2017 +0900 @@ -1,5 +1,5 @@ ;; DFA scheduling description for ST40-300. -;; Copyright (C) 2004, 2006, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2004-2017 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -35,26 +35,21 @@ ;; Since SH4 is a dual issue machine,it is as if there are two ;; units so that any insn can be processed by either one ;; of the decoding unit. - (define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline") ;; The floating point units. - (define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe") ;; integer multiplier unit - (define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline") ;; LS unit - (define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline") ;; The address calculator used for branch instructions. ;; This will be reserved after "issue" of branch instructions ;; and this is to make sure that no two branch instructions ;; can be issued in parallel. - (define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline") ;; ---------------------------------------------------- @@ -85,7 +80,6 @@ "sh4_300_issue+sh4_300_mul") ;; Instructions without specific resource requirements with latency 1. - (define_insn_reservation "sh4_300_simple_arith" 1 (and (eq_attr "pipe_model" "sh4_300") (eq_attr "type" "mt_group,arith,dyn_shift,prset")) @@ -153,7 +147,6 @@ ;; or likely and likely not predicted, we might want to fill the delay slot. ;; However, there appears to be no machinery to make the compiler ;; recognize these scenarios. - (define_insn_reservation "sh4_300_branch" 1 (and (eq_attr "pipe_model" "sh4_300") (eq_attr "type" "cbranch,jump,return,jump_ind")) @@ -169,8 +162,11 @@ ;; Group: CO ;; Latency: 1-5 ;; Issue Rate: 1 - -;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2 +;; cwb is used for the sequence +;; ocbwb @%0 +;; extu.w %0,%2 +;; or %1,%2 +;; mov.l %0,@%2 ;; This description is likely inexact, but this pattern should not actually ;; appear when compiling for sh4-300; we should use isbi instead. ;; If a -mtune option is added later, we should use the icache array @@ -197,7 +193,6 @@ ;; since there are no instructions that contend for memory access early. ;; We could, of course, provide exact scheduling information for specific ;; sfuncs, if that should prove useful. - (define_insn_reservation "sh4_300_call" 16 (and (eq_attr "pipe_model" "sh4_300") (eq_attr "type" "call,sfunc")) @@ -265,7 +260,6 @@ (eq_attr "type" "dfdiv")) "sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31") - ;; ??? We don't really want these for sh4-300. ;; this pattern itself is likely to finish in 3 cycles, but also ;; to disrupt branch prediction for taken branches for the following