--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/testsuite/gcc.target/powerpc/vec-strir-12.c	Mon May 25 07:50:57 2020 +0900
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mdejagnu-cpu=future" } */
+/* See vec-strir-13.c for the same test with -O2 optimization.  */
+
+#include <altivec.h>
+
+vector unsigned short
+doString(vector unsigned short *vp)
+{
+  /* Though two built-in functions are called, the implementation
+     should use a single instruction to implement both with -O1.  */
+  vector unsigned short result = vec_strir (*vp);
+  if (vec_strir_p (*vp))
+    return result;
+  else
+    return doString (vp + 1);
+}
+
+/* Enforce that a single dot-form instruction which is properly biased
+   for the target's endianness implements this built-in.  */
+
+/* { dg-final { scan-assembler-times {\mvstrihr\.} 1 { target { be } } } } */
+/* { dg-final { scan-assembler-times {\mvstrihr\M[^.]} 0 { target { be } } } } */
+/* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
+/* { dg-final { scan-assembler-times {\mvstrihl\.} 1 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mvstrihl\M[^.]} 0 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */
+