Mercurial > hg > CbC > CbC_gcc
diff gcc/config/sh/sh.md @ 19:58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
| author | kent@firefly.cr.ie.u-ryukyu.ac.jp |
|---|---|
| date | Thu, 24 Sep 2009 13:21:57 +0900 |
| parents | a06113de4d67 |
| children | 77e2b8dfacca |
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--- a/gcc/config/sh/sh.md Thu Sep 24 13:06:16 2009 +0900 +++ b/gcc/config/sh/sh.md Thu Sep 24 13:21:57 2009 +0900 @@ -3999,6 +3999,34 @@ [(set_attr "length" "4") (set_attr "type" "arith")]) +;; Expander for DImode shift left with SImode operations. + +(define_expand "ashldi3_std" + [(set (match_operand:DI 0 "arith_reg_dest" "=r") + (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r") + (match_operand:DI 2 "const_int_operand" "n")))] + "TARGET_SH1 && INTVAL (operands[2]) < 32" + " +{ + int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1); + int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0); + rtx low_src = operand_subword (operands[1], low_word, 0, DImode); + rtx high_src = operand_subword (operands[1], high_word, 0, DImode); + rtx dst = gen_reg_rtx (DImode); + rtx low_dst = operand_subword (dst, low_word, 1, DImode); + rtx high_dst = operand_subword (dst, high_word, 1, DImode); + rtx tmp0, tmp1; + + tmp0 = gen_reg_rtx (SImode); + tmp1 = gen_reg_rtx (SImode); + emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2])))); + emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2])); + emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2])); + emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1)); + emit_move_insn (operands[0], dst); + DONE; +}") + (define_insn "ashldi3_media" [(set (match_operand:DI 0 "arith_reg_dest" "=r,r") (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r") @@ -4031,8 +4059,19 @@ emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2])); DONE; } - if (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) != 1) + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) == 1) + { + emit_insn (gen_ashldi3_k (operands[0], operands[1])); + DONE; + } + else if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) < 32) + { + emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2])); + DONE; + } + else FAIL; }")