--- a/gcc/config/arm/arm-cpus.in	Fri Oct 27 22:46:09 2017 +0900
+++ b/gcc/config/arm/arm-cpus.in	Thu Oct 25 07:37:49 2018 +0900
@@ -1,6 +1,6 @@
 # CPU, FPU and architecture specifications for ARM.
 #
-# Copyright (C) 2011-2017 Free Software Foundation, Inc.
+# Copyright (C) 2011-2018 Free Software Foundation, Inc.
 #
 # This file is part of GCC.
 #
@@ -48,26 +48,17 @@
 
 # Features - general convention: all lower case.
 
-# Extended multiply
-define feature armv3m
-
-# 26-bit mode support
-define feature mode26
-
-# 32-bit mode support
-define feature mode32
-
 # Architecture rel 4
 define feature armv4
 
-# Architecture rel 5
-define feature armv5
-
 # Thumb aware.
 define feature thumb
 
-# Architecture rel 5e.
-define feature armv5e
+# Architecture rel 5t.
+define feature armv5t
+
+# Architecture rel 5te.
+define feature armv5te
 
 # XScale.
 define feature xscale
@@ -114,9 +105,15 @@
 # Architecture rel 8.1.
 define feature armv8_1
 
-# Architecutre rel 8.2.
+# Architecture rel 8.2.
 define feature armv8_2
 
+# Architecture rel 8.3.
+define feature armv8_3
+
+# Architecture rel 8.4.
+define feature armv8_4
+
 # M-Profile security extensions.
 define feature cmse
 
@@ -159,6 +156,9 @@
 # Dot Product instructions extension to ARMv8.2-a.
 define feature dotprod
 
+# Half-precision floating-point instructions in ARMv8.4-A.
+define feature fp16fml
+
 # ISA Quirks (errata?).  Don't forget to add this to the fgroup
 # ALL_QUIRKS below.
 
@@ -196,7 +196,7 @@
 # strip off 32 D-registers, but does not remove support for
 # double-precision FP.
 define fgroup ALL_SIMD_INTERNAL	fp_d32 neon ALL_CRYPTO
-define fgroup ALL_SIMD	ALL_SIMD_INTERNAL dotprod
+define fgroup ALL_SIMD	ALL_SIMD_INTERNAL dotprod fp16fml
 
 # List of all FPU bits to strip out if -mfpu is used to override the
 # default.  fp16 is deliberately missing from this list.
@@ -206,15 +206,10 @@
 # -mfpu support.
 define fgroup ALL_FP	fp16 ALL_FPU_INTERNAL
 
-define fgroup ARMv2       notm
-define fgroup ARMv3       ARMv2 mode32
-define fgroup ARMv3m      ARMv3 armv3m
-define fgroup ARMv4       ARMv3m armv4
+define fgroup ARMv4       armv4 notm
 define fgroup ARMv4t      ARMv4 thumb
-define fgroup ARMv5       ARMv4 armv5
-define fgroup ARMv5t      ARMv5 thumb
-define fgroup ARMv5e      ARMv5 armv5e
-define fgroup ARMv5te     ARMv5e thumb
+define fgroup ARMv5t      ARMv4t armv5t
+define fgroup ARMv5te     ARMv5t armv5te
 define fgroup ARMv5tej    ARMv5te
 define fgroup ARMv6       ARMv5te armv6 be8
 define fgroup ARMv6j      ARMv6
@@ -225,7 +220,7 @@
 define fgroup ARMv6t2     ARMv6 thumb2
 # This is suspect.  ARMv6-m doesn't really pull in any useful features
 # from ARMv5* or ARMv6.
-define fgroup ARMv6m      mode32 armv3m armv4 thumb armv5 armv5e armv6
+define fgroup ARMv6m      armv4 thumb armv5t armv5te armv6 be8
 # This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
 # integer SIMD instructions that are in ARMv6T2.  */
 define fgroup ARMv7       ARMv6m thumb2 armv7
@@ -238,6 +233,8 @@
 define fgroup ARMv8a      ARMv7ve armv8
 define fgroup ARMv8_1a    ARMv8a crc32 armv8_1
 define fgroup ARMv8_2a    ARMv8_1a armv8_2
+define fgroup ARMv8_3a    ARMv8_2a armv8_3
+define fgroup ARMv8_4a    ARMv8_3a armv8_4
 define fgroup ARMv8m_base ARMv6m armv8 cmse tdiv
 define fgroup ARMv8m_main ARMv7m armv8 cmse
 define fgroup ARMv8r      ARMv8a
@@ -257,7 +254,9 @@
 
 # List of all quirk bits to strip out when comparing CPU features with
 # architectures.
-define fgroup ALL_QUIRKS   quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd
+# xscale isn't really a 'quirk', but it isn't an architecture either and we
+# need to ignore it for matching purposes.
+define fgroup ALL_QUIRKS   quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd xscale
 
 # Architecture entries
 # format:
@@ -270,43 +269,13 @@
 # end arch <name>
 #
 
-begin arch armv2
- tune for arm2
- tune flags CO_PROC NO_MODE32
- base 2
- isa ARMv2 mode26
-end arch armv2
-
-begin arch armv2a
- tune for arm2
- tune flags CO_PROC NO_MODE32
- base 2
- isa ARMv2 mode26
-end arch armv2a
-
-begin arch armv3
- tune for arm6
- tune flags CO_PROC
- base 3
- isa ARMv3 mode26
-end arch armv3
-
-begin arch armv3m
- tune for arm7m
- tune flags CO_PROC
- base 3M
- isa ARMv3m mode26
-end arch armv3m
-
 begin arch armv4
  tune for arm7tdmi
  tune flags CO_PROC
  base 4
- isa ARMv4 mode26
+ isa ARMv4
 end arch armv4
 
-# Strictly, mode26 is a permitted option for v4t, but there are no
-# implementations that support it, so we will leave it out for now.
 begin arch armv4t
  tune for arm7tdmi
  tune flags CO_PROC
@@ -314,13 +283,6 @@
  isa ARMv4t
 end arch armv4t
 
-begin arch armv5
- tune for arm10tdmi
- tune flags CO_PROC
- base 5
- isa ARMv5
-end arch armv5
-
 begin arch armv5t
  tune for arm10tdmi
  tune flags CO_PROC
@@ -328,16 +290,6 @@
  isa ARMv5t
 end arch armv5t
 
-begin arch armv5e
- tune for arm1026ej-s
- tune flags CO_PROC
- base 5E
- isa ARMv5e
- option fp add VFPv2 FP_DBL
- optalias vfpv2 fp
- option nofp remove ALL_FP
-end arch armv5e
-
 begin arch armv5te
  tune for arm1026ej-s
  tune flags CO_PROC
@@ -435,6 +387,8 @@
  isa ARMv6m
 end arch armv6-m
 
+# This is now equivalent to armv6-m, but we keep it because some
+# versions of GAS still distinguish between the two.
 begin arch armv6s-m
  tune for cortex-m1
  base 6M
@@ -573,12 +527,41 @@
  isa ARMv8_2a
  option simd add FP_ARMv8 NEON
  option fp16 add fp16 FP_ARMv8 NEON
+ option fp16fml add fp16fml fp16 FP_ARMv8 NEON
  option crypto add FP_ARMv8 CRYPTO
  option nocrypto remove ALL_CRYPTO
  option nofp remove ALL_FP
  option dotprod add FP_ARMv8 DOTPROD
 end arch armv8.2-a
 
+begin arch armv8.3-a
+ tune for cortex-a53
+ tune flags CO_PROC
+ base 8A
+ profile A
+ isa ARMv8_3a
+ option simd add FP_ARMv8 NEON
+ option fp16 add fp16 FP_ARMv8 NEON
+ option fp16fml add fp16fml fp16 FP_ARMv8 NEON
+ option crypto add FP_ARMv8 CRYPTO
+ option nocrypto remove ALL_CRYPTO
+ option nofp remove ALL_FP
+ option dotprod add FP_ARMv8 DOTPROD
+end arch armv8.3-a
+
+begin arch armv8.4-a
+ tune for cortex-a53
+ tune flags CO_PROC
+ base 8A
+ profile A
+ isa ARMv8_4a
+ option simd add FP_ARMv8 DOTPROD
+ option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD
+ option crypto add FP_ARMv8 CRYPTO DOTPROD
+ option nocrypto remove ALL_CRYPTO
+ option nofp remove ALL_FP
+end arch armv8.4-a
+
 begin arch armv8-m.base
  tune for cortex-m23
  base 8M_BASE
@@ -637,11 +620,12 @@
 #   [tune for <cpu-name>]
 #   [tune flags <list>]
 #   architecture <name>
-#   [fpu <name>]
 #   [isa <additional-isa-flags-list>]
 #   [option <name> add|remove <isa-list>]*
 #   [optalias <name> <optname>]*
 #   [costs <name>]
+#   [vendor <vendor-id>
+#    [part <part-id> [minrev [maxrev]]]
 # end cpu <name>
 #
 # If omitted, cname is formed from transforming the cpuname to convert
@@ -650,155 +634,15 @@
 # isa flags are appended to those defined by the architecture.
 # Each add option must have a distinct feature set and each remove
 # option must similarly have a distinct feature set.  Option aliases can be
-# added with the optalias statement
-
-# V2/V2A Architecture Processors
-begin cpu arm2
- tune flags CO_PROC NO_MODE32
- architecture armv2
- costs slowmul
-end cpu arm2
-
-begin cpu arm250
- tune flags CO_PROC NO_MODE32
- architecture armv2
- costs slowmul
-end cpu arm250
-
-begin cpu arm3
- tune flags CO_PROC NO_MODE32
- architecture armv2
- costs slowmul
-end cpu arm3
-
-
-# V3 Architecture Processors
-begin cpu arm6
- tune flags CO_PROC
- architecture armv3
- costs slowmul
-end cpu arm6
-
-begin cpu arm60
- tune flags CO_PROC
- architecture armv3
- costs slowmul
-end cpu arm60
-
-begin cpu arm600
- tune flags CO_PROC WBUF
- architecture armv3
- costs slowmul
-end cpu arm600
-
-begin cpu arm610
- tune flags WBUF
- architecture armv3
- costs slowmul
-end cpu arm610
-
-begin cpu arm620
- tune flags CO_PROC WBUF
- architecture armv3
- costs slowmul
-end cpu arm620
-
-begin cpu arm7
- tune flags CO_PROC
- architecture armv3
- costs slowmul
-end cpu arm7
-
-begin cpu arm7d
- tune flags CO_PROC
- architecture armv3
- costs slowmul
-end cpu arm7d
-
-begin cpu arm7di
- tune flags CO_PROC
- architecture armv3
- costs slowmul
-end cpu arm7di
-
-begin cpu arm70
- tune flags CO_PROC
- architecture armv3
- costs slowmul
-end cpu arm70
-
-begin cpu arm700
- tune flags CO_PROC WBUF
- architecture armv3
- costs slowmul
-end cpu arm700
-
-begin cpu arm700i
- tune flags CO_PROC WBUF
- architecture armv3
- costs slowmul
-end cpu arm700i
-
-begin cpu arm710
- tune flags WBUF
- architecture armv3
- costs slowmul
-end cpu arm710
-
-begin cpu arm720
- tune flags WBUF
- architecture armv3
- costs slowmul
-end cpu arm720
-
-begin cpu arm710c
- tune flags WBUF
- architecture armv3
- costs slowmul
-end cpu arm710c
-
-begin cpu arm7100
- tune flags WBUF
- architecture armv3
- costs slowmul
-end cpu arm7100
-
-begin cpu arm7500
- tune flags WBUF
- architecture armv3
- costs slowmul
-end cpu arm7500
-
-# Doesn't have an external co-proc, but does have embedded FPA
-# (the FPA part is no-longer supported).
-begin cpu arm7500fe
- tune flags CO_PROC WBUF
- architecture armv3
- costs slowmul
-end cpu arm7500fe
-
-
-# V3M Architecture Processors
-# arm7m doesn't exist on its own, but only with "D", (and "I"), but
-# those don't alter the code, so arm7m is sometimes used.
-begin cpu arm7m
- tune flags CO_PROC
- architecture armv3m
- costs fastmul
-end cpu arm7m
-
-begin cpu arm7dm
- tune flags CO_PROC
- architecture armv3m
- costs fastmul
-end cpu arm7dm
-
-begin cpu arm7dmi
- tune flags CO_PROC
- architecture armv3m
- costs fastmul
-end cpu arm7dmi
-
+# added with the optalias statement.
+# Vendor, part and revision information is used for native CPU and architecture
+# detection.  All values must be in hex (lower case) with the leading '0x'
+# omitted.  For example the cortex-a9 will have vendor 41 and part c09.
+# Revision information is used to match a subrange of part
+# revisions: minrev <= detected <= maxrev.
+# If a minrev or maxrev are omitted then minrev defaults to zero and maxrev
+# to infinity.
+# Revision information is not implemented yet; no part uses it.
 
 # V4 Architecture Processors
 begin cpu arm8
@@ -943,8 +787,7 @@
 # V5TE Architecture Processors
 begin cpu arm9e
  tune flags LDSCHED
- architecture armv5te
- fpu vfpv2
+ architecture armv5te+fp
  option nofp remove ALL_FP
  costs 9e
 end cpu arm9e
@@ -952,8 +795,7 @@
 begin cpu arm946e-s
  cname arm946es
  tune flags LDSCHED
- architecture armv5te
- fpu vfpv2
+ architecture armv5te+fp
  option nofp remove ALL_FP
  costs 9e
 end cpu arm946e-s
@@ -961,8 +803,7 @@
 begin cpu arm966e-s
  cname arm966es
  tune flags LDSCHED
- architecture armv5te
- fpu vfpv2
+ architecture armv5te+fp
  option nofp remove ALL_FP
  costs 9e
 end cpu arm966e-s
@@ -970,32 +811,28 @@
 begin cpu arm968e-s
  cname arm968es
  tune flags LDSCHED
- architecture armv5te
- fpu vfpv2
+ architecture armv5te+fp
  option nofp remove ALL_FP
  costs 9e
 end cpu arm968e-s
 
 begin cpu arm10e
  tune flags LDSCHED
- architecture armv5te
- fpu vfpv2
+ architecture armv5te+fp
  option nofp remove ALL_FP
  costs fastmul
 end cpu arm10e
 
 begin cpu arm1020e
  tune flags LDSCHED
- architecture armv5te
- fpu vfpv2
+ architecture armv5te+fp
  option nofp remove ALL_FP
  costs fastmul
 end cpu arm1020e
 
 begin cpu arm1022e
  tune flags LDSCHED
- architecture armv5te
- fpu vfpv2
+ architecture armv5te+fp
  option nofp remove ALL_FP
  costs fastmul
 end cpu arm1022e
@@ -1048,19 +885,21 @@
 begin cpu arm926ej-s
  cname arm926ejs
  tune flags LDSCHED
- architecture armv5tej
- fpu vfpv2
+ architecture armv5tej+fp
  option nofp remove ALL_FP
  costs 9e
+ vendor 41
+ part 926
 end cpu arm926ej-s
 
 begin cpu arm1026ej-s
  cname arm1026ejs
  tune flags LDSCHED
- architecture armv5tej
- fpu vfpv2
+ architecture armv5tej+fp
  option nofp remove ALL_FP
  costs 9e
+ vendor 41
+ part a26
 end cpu arm1026ej-s
 
 
@@ -1075,9 +914,10 @@
 begin cpu arm1136jf-s
  cname arm1136jfs
  tune flags LDSCHED
- architecture armv6j
- fpu vfpv2
+ architecture armv6j+fp
  costs 9e
+ vendor 41
+ part b36
 end cpu arm1136jf-s
 
 begin cpu arm1176jz-s
@@ -1090,9 +930,10 @@
 begin cpu arm1176jzf-s
  cname arm1176jzfs
  tune flags LDSCHED
- architecture armv6kz
- fpu vfpv2
+ architecture armv6kz+fp
  costs 9e
+ vendor 41
+ part b76
 end cpu arm1176jzf-s
 
 begin cpu mpcorenovfp
@@ -1103,9 +944,10 @@
 
 begin cpu mpcore
  tune flags LDSCHED
- architecture armv6k
- fpu vfpv2
+ architecture armv6k+fp
  costs 9e
+ vendor 41
+ part b02
 end cpu mpcore
 
 begin cpu arm1156t2-s
@@ -1118,9 +960,10 @@
 begin cpu arm1156t2f-s
  cname arm1156t2fs
  tune flags LDSCHED
- architecture armv6t2
- fpu vfpv2
+ architecture armv6t2+fp
  costs v6t2
+ vendor 41
+ part b56
 end cpu arm1156t2f-s
 
 
@@ -1128,21 +971,25 @@
 begin cpu cortex-m1
  cname cortexm1
  tune flags LDSCHED
- architecture armv6-m
+ architecture armv6s-m
  costs v6m
+ vendor 41
+ part c21
 end cpu cortex-m1
 
 begin cpu cortex-m0
  cname cortexm0
  tune flags LDSCHED
- architecture armv6-m
+ architecture armv6s-m
  costs v6m
+ vendor 41
+ part c20
 end cpu cortex-m0
 
 begin cpu cortex-m0plus
  cname cortexm0plus
  tune flags LDSCHED
- architecture armv6-m
+ architecture armv6s-m
  costs v6m
 end cpu cortex-m0plus
 
@@ -1152,7 +999,7 @@
  cname cortexm1smallmultiply
  tune for cortex-m1
  tune flags LDSCHED SMALLMUL
- architecture armv6-m
+ architecture armv6s-m
  costs v6m
 end cpu cortex-m1.small-multiply
 
@@ -1160,7 +1007,7 @@
  cname cortexm0smallmultiply
  tune for cortex-m0
  tune flags LDSCHED SMALLMUL
- architecture armv6-m
+ architecture armv6s-m
  costs v6m
 end cpu cortex-m0.small-multiply
 
@@ -1168,7 +1015,7 @@
  cname cortexm0plussmallmultiply
  tune for cortex-m0plus
  tune flags LDSCHED SMALLMUL
- architecture armv6-m
+ architecture armv6s-m
  costs v6m
 end cpu cortex-m0plus.small-multiply
 
@@ -1177,8 +1024,7 @@
 begin cpu generic-armv7-a
  cname genericv7a
  tune flags LDSCHED
- architecture armv7-a
- fpu vfpv3-d16
+ architecture armv7-a+fp
  option vfpv3-d16 add VFPv3 FP_DBL
  option vfpv3 add VFPv3 FP_D32
  option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv
@@ -1198,68 +1044,75 @@
 begin cpu cortex-a5
  cname cortexa5
  tune flags LDSCHED
- architecture armv7-a
- fpu neon-fp16
+ architecture armv7-a+neon-fp16
  option nosimd remove ALL_SIMD
  option nofp remove ALL_FP
  costs cortex_a5
+ vendor 41
+ part c05
 end cpu cortex-a5
 
 begin cpu cortex-a7
  cname cortexa7
  tune flags LDSCHED
- architecture armv7ve
- fpu neon-vfpv4
+ architecture armv7ve+simd
  option nosimd remove ALL_SIMD
  option nofp remove ALL_FP
  costs cortex_a7
+ vendor 41
+ part c07
 end cpu cortex-a7
 
 begin cpu cortex-a8
  cname cortexa8
  tune flags LDSCHED
- architecture armv7-a
- fpu neon-vfpv3
+ architecture armv7-a+simd
  option nofp remove ALL_FP
  costs cortex_a8
+ vendor 41
+ part c08
 end cpu cortex-a8
 
 begin cpu cortex-a9
  cname cortexa9
  tune flags LDSCHED
- architecture armv7-a
- fpu neon-fp16
+ architecture armv7-a+neon-fp16
  option nosimd remove ALL_SIMD
  option nofp remove ALL_FP
  costs cortex_a9
+ vendor 41
+ part c09
 end cpu cortex-a9
 
 begin cpu cortex-a12
  cname cortexa12
  tune for cortex-a17
  tune flags LDSCHED
- architecture armv7ve
- fpu neon-vfpv4
+ architecture armv7ve+simd
  option nofp remove ALL_FP
  costs cortex_a12
+ vendor 41
+ part c0d
 end cpu cortex-a12
 
 begin cpu cortex-a15
  cname cortexa15
  tune flags LDSCHED
- architecture armv7ve
- fpu neon-vfpv4
+ architecture armv7ve+simd
  option nofp remove ALL_FP
  costs cortex_a15
+ vendor 41
+ part c0f
 end cpu cortex-a15
 
 begin cpu cortex-a17
  cname cortexa17
  tune flags LDSCHED
- architecture armv7ve
- fpu neon-vfpv4
+ architecture armv7ve+simd
  option nofp remove ALL_FP
  costs cortex_a12
+ vendor 41
+ part c0e
 end cpu cortex-a17
 
 begin cpu cortex-r4
@@ -1272,46 +1125,49 @@
 begin cpu cortex-r4f
  cname cortexr4f
  tune flags LDSCHED
- architecture armv7-r
- fpu vfpv3-d16
+ architecture armv7-r+fp
  costs cortex
+ vendor 41
+ part c14
 end cpu cortex-r4f
 
 begin cpu cortex-r5
  cname cortexr5
  tune flags LDSCHED
- architecture armv7-r+idiv
- fpu vfpv3-d16
+ architecture armv7-r+idiv+fp
  option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
+ vendor 41
+ part c15
 end cpu cortex-r5
 
 begin cpu cortex-r7
  cname cortexr7
  tune flags LDSCHED
- architecture armv7-r+idiv
- fpu vfpv3-d16
+ architecture armv7-r+idiv+fp
  option nofp remove ALL_FP
  costs cortex
+ vendor 41
+ part c17
 end cpu cortex-r7
 
 begin cpu cortex-r8
  cname cortexr8
  tune for cortex-r7
  tune flags LDSCHED
- architecture armv7-r+idiv
- fpu vfpv3-d16
+ architecture armv7-r+idiv+fp
  option nofp remove ALL_FP
  costs cortex
+ vendor 41
+ part c18
 end cpu cortex-r8
 
 begin cpu cortex-m7
  cname cortexm7
  tune flags LDSCHED
- architecture armv7e-m
+ architecture armv7e-m+fp.dp
  isa quirk_no_volatile_ce
- fpu fpv5-d16
  option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex_m7
@@ -1320,10 +1176,11 @@
 begin cpu cortex-m4
  cname cortexm4
  tune flags LDSCHED
- architecture armv7e-m
- fpu fpv4-sp-d16
+ architecture armv7e-m+fp
  option nofp remove ALL_FP
  costs v7m
+ vendor 41
+ part c24
 end cpu cortex-m4
 
 begin cpu cortex-m3
@@ -1332,6 +1189,8 @@
  architecture armv7-m
  isa quirk_cm3_ldrd
  costs v7m
+ vendor 41
+ part c23
 end cpu cortex-m3
 
 begin cpu marvell-pj4
@@ -1346,8 +1205,7 @@
  cname cortexa15cortexa7
  tune for cortex-a7
  tune flags LDSCHED
- architecture armv7ve
- fpu neon-vfpv4
+ architecture armv7ve+simd
  option nofp remove ALL_FP
  costs cortex_a15
 end cpu cortex-a15.cortex-a7
@@ -1356,8 +1214,7 @@
  cname cortexa17cortexa7
  tune for cortex-a7
  tune flags LDSCHED
- architecture armv7ve
- fpu neon-vfpv4
+ architecture armv7ve+simd
  option nofp remove ALL_FP
  costs cortex_a12
 end cpu cortex-a17.cortex-a7
@@ -1368,76 +1225,80 @@
  cname cortexa32
  tune for cortex-a53
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  option nofp remove ALL_FP
  costs cortex_a35
+ vendor 41
+ part d01
 end cpu cortex-a32
 
 begin cpu cortex-a35
  cname cortexa35
  tune for cortex-a53
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  option nofp remove ALL_FP
  costs cortex_a35
+ vendor 41
+ part d04
 end cpu cortex-a35
 
 begin cpu cortex-a53
  cname cortexa53
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  option nofp remove ALL_FP
  costs cortex_a53
+ vendor 41
+ part d03
 end cpu cortex-a53
 
 begin cpu cortex-a57
  cname cortexa57
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a57
+ vendor 41
+ part d07
 end cpu cortex-a57
 
 begin cpu cortex-a72
  cname cortexa72
  tune for cortex-a57
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a57
+ vendor 41
+ part d08
 end cpu cortex-a72
 
 begin cpu cortex-a73
  cname cortexa73
  tune for cortex-a57
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a73
+ vendor 41
+ part d09
 end cpu cortex-a73
 
 begin cpu exynos-m1
  cname exynosm1
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  costs exynosm1
 end cpu exynos-m1
 
 begin cpu xgene1
  tune flags LDSCHED
- architecture armv8-a
- fpu neon-fp-armv8
+ architecture armv8-a+simd
  option crypto add FP_ARMv8 CRYPTO
  costs xgene1
 end cpu xgene1
@@ -1447,8 +1308,7 @@
  cname cortexa57cortexa53
  tune for cortex-a53
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a57
 end cpu cortex-a57.cortex-a53
@@ -1457,8 +1317,7 @@
  cname cortexa72cortexa53
  tune for cortex-a53
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a57
 end cpu cortex-a72.cortex-a53
@@ -1467,8 +1326,7 @@
  cname cortexa73cortexa35
  tune for cortex-a53
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a73
 end cpu cortex-a73.cortex-a35
@@ -1477,8 +1335,7 @@
  cname cortexa73cortexa53
  tune for cortex-a53
  tune flags LDSCHED
- architecture armv8-a+crc
- fpu neon-fp-armv8
+ architecture armv8-a+crc+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a73
 end cpu cortex-a73.cortex-a53
@@ -1489,35 +1346,55 @@
  cname cortexa55
  tune for cortex-a53
  tune flags LDSCHED
- architecture armv8.2-a+fp16+dotprod
- fpu neon-fp-armv8
+ architecture armv8.2-a+fp16+dotprod+simd
  option crypto add FP_ARMv8 CRYPTO
  option nofp remove ALL_FP
  costs cortex_a53
+ vendor 41
+ part d05
 end cpu cortex-a55
 
 begin cpu cortex-a75
  cname cortexa75
  tune for cortex-a57
  tune flags LDSCHED
- architecture armv8.2-a+fp16+dotprod
- fpu neon-fp-armv8
+ architecture armv8.2-a+fp16+dotprod+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a73
+ vendor 41
+ part d0a
 end cpu cortex-a75
 
+begin cpu cortex-a76
+ cname cortexa76
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16+dotprod+simd
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a57
+ vendor 41
+ part d0b
+end cpu cortex-a76
 
 # ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations
 begin cpu cortex-a75.cortex-a55
  cname cortexa75cortexa55
  tune for cortex-a53
  tune flags LDSCHED
- architecture armv8.2-a+fp16+dotprod
- fpu neon-fp-armv8
+ architecture armv8.2-a+fp16+dotprod+simd
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a73
 end cpu cortex-a75.cortex-a55
 
+begin cpu cortex-a76.cortex-a55
+ cname cortexa76cortexa55
+ tune for cortex-a53
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16+dotprod+simd
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a57
+end cpu cortex-a76.cortex-a55
+
 # V8 M-profile implementations.
 begin cpu cortex-m23
  cname cortexm23
@@ -1529,8 +1406,7 @@
 begin cpu cortex-m33
  cname cortexm33
  tune flags LDSCHED
- architecture armv8-m.main+dsp
- fpu fpv5-sp-d16
+ architecture armv8-m.main+dsp+fp
  option nofp remove ALL_FP
  option nodsp remove armv7em
  costs v7m
@@ -1541,9 +1417,10 @@
  cname cortexr52
  tune flags LDSCHED
  architecture armv8-r+crc+simd
- fpu neon-fp-armv8
  option nofp.dp remove FP_DBL ALL_SIMD
  costs cortex
+ vendor 41
+ part d13
 end cpu cortex-r52
 
 # FPU entries