--- a/gcc/config/arm/arm-fixed.md	Fri Oct 27 22:46:09 2017 +0900
+++ b/gcc/config/arm/arm-fixed.md	Thu Oct 25 07:37:49 2018 +0900
@@ -1,4 +1,4 @@
-;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
+;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -35,7 +35,6 @@
   "TARGET_INT_SIMD"
   "sadd<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")
    (set_attr "type" "alu_dsp_reg")])
 
 (define_insn "usadd<mode>3"
@@ -45,7 +44,6 @@
   "TARGET_INT_SIMD"
   "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")
    (set_attr "type" "alu_dsp_reg")])
 
 (define_insn "ssadd<mode>3"
@@ -55,7 +53,6 @@
   "TARGET_INT_SIMD"
   "qadd<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")
    (set_attr "type" "alu_dsp_reg")])
 
 (define_insn "sub<mode>3"
@@ -75,7 +72,6 @@
   "TARGET_INT_SIMD"
   "ssub<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")
    (set_attr "type" "alu_dsp_reg")])
 
 (define_insn "ussub<mode>3"
@@ -86,7 +82,6 @@
   "TARGET_INT_SIMD"
   "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")
    (set_attr "type" "alu_dsp_reg")])
 
 (define_insn "sssub<mode>3"
@@ -96,7 +91,6 @@
   "TARGET_INT_SIMD"
   "qsub<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")
    (set_attr "type" "alu_dsp_reg")])
 
 ;; Fractional multiplies.
@@ -143,7 +137,7 @@
   [(set (match_operand:SQ 0 "s_register_operand" "")
 	(mult:SQ (match_operand:SQ 1 "s_register_operand" "")
 		 (match_operand:SQ 2 "s_register_operand" "")))]
-  "TARGET_32BIT && arm_arch3m"
+  "TARGET_32BIT"
 {
   rtx tmp1 = gen_reg_rtx (DImode);
   rtx tmp2 = gen_reg_rtx (SImode);
@@ -165,7 +159,7 @@
   [(set (match_operand:SA 0 "s_register_operand" "")
 	(mult:SA (match_operand:SA 1 "s_register_operand" "")
 		 (match_operand:SA 2 "s_register_operand" "")))]
-  "TARGET_32BIT && arm_arch3m"
+  "TARGET_32BIT"
 {
   rtx tmp1 = gen_reg_rtx (DImode);
   rtx tmp2 = gen_reg_rtx (SImode);
@@ -184,7 +178,7 @@
   [(set (match_operand:USA 0 "s_register_operand" "")
 	(mult:USA (match_operand:USA 1 "s_register_operand" "")
 		  (match_operand:USA 2 "s_register_operand" "")))]
-  "TARGET_32BIT && arm_arch3m"
+  "TARGET_32BIT"
 {
   rtx tmp1 = gen_reg_rtx (DImode);
   rtx tmp2 = gen_reg_rtx (SImode);
@@ -414,7 +408,6 @@
   "TARGET_32BIT && arm_arch6"
   "ssat%?\\t%0, #16, %2%S1"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")
    (set_attr "shift" "1")
    (set_attr "type" "alu_shift_imm")])
 
@@ -424,6 +417,5 @@
   "TARGET_INT_SIMD"
   "usat%?\\t%0, #16, %1"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")
    (set_attr "type" "alu_imm")]
 )