--- a/gcc/config/rs6000/dfp.md	Fri Oct 27 22:46:09 2017 +0900
+++ b/gcc/config/rs6000/dfp.md	Thu Oct 25 07:37:49 2018 +0900
@@ -1,5 +1,5 @@
 ;; Decimal Floating Point (DFP) patterns.
-;; Copyright (C) 2007-2017 Free Software Foundation, Inc.
+;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
 ;; (bergner@vnet.ibm.com).
 
@@ -37,8 +37,7 @@
    || gpc_reg_operand (operands[1], SDmode))
    && TARGET_HARD_FLOAT"
   "stfd%U0%X0 %1,%0"
-  [(set_attr "type" "fpstore")
-   (set_attr "length" "4")])
+  [(set_attr "type" "fpstore")])
 
 (define_insn "movsd_load"
   [(set (match_operand:SD 0 "nonimmediate_operand" "=f")
@@ -48,8 +47,7 @@
    || gpc_reg_operand (operands[1], DDmode))
    && TARGET_HARD_FLOAT"
   "lfd%U1%X1 %0,%1"
-  [(set_attr "type" "fpload")
-   (set_attr "length" "4")])
+  [(set_attr "type" "fpload")])
 
 ;; Hardware support for decimal floating point operations.
 
@@ -344,11 +342,11 @@
   [(set (match_dup 3)
 	(compare:CCFP
          (unspec:D64_D128
-	  [(match_operand:SI 1 "const_int_operand" "n")
-	   (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
+	  [(match_operand:SI 1 "const_int_operand")
+	   (match_operand:D64_D128 2 "gpc_reg_operand")]
 	  UNSPEC_DTSTSFI)
 	 (match_dup 4)))
-   (set (match_operand:SI 0 "register_operand" "")
+   (set (match_operand:SI 0 "register_operand")
    	(DFP_TEST:SI (match_dup 3)
 		     (const_int 0)))
   ]