Mercurial > hg > CbC > CbC_gcc
diff gcc/config/rs6000/rs6000.h @ 131:84e7813d76e9
gcc-8.2
| author | mir3636 |
|---|---|
| date | Thu, 25 Oct 2018 07:37:49 +0900 |
| parents | 04ced10e8804 |
| children | 1830386684a0 |
line wrap: on
line diff
--- a/gcc/config/rs6000/rs6000.h Fri Oct 27 22:46:09 2017 +0900 +++ b/gcc/config/rs6000/rs6000.h Thu Oct 25 07:37:49 2018 +0900 @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 1992-2017 Free Software Foundation, Inc. + Copyright (C) 1992-2018 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -30,6 +30,11 @@ #include "config/rs6000/rs6000-opts.h" #endif +/* 128-bit floating point precision values. */ +#ifndef RS6000_MODES_H +#include "config/rs6000/rs6000-modes.h" +#endif + /* Definitions for the object file format. These are set at compile-time. */ @@ -67,50 +72,11 @@ #define PPC405_ERRATUM77 0 #endif -#ifndef TARGET_PAIRED_FLOAT -#define TARGET_PAIRED_FLOAT 0 -#endif - -#ifdef HAVE_AS_POPCNTB -#define ASM_CPU_POWER5_SPEC "-mpower5" -#else -#define ASM_CPU_POWER5_SPEC "-mpower4" -#endif - -#ifdef HAVE_AS_DFP -#define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" -#else -#define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" -#endif - -#ifdef HAVE_AS_POPCNTD -#define ASM_CPU_POWER7_SPEC "-mpower7" -#else -#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" -#endif - -#ifdef HAVE_AS_POWER8 -#define ASM_CPU_POWER8_SPEC "-mpower8" -#else -#define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC -#endif - -#ifdef HAVE_AS_POWER9 -#define ASM_CPU_POWER9_SPEC "-mpower9" -#else -#define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC -#endif - -#ifdef HAVE_AS_DCI -#define ASM_CPU_476_SPEC "-m476" -#else -#define ASM_CPU_476_SPEC "-mpower4" -#endif - /* Common ASM definitions used by ASM_SPEC among the various targets for handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to provide the default assembler options if the user uses -mcpu=native, so if - you make changes here, make them also there. */ + you make changes here, make them also there. PR63177: Do not pass -mpower8 + to the assembler if -mpower9-vector was also used. */ #define ASM_CPU_SPEC \ "%{!mcpu*: \ %{mpowerpc64*: -mppc64} \ @@ -119,16 +85,16 @@ %{mcpu=cell: -mcell} \ %{mcpu=power3: -mppc64} \ %{mcpu=power4: -mpower4} \ -%{mcpu=power5: %(asm_cpu_power5)} \ -%{mcpu=power5+: %(asm_cpu_power5)} \ -%{mcpu=power6: %(asm_cpu_power6) -maltivec} \ -%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ -%{mcpu=power7: %(asm_cpu_power7)} \ -%{mcpu=power8: %(asm_cpu_power8)} \ -%{mcpu=power9: %(asm_cpu_power9)} \ +%{mcpu=power5: -mpower5} \ +%{mcpu=power5+: -mpower5} \ +%{mcpu=power6: -mpower6 -maltivec} \ +%{mcpu=power6x: -mpower6 -maltivec} \ +%{mcpu=power7: -mpower7} \ +%{mcpu=power8: %{!mpower9-vector: -mpower8}} \ +%{mcpu=power9: -mpower9} \ %{mcpu=a2: -ma2} \ %{mcpu=powerpc: -mppc} \ -%{mcpu=powerpc64le: %(asm_cpu_power8)} \ +%{mcpu=powerpc64le: -mpower8} \ %{mcpu=rs64a: -mppc64} \ %{mcpu=401: -mppc} \ %{mcpu=403: -m403} \ @@ -138,8 +104,8 @@ %{mcpu=440fp: -m440} \ %{mcpu=464: -m440} \ %{mcpu=464fp: -m440} \ -%{mcpu=476: %(asm_cpu_476)} \ -%{mcpu=476fp: %(asm_cpu_476)} \ +%{mcpu=476: -m476} \ +%{mcpu=476fp: -m476} \ %{mcpu=505: -mppc} \ %{mcpu=601: -m601} \ %{mcpu=602: -mppc} \ @@ -171,8 +137,9 @@ %{mcpu=e5500: -me5500} \ %{mcpu=e6500: -me6500} \ %{maltivec: -maltivec} \ -%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ -%{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ +%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: -mpower7}} \ +%{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: -mpower8}} \ +%{mpower9-vector: %{!mcpu*|mcpu=power8: -mpower9}} \ -many" #define CPP_DEFAULT_SPEC "" @@ -197,12 +164,6 @@ { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ { "asm_default", ASM_DEFAULT_SPEC }, \ { "cc1_cpu", CC1_CPU_SPEC }, \ - { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ - { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ - { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ - { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ - { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \ - { "asm_cpu_476", ASM_CPU_476_SPEC }, \ SUBTARGET_EXTRA_SPECS /* -mcpu=native handling only makes sense with compiler running on @@ -240,94 +201,6 @@ #define TARGET_MFCRF 0 #endif -/* Define TARGET_POPCNTB if the target assembler does not support the - popcount byte instruction. */ - -#ifndef HAVE_AS_POPCNTB -#undef TARGET_POPCNTB -#define TARGET_POPCNTB 0 -#endif - -/* Define TARGET_FPRND if the target assembler does not support the - fp rounding instructions. */ - -#ifndef HAVE_AS_FPRND -#undef TARGET_FPRND -#define TARGET_FPRND 0 -#endif - -/* Define TARGET_CMPB if the target assembler does not support the - cmpb instruction. */ - -#ifndef HAVE_AS_CMPB -#undef TARGET_CMPB -#define TARGET_CMPB 0 -#endif - -/* Define TARGET_MFPGPR if the target assembler does not support the - mffpr and mftgpr instructions. */ - -#ifndef HAVE_AS_MFPGPR -#undef TARGET_MFPGPR -#define TARGET_MFPGPR 0 -#endif - -/* Define TARGET_DFP if the target assembler does not support decimal - floating point instructions. */ -#ifndef HAVE_AS_DFP -#undef TARGET_DFP -#define TARGET_DFP 0 -#endif - -/* Define TARGET_POPCNTD if the target assembler does not support the - popcount word and double word instructions. */ - -#ifndef HAVE_AS_POPCNTD -#undef TARGET_POPCNTD -#define TARGET_POPCNTD 0 -#endif - -/* Define the ISA 2.07 flags as 0 if the target assembler does not support the - waitasecond instruction. Allow -mpower8-fusion, since it does not add new - instructions. */ - -#ifndef HAVE_AS_POWER8 -#undef TARGET_DIRECT_MOVE -#undef TARGET_CRYPTO -#undef TARGET_HTM -#undef TARGET_P8_VECTOR -#define TARGET_DIRECT_MOVE 0 -#define TARGET_CRYPTO 0 -#define TARGET_HTM 0 -#define TARGET_P8_VECTOR 0 -#endif - -/* Define the ISA 3.0 flags as 0 if the target assembler does not support - Power9 instructions. Allow -mpower9-fusion, since it does not add new - instructions. Allow -misel, since it predates ISA 3.0 and does - not require any Power9 features. */ - -#ifndef HAVE_AS_POWER9 -#undef TARGET_FLOAT128_HW -#undef TARGET_MODULO -#undef TARGET_P9_VECTOR -#undef TARGET_P9_MINMAX -#undef TARGET_P9_MISC -#define TARGET_FLOAT128_HW 0 -#define TARGET_MODULO 0 -#define TARGET_P9_VECTOR 0 -#define TARGET_P9_MINMAX 0 -#define TARGET_P9_MISC 0 -#endif - -/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If - not, generate the lwsync code as an integer constant. */ -#ifdef HAVE_AS_LWSYNC -#define TARGET_LWSYNC_INSTRUCTION 1 -#else -#define TARGET_LWSYNC_INSTRUCTION 0 -#endif - /* Define TARGET_TLS_MARKERS if the target assembler does not support arg markers for __tls_get_addr calls. */ #ifndef HAVE_AS_TLS_MARKERS @@ -380,19 +253,7 @@ /* The option machinery will define this. */ #endif -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) - -/* FPU operations supported. - Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must - also test TARGET_HARD_FLOAT. */ -#define TARGET_SINGLE_FLOAT 1 -#define TARGET_DOUBLE_FLOAT 1 -#define TARGET_SINGLE_FPU 0 -#define TARGET_SIMPLE_FPU 0 -#define TARGET_XILINX_FPU 0 - -/* Recast the processor type to the cpu attribute. */ -#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) +#define TARGET_DEFAULT (MASK_MULTIPLE) /* Define generic processor types based upon current deployment. */ #define PROCESSOR_COMMON PROCESSOR_PPC601 @@ -440,11 +301,13 @@ Similarly IFmode is the IBM long double format even if the default is IEEE 128-bit. Don't allow IFmode if -msoft-float. */ #define FLOAT128_IEEE_P(MODE) \ - ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ + ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ + && ((MODE) == TFmode || (MODE) == TCmode)) \ || ((MODE) == KFmode) || ((MODE) == KCmode)) #define FLOAT128_IBM_P(MODE) \ - ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ + ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ + && ((MODE) == TFmode || (MODE) == TCmode)) \ || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) /* Helper macros to say whether a 128-bit floating point type can go in a @@ -526,15 +389,6 @@ ? rs6000_vector_align[(MODE)] \ : (int)GET_MODE_BITSIZE ((MODE))) -/* Determine the element order to use for vector instructions. By - default we use big-endian element order when targeting big-endian, - and little-endian element order when targeting little-endian. For - programs being ported from BE Power to LE Power, it can sometimes - be useful to use big-endian element order when targeting little-endian. - This is set via -maltivec=be, for example. */ -#define VECTOR_ELT_ORDER_BIG \ - (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) - /* Element number of the 64-bit value in a 128-bit vector that can be accessed with scalar instructions. */ #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) @@ -560,20 +414,20 @@ #define TARGET_ALIGN_NATURAL 0 #endif -#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) +/* We use values 126..128 to pick the appropriate long double type (IFmode, + KFmode, TFmode). */ +#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) #define TARGET_IEEEQUAD rs6000_ieeequad #define TARGET_ALTIVEC_ABI rs6000_altivec_abi #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. - Enable 32-bit fcfid's on any of the switches for newer ISA machines or - XILINX. */ + Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POPCNTB /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ - || TARGET_POPCNTD /* ISA 2.06 */ \ - || TARGET_XILINX_FPU) + || TARGET_POPCNTD) /* ISA 2.06 */ #define TARGET_FCTIDZ TARGET_FCFID #define TARGET_STFIWX TARGET_PPC_GFXOPT @@ -621,11 +475,8 @@ /* ISA 3.0 has new min/max functions that don't need fast math that are being phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct answers if the arguments are not in the normal range. */ -#define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \ - && (TARGET_P9_MINMAX || !flag_trapping_math)) - -#define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \ - && (TARGET_P9_MINMAX || !flag_trapping_math)) +#define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ + && (TARGET_P9_MINMAX || !flag_trapping_math)) /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map @@ -659,7 +510,6 @@ #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN -#define MASK_STRING OPTION_MASK_STRING #define MASK_UPDATE OPTION_MASK_UPDATE #define MASK_VSX OPTION_MASK_VSX @@ -691,70 +541,40 @@ /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a - given system. The Paired builtins are only enabled if you configure the - compiler for those builtins, and those machines don't support altivec or - VSX. */ + given system. */ -#define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ - && ((TARGET_POWERPC64 \ - || TARGET_PPC_GPOPT /* 970/power4 */ \ - || TARGET_POPCNTB /* ISA 2.02 */ \ - || TARGET_CMPB /* ISA 2.05 */ \ - || TARGET_POPCNTD /* ISA 2.06 */ \ - || TARGET_ALTIVEC \ - || TARGET_VSX \ - || TARGET_HARD_FLOAT))) +#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ + || TARGET_PPC_GPOPT /* 970/power4 */ \ + || TARGET_POPCNTB /* ISA 2.02 */ \ + || TARGET_CMPB /* ISA 2.05 */ \ + || TARGET_POPCNTD /* ISA 2.06 */ \ + || TARGET_ALTIVEC \ + || TARGET_VSX \ + || TARGET_HARD_FLOAT) /* E500 cores only support plain "sync", not lwsync. */ #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ || rs6000_cpu == PROCESSOR_PPC8548) -/* Whether SF/DF operations are supported by the normal floating point unit - (or the vector/scalar unit). */ -#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT) -#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) +/* Which machine supports the various reciprocal estimate instructions. */ +#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) -/* Whether SF/DF operations are supported by any hardware. */ -#define TARGET_SF_INSN TARGET_SF_FPR -#define TARGET_DF_INSN TARGET_DF_FPR - -/* Which machine supports the various reciprocal estimate instructions. */ -#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ - && TARGET_SINGLE_FLOAT) - -#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ +#define TARGET_FRE (TARGET_HARD_FLOAT \ && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ - && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT) - -#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ - && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) + && TARGET_PPC_GFXOPT) -/* Conditions to allow TOC fusion for loading/storing integers. */ -#define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \ - && TARGET_TOC_FUSION \ - && (TARGET_CMODEL != CMODEL_SMALL) \ - && TARGET_POWERPC64) - -/* Conditions to allow TOC fusion for loading/storing floating point. */ -#define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \ - && TARGET_TOC_FUSION \ - && (TARGET_CMODEL != CMODEL_SMALL) \ - && TARGET_POWERPC64 \ - && TARGET_HARD_FLOAT \ - && TARGET_SINGLE_FLOAT \ - && TARGET_DOUBLE_FLOAT) +#define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ + && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) /* Macro to say whether we can do optimizations where we need to do parts of the calculation in 64-bit GPRs and then is transfered to the vector - registers. Do not allow -maltivec=be for these optimizations, because it - adds to the complexity of the code. */ + registers. */ #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ && TARGET_P8_VECTOR \ - && TARGET_POWERPC64 \ - && (rs6000_altivec_element_order != 2)) + && TARGET_POWERPC64) /* Whether the various reciprocal divide/square root estimate instructions exist, and whether we should automatically generate code for the instruction @@ -859,7 +679,6 @@ #define UNITS_PER_FP_WORD 8 #define UNITS_PER_ALTIVEC_WORD 16 #define UNITS_PER_VSX_WORD 16 -#define UNITS_PER_PAIRED_WORD 8 /* Type used for ptrdiff_t, as a string used in a declaration. */ #define PTRDIFF_TYPE "int" @@ -904,9 +723,8 @@ words. */ #define DOUBLE_TYPE_SIZE 64 -/* A C expression for the size in bits of the type `long double' on - the target machine. If you don't define this, the default is two - words. */ +/* A C expression for the size in bits of the type `long double' on the target + machine. If you don't define this, the default is two words. */ #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ @@ -1134,7 +952,7 @@ 33, \ 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 50, 49, 48, 47, 46, \ - 75, 73, 74, 69, 68, 72, 71, 70, \ + 68, 75, 73, 74, 69, 72, 71, 70, \ MAYBE_R2_AVAILABLE \ 9, 10, 8, 7, 6, 5, 4, \ 3, EARLY_R12 11, 0, \ @@ -1165,9 +983,6 @@ #define INT_REGNO_P(N) \ ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) -/* PAIRED SIMD registers are just the FPRs. */ -#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) - /* True if register is the CA register. */ #define CA_REGNO_P(N) ((N) == CA_REGNO) @@ -1228,9 +1043,6 @@ (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ || (MODE) == V2DImode || (MODE) == V1TImode) -#define PAIRED_VECTOR_MODE(MODE) \ - ((MODE) == V2SFmode) - /* Post-reload, we can't use any new AltiVec registers, as we already emitted the vrsave mask. */ @@ -1568,7 +1380,8 @@ This value must be a multiple of STACK_BOUNDARY (hard coded in `emit-rtl.c'). */ #define STACK_DYNAMIC_OFFSET(FUNDECL) \ - RS6000_ALIGN (crtl->outgoing_args_size + STACK_POINTER_OFFSET, \ + RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ + + STACK_POINTER_OFFSET, \ (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) /* If we generate an insn to push BYTES bytes, @@ -2479,8 +2292,8 @@ #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ /* Builtin targets. For now, we reuse the masks for those options that are in - target flags, and pick two random bits for paired and ldbl128, which - aren't in target_flags. */ + target flags, and pick a random bit for ldbl128, which isn't in + target_flags. */ #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ @@ -2490,7 +2303,6 @@ #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ -#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ @@ -2501,6 +2313,7 @@ #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ +#define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ @@ -2521,6 +2334,7 @@ | RS6000_BTM_DFP \ | RS6000_BTM_HARD_FLOAT \ | RS6000_BTM_LDBL128 \ + | RS6000_BTM_POWERPC64 \ | RS6000_BTM_FLOAT128 \ | RS6000_BTM_FLOAT128_HW) @@ -2534,7 +2348,6 @@ #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_X #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, @@ -2545,7 +2358,6 @@ #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, enum rs6000_builtins @@ -2563,27 +2375,21 @@ #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_X enum rs6000_builtin_type_index { RS6000_BTI_NOT_OPAQUE, - RS6000_BTI_opaque_V2SI, - RS6000_BTI_opaque_V2SF, - RS6000_BTI_opaque_p_V2SI, RS6000_BTI_opaque_V4SI, - RS6000_BTI_V16QI, + RS6000_BTI_V16QI, /* __vector signed char */ RS6000_BTI_V1TI, - RS6000_BTI_V2SI, - RS6000_BTI_V2SF, RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V4HI, RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V8HI, - RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, @@ -2591,8 +2397,14 @@ RS6000_BTI_bool_char, /* __bool char */ RS6000_BTI_bool_short, /* __bool short */ RS6000_BTI_bool_int, /* __bool int */ - RS6000_BTI_bool_long, /* __bool long */ - RS6000_BTI_pixel, /* __pixel */ + RS6000_BTI_bool_long_long, /* __bool long long */ + RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 + channels of 1, 5, 5, and 5 bits + respectively as packed with the + vpkpx insn. __pixel is only + meaningful as a vector type. + There is no corresponding scalar + __pixel data type.) */ RS6000_BTI_bool_V16QI, /* __vector __bool char */ RS6000_BTI_bool_V8HI, /* __vector __bool short */ RS6000_BTI_bool_V4SI, /* __vector __bool int */ @@ -2602,11 +2414,11 @@ RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ RS6000_BTI_long_long, /* long_long_integer_type_node */ RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ - RS6000_BTI_INTQI, /* intQI_type_node */ + RS6000_BTI_INTQI, /* (signed) intQI_type_node */ RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ RS6000_BTI_INTHI, /* intHI_type_node */ RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ - RS6000_BTI_INTSI, /* intSI_type_node */ + RS6000_BTI_INTSI, /* intSI_type_node (signed) */ RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ RS6000_BTI_INTDI, /* intDI_type_node */ RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ @@ -2625,16 +2437,11 @@ }; -#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) -#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) -#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) -#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) -#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) @@ -2647,7 +2454,7 @@ #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) -#define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) +#define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])