Mercurial > hg > CbC > CbC_gcc
diff gcc/config/i386/i386.h @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
---|---|
date | Mon, 24 May 2010 12:47:05 +0900 |
parents | 77e2b8dfacca |
children | f6334be47118 |
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--- a/gcc/config/i386/i386.h Fri Feb 12 23:41:23 2010 +0900 +++ b/gcc/config/i386/i386.h Mon May 24 12:47:05 2010 +0900 @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC for IA-32. Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, - 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 + 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. This file is part of GCC. @@ -240,6 +240,7 @@ #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) +#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) /* Feature tests against the various tunings. */ @@ -277,7 +278,9 @@ X86_TUNE_INTEGER_DFMODE_MOVES, X86_TUNE_PARTIAL_REG_DEPENDENCY, X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, - X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL, + X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, + X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, + X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, X86_TUNE_SSE_SPLIT_REGS, X86_TUNE_SSE_TYPELESS_STORES, X86_TUNE_SSE_LOAD0_BY_PXOR, @@ -352,8 +355,12 @@ ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] -#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ - ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL] +#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ + ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] +#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ + ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] +#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ + ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] #define TARGET_SSE_TYPELESS_STORES \ ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] @@ -429,7 +436,7 @@ #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) -#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) +#define TARGET_SUN_TLS 0 extern int ix86_isa_flags; @@ -591,6 +598,7 @@ TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, TARGET_CPU_DEFAULT_amdfam10, + TARGET_CPU_DEFAULT_bdver1, TARGET_CPU_DEFAULT_max }; @@ -955,7 +963,7 @@ registers listed in CALL_USED_REGISTERS, keeping the others available for storage of persistent values. - The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, + The ADJUST_REG_ALLOC_ORDER actually overwrite the order, so this is just empty initializer for array. */ #define REG_ALLOC_ORDER \ @@ -964,11 +972,11 @@ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52 } -/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order +/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order to be rearranged based on a particular function. When using sse math, we want to allocate SSE before x87 registers and vice versa. */ -#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () +#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) @@ -1296,11 +1304,11 @@ #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) -/* When defined, the compiler allows registers explicitly used in the - rtl to be used as spill registers but prevents the compiler from - extending the lifetime of these registers. */ - -#define SMALL_REGISTER_CLASSES 1 +/* When this hook returns true for MODE, the compiler allows + registers explicitly used in the rtl to be used as spill registers + but prevents the compiler from extending the lifetime of these + registers. */ +#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG) @@ -1554,8 +1562,6 @@ #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) -#define FUNCTION_VALUE_REGNO_P(N) ix86_function_value_regno_p (N) - /* Define how to find the value returned by a library function assuming the value has mode MODE. */ @@ -1580,7 +1586,8 @@ int words; /* # words passed so far */ int nregs; /* # registers available for passing */ int regno; /* next available register number */ - int fastcall; /* fastcall calling convention is used */ + int fastcall; /* fastcall or thiscall calling convention + is used */ int sse_words; /* # sse words passed so far */ int sse_nregs; /* # sse registers available for passing */ int warn_avx; /* True when we want to warn about AVX ABI. */ @@ -1627,9 +1634,6 @@ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ function_arg (&(CUM), (MODE), (TYPE), (NAMED)) -#define TARGET_ASM_FILE_END ix86_file_end -#define NEED_INDICATE_EXEC_STACK 0 - /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ @@ -1810,7 +1814,7 @@ #define X86_64_SSE_REGPARM_MAX 8 #define X86_64_MS_SSE_REGPARM_MAX 4 -#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0) +#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) #define SSE_REGPARM_MAX \ (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_SSE_REGPARM_MAX \ @@ -2150,9 +2154,12 @@ /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, and switch back. For x86 we do this only to save a few bytes that would otherwise be unused in the text section. */ -#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ - asm (SECTION_OP "\n\t" \ - "call " USER_LABEL_PREFIX #FUNC "\n" \ +#define CRT_MKSTR2(VAL) #VAL +#define CRT_MKSTR(x) CRT_MKSTR2(x) + +#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ + asm (SECTION_OP "\n\t" \ + "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ TEXT_SECTION_ASM_OP); /* Print operand X (an rtx) in assembler syntax to file FILE. @@ -2194,6 +2201,7 @@ PROCESSOR_GENERIC32, PROCESSOR_GENERIC64, PROCESSOR_AMDFAM10, + PROCESSOR_BDVER1, PROCESSOR_ATOM, PROCESSOR_max };