Mercurial > hg > CbC > CbC_gcc
diff gcc/ira-costs.c @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
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--- a/gcc/ira-costs.c Fri Feb 12 23:41:23 2010 +0900 +++ b/gcc/ira-costs.c Mon May 24 12:47:05 2010 +0900 @@ -224,6 +224,14 @@ int alt_fail = 0; int alt_cost = 0, op_cost_add; + if (!recog_data.alternative_enabled_p[alt]) + { + for (i = 0; i < recog_data.n_operands; i++) + constraints[i] = skip_alternative (constraints[i]); + + continue; + } + for (i = 0; i < n_ops; i++) { unsigned char c; @@ -1765,5 +1773,32 @@ } if (min_cost != INT_MAX) ALLOCNO_COVER_CLASS_COST (a) = min_cost; + + /* Some targets allow pseudos to be allocated to unaligned + sequences of hard registers. However, selecting an unaligned + sequence can unnecessarily restrict later allocations. So + increase the cost of unaligned hard regs to encourage the use + of aligned hard regs. */ + { + int nregs, index; + + if ((nregs = ira_reg_class_nregs[cover_class][ALLOCNO_MODE (a)]) > 1) + { + ira_allocate_and_set_costs + (&ALLOCNO_HARD_REG_COSTS (a), cover_class, + ALLOCNO_COVER_CLASS_COST (a)); + reg_costs = ALLOCNO_HARD_REG_COSTS (a); + for (j = n - 1; j >= 0; j--) + { + if (j % nregs != 0) + { + regno = ira_non_ordered_class_hard_regs[cover_class][j]; + index = ira_class_hard_reg_index[cover_class][regno]; + ira_assert (index != -1); + reg_costs[index] += ALLOCNO_FREQ (a); + } + } + } + } } }