--- a/gcc/config/pa/pa64-regs.h	Tue May 25 18:58:51 2010 +0900
+++ b/gcc/config/pa/pa64-regs.h	Tue Mar 22 17:18:12 2011 +0900
@@ -1,5 +1,5 @@
 /* Configuration for GCC-compiler for PA-RISC.
-   Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008
+   Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008, 2010
    Free Software Foundation, Inc.
 
 This file is part of GCC.
@@ -38,8 +38,8 @@
    issue as using the halves independently triggers false dependency stalls
    anyway.  */
 
-#define FIRST_PSEUDO_REGISTER 61  /* 32 general regs + 28 fp regs +
-				     + 1 shift reg */
+#define FIRST_PSEUDO_REGISTER 62  /* 32 general regs + 28 fp regs +
+				     + 1 shift reg + frame pointer */
 
 /* 1 for registers that have pervasive standard uses
    and are not available for the register allocator.
@@ -79,8 +79,8 @@
   0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0,		  \
-  /* shift register */	  \
-  0}
+  /* shift register and soft frame pointer */	  \
+  0, 1}
 
 /* 1 for registers not available across function calls.
    These must include the FIXED_REGISTERS and also any
@@ -98,20 +98,8 @@
   0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 1, 1, 1, 1, 1, 1, \
   1, 1, 1, 1, 		  \
-  /* shift register */    \
-  1}
-
-#define CONDITIONAL_REGISTER_USAGE \
-{						\
-  int i;					\
-  if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
-    {						\
-      for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-    }						\
-  if (flag_pic)					\
-    fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
-}
+  /* shift register and soft frame pointer */    \
+  1, 1}
 
 /* Allocate the call used registers first.  This should minimize
    the number of registers that need to be saved (as call used
@@ -137,7 +125,7 @@
    3,  4,  5,  6,  7,  8,  9, 10, 	\
   11, 12, 13, 14, 15, 16, 17, 18,	\
   /* special registers.  */		\
-   1, 27, 30,  0, 60}
+   1, 27, 30,  0, 60, 61}
 
 
 /* Return number of consecutive hard regs needed starting at reg REGNO
@@ -235,12 +223,12 @@
 #define REG_CLASS_CONTENTS	\
  {{0x00000000, 0x00000000},	/* NO_REGS */			\
   {0x00000002, 0x00000000},	/* R1_REGS */			\
-  {0xfffffffe, 0x00000000},	/* GENERAL_REGS */		\
+  {0xfffffffe, 0x20000000},	/* GENERAL_REGS */		\
   {0x00000000, 0x00000000},	/* FPUPPER_REGS */		\
   {0x00000000, 0x0fffffff},	/* FP_REGS */			\
-  {0xfffffffe, 0x0fffffff},	/* GENERAL_OR_FP_REGS */	\
+  {0xfffffffe, 0x2fffffff},	/* GENERAL_OR_FP_REGS */	\
   {0x00000000, 0x10000000},	/* SHIFT_REGS */		\
-  {0xfffffffe, 0x1fffffff}}	/* ALL_REGS */
+  {0xfffffffe, 0x3fffffff}}	/* ALL_REGS */
 
 /* The following macro defines cover classes for Integrated Register
    Allocator.  Cover classes is a set of non-intersected register
@@ -267,7 +255,7 @@
 #define REGNO_REG_CLASS(REGNO)						\
   ((REGNO) == 0 ? NO_REGS 						\
    : (REGNO) == 1 ? R1_REGS						\
-   : (REGNO) < 32 ? GENERAL_REGS					\
+   : (REGNO) < 32 || (REGNO) == 61 ? GENERAL_REGS			\
    : (REGNO) < 60 ? FP_REGS						\
    : SHIFT_REGS)
 
@@ -293,7 +281,7 @@
  "%fr4",  "%fr5",   "%fr6",  "%fr7",   "%fr8",  "%fr9",   "%fr10", "%fr11",  \
  "%fr12", "%fr13",  "%fr14", "%fr15",  "%fr16", "%fr17",  "%fr18", "%fr19",  \
  "%fr20", "%fr21",  "%fr22", "%fr23",  "%fr24", "%fr25",  "%fr26", "%fr27",  \
- "%fr28", "%fr29",  "%fr30", "%fr31", "SAR"}
+ "%fr28", "%fr29",  "%fr30", "%fr31",  "SAR",   "sfp"}
 
 #define ADDITIONAL_REGISTER_NAMES \
  {{"%cr11",60}}