;; Mips.md Machine Description for MIPS based processors
;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
;; Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org
;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
;; Brendan Eich, brendan@microunity.com.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; .
(define_constants
[(UNSPEC_LOAD_LOW 0)
(UNSPEC_LOAD_HIGH 1)
(UNSPEC_STORE_WORD 2)
(UNSPEC_GET_FNADDR 3)
(UNSPEC_BLOCKAGE 4)
(UNSPEC_CPRESTORE 5)
(UNSPEC_RESTORE_GP 6)
(UNSPEC_EH_RETURN 7)
(UNSPEC_CONSTTABLE_INT 8)
(UNSPEC_CONSTTABLE_FLOAT 9)
(UNSPEC_ALIGN 14)
(UNSPEC_HIGH 17)
(UNSPEC_LOAD_LEFT 18)
(UNSPEC_LOAD_RIGHT 19)
(UNSPEC_STORE_LEFT 20)
(UNSPEC_STORE_RIGHT 21)
(UNSPEC_LOADGP 22)
(UNSPEC_LOAD_CALL 23)
(UNSPEC_LOAD_GOT 24)
(UNSPEC_GP 25)
(UNSPEC_MFHI 26)
(UNSPEC_MTHI 27)
(UNSPEC_SET_HILO 28)
(UNSPEC_TLS_LDM 29)
(UNSPEC_TLS_GET_TP 30)
(UNSPEC_MFHC1 31)
(UNSPEC_MTHC1 32)
(UNSPEC_CLEAR_HAZARD 33)
(UNSPEC_RDHWR 34)
(UNSPEC_SYNCI 35)
(UNSPEC_SYNC 36)
(UNSPEC_COMPARE_AND_SWAP 37)
(UNSPEC_COMPARE_AND_SWAP_12 38)
(UNSPEC_SYNC_OLD_OP 39)
(UNSPEC_SYNC_NEW_OP 40)
(UNSPEC_SYNC_NEW_OP_12 41)
(UNSPEC_SYNC_OLD_OP_12 42)
(UNSPEC_SYNC_EXCHANGE 43)
(UNSPEC_SYNC_EXCHANGE_12 44)
(UNSPEC_MEMORY_BARRIER 45)
(UNSPEC_SET_GOT_VERSION 46)
(UNSPEC_UPDATE_GOT_VERSION 47)
(UNSPEC_COPYGP 48)
(UNSPEC_ADDRESS_FIRST 100)
(TLS_GET_TP_REGNUM 3)
(GOT_VERSION_REGNUM 79)
;; For MIPS Paired-Singled Floating Point Instructions.
(UNSPEC_MOVE_TF_PS 200)
(UNSPEC_C 201)
;; MIPS64/MIPS32R2 alnv.ps
(UNSPEC_ALNV_PS 202)
;; MIPS-3D instructions
(UNSPEC_CABS 203)
(UNSPEC_ADDR_PS 204)
(UNSPEC_CVT_PW_PS 205)
(UNSPEC_CVT_PS_PW 206)
(UNSPEC_MULR_PS 207)
(UNSPEC_ABS_PS 208)
(UNSPEC_RSQRT1 209)
(UNSPEC_RSQRT2 210)
(UNSPEC_RECIP1 211)
(UNSPEC_RECIP2 212)
(UNSPEC_SINGLE_CC 213)
(UNSPEC_SCC 214)
;; MIPS DSP ASE Revision 0.98 3/24/2005
(UNSPEC_ADDQ 300)
(UNSPEC_ADDQ_S 301)
(UNSPEC_SUBQ 302)
(UNSPEC_SUBQ_S 303)
(UNSPEC_ADDSC 304)
(UNSPEC_ADDWC 305)
(UNSPEC_MODSUB 306)
(UNSPEC_RADDU_W_QB 307)
(UNSPEC_ABSQ_S 308)
(UNSPEC_PRECRQ_QB_PH 309)
(UNSPEC_PRECRQ_PH_W 310)
(UNSPEC_PRECRQ_RS_PH_W 311)
(UNSPEC_PRECRQU_S_QB_PH 312)
(UNSPEC_PRECEQ_W_PHL 313)
(UNSPEC_PRECEQ_W_PHR 314)
(UNSPEC_PRECEQU_PH_QBL 315)
(UNSPEC_PRECEQU_PH_QBR 316)
(UNSPEC_PRECEQU_PH_QBLA 317)
(UNSPEC_PRECEQU_PH_QBRA 318)
(UNSPEC_PRECEU_PH_QBL 319)
(UNSPEC_PRECEU_PH_QBR 320)
(UNSPEC_PRECEU_PH_QBLA 321)
(UNSPEC_PRECEU_PH_QBRA 322)
(UNSPEC_SHLL 323)
(UNSPEC_SHLL_S 324)
(UNSPEC_SHRL_QB 325)
(UNSPEC_SHRA_PH 326)
(UNSPEC_SHRA_R 327)
(UNSPEC_MULEU_S_PH_QBL 328)
(UNSPEC_MULEU_S_PH_QBR 329)
(UNSPEC_MULQ_RS_PH 330)
(UNSPEC_MULEQ_S_W_PHL 331)
(UNSPEC_MULEQ_S_W_PHR 332)
(UNSPEC_DPAU_H_QBL 333)
(UNSPEC_DPAU_H_QBR 334)
(UNSPEC_DPSU_H_QBL 335)
(UNSPEC_DPSU_H_QBR 336)
(UNSPEC_DPAQ_S_W_PH 337)
(UNSPEC_DPSQ_S_W_PH 338)
(UNSPEC_MULSAQ_S_W_PH 339)
(UNSPEC_DPAQ_SA_L_W 340)
(UNSPEC_DPSQ_SA_L_W 341)
(UNSPEC_MAQ_S_W_PHL 342)
(UNSPEC_MAQ_S_W_PHR 343)
(UNSPEC_MAQ_SA_W_PHL 344)
(UNSPEC_MAQ_SA_W_PHR 345)
(UNSPEC_BITREV 346)
(UNSPEC_INSV 347)
(UNSPEC_REPL_QB 348)
(UNSPEC_REPL_PH 349)
(UNSPEC_CMP_EQ 350)
(UNSPEC_CMP_LT 351)
(UNSPEC_CMP_LE 352)
(UNSPEC_CMPGU_EQ_QB 353)
(UNSPEC_CMPGU_LT_QB 354)
(UNSPEC_CMPGU_LE_QB 355)
(UNSPEC_PICK 356)
(UNSPEC_PACKRL_PH 357)
(UNSPEC_EXTR_W 358)
(UNSPEC_EXTR_R_W 359)
(UNSPEC_EXTR_RS_W 360)
(UNSPEC_EXTR_S_H 361)
(UNSPEC_EXTP 362)
(UNSPEC_EXTPDP 363)
(UNSPEC_SHILO 364)
(UNSPEC_MTHLIP 365)
(UNSPEC_WRDSP 366)
(UNSPEC_RDDSP 367)
;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
(UNSPEC_ABSQ_S_QB 400)
(UNSPEC_ADDU_PH 401)
(UNSPEC_ADDU_S_PH 402)
(UNSPEC_ADDUH_QB 403)
(UNSPEC_ADDUH_R_QB 404)
(UNSPEC_APPEND 405)
(UNSPEC_BALIGN 406)
(UNSPEC_CMPGDU_EQ_QB 407)
(UNSPEC_CMPGDU_LT_QB 408)
(UNSPEC_CMPGDU_LE_QB 409)
(UNSPEC_DPA_W_PH 410)
(UNSPEC_DPS_W_PH 411)
(UNSPEC_MADD 412)
(UNSPEC_MADDU 413)
(UNSPEC_MSUB 414)
(UNSPEC_MSUBU 415)
(UNSPEC_MUL_PH 416)
(UNSPEC_MUL_S_PH 417)
(UNSPEC_MULQ_RS_W 418)
(UNSPEC_MULQ_S_PH 419)
(UNSPEC_MULQ_S_W 420)
(UNSPEC_MULSA_W_PH 421)
(UNSPEC_MULT 422)
(UNSPEC_MULTU 423)
(UNSPEC_PRECR_QB_PH 424)
(UNSPEC_PRECR_SRA_PH_W 425)
(UNSPEC_PRECR_SRA_R_PH_W 426)
(UNSPEC_PREPEND 427)
(UNSPEC_SHRA_QB 428)
(UNSPEC_SHRA_R_QB 429)
(UNSPEC_SHRL_PH 430)
(UNSPEC_SUBU_PH 431)
(UNSPEC_SUBU_S_PH 432)
(UNSPEC_SUBUH_QB 433)
(UNSPEC_SUBUH_R_QB 434)
(UNSPEC_ADDQH_PH 435)
(UNSPEC_ADDQH_R_PH 436)
(UNSPEC_ADDQH_W 437)
(UNSPEC_ADDQH_R_W 438)
(UNSPEC_SUBQH_PH 439)
(UNSPEC_SUBQH_R_PH 440)
(UNSPEC_SUBQH_W 441)
(UNSPEC_SUBQH_R_W 442)
(UNSPEC_DPAX_W_PH 443)
(UNSPEC_DPSX_W_PH 444)
(UNSPEC_DPAQX_S_W_PH 445)
(UNSPEC_DPAQX_SA_W_PH 446)
(UNSPEC_DPSQX_S_W_PH 447)
(UNSPEC_DPSQX_SA_W_PH 448)
;; ST Microelectronics Loongson-2E/2F.
(UNSPEC_LOONGSON_PAVG 500)
(UNSPEC_LOONGSON_PCMPEQ 501)
(UNSPEC_LOONGSON_PCMPGT 502)
(UNSPEC_LOONGSON_PEXTR 503)
(UNSPEC_LOONGSON_PINSR_0 504)
(UNSPEC_LOONGSON_PINSR_1 505)
(UNSPEC_LOONGSON_PINSR_2 506)
(UNSPEC_LOONGSON_PINSR_3 507)
(UNSPEC_LOONGSON_PMADD 508)
(UNSPEC_LOONGSON_PMOVMSK 509)
(UNSPEC_LOONGSON_PMULHU 510)
(UNSPEC_LOONGSON_PMULH 511)
(UNSPEC_LOONGSON_PMULL 512)
(UNSPEC_LOONGSON_PMULU 513)
(UNSPEC_LOONGSON_PASUBUB 514)
(UNSPEC_LOONGSON_BIADD 515)
(UNSPEC_LOONGSON_PSADBH 516)
(UNSPEC_LOONGSON_PSHUFH 517)
(UNSPEC_LOONGSON_PUNPCKH 518)
(UNSPEC_LOONGSON_PUNPCKL 519)
(UNSPEC_LOONGSON_PADDD 520)
(UNSPEC_LOONGSON_PSUBD 521)
;; Used in loongson2ef.md
(UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
(UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
(UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
(UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
(UNSPEC_MIPS_CACHE 600)
(UNSPEC_R10K_CACHE_BARRIER 601)
]
)
(include "predicates.md")
(include "constraints.md")
;; ....................
;;
;; Attributes
;;
;; ....................
(define_attr "got" "unset,xgot_high,load"
(const_string "unset"))
;; For jal instructions, this attribute is DIRECT when the target address
;; is symbolic and INDIRECT when it is a register.
(define_attr "jal" "unset,direct,indirect"
(const_string "unset"))
;; This attribute is YES if the instruction is a jal macro (not a
;; real jal instruction).
;;
;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
;; an instruction to restore $gp. Direct jals are also macros for
;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
;; the target address into a register.
(define_attr "jal_macro" "no,yes"
(cond [(eq_attr "jal" "direct")
(symbol_ref "TARGET_CALL_CLOBBERED_GP
|| (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
(eq_attr "jal" "indirect")
(symbol_ref "TARGET_CALL_CLOBBERED_GP")]
(const_string "no")))
;; Classification of moves, extensions and truncations. Most values
;; are as for "type" (see below) but there are also the following
;; move-specific values:
;;
;; constN move an N-constraint integer into a MIPS16 register
;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
;; to produce a sign-extended DEST, even if SRC is not
;; properly sign-extended
;; andi a single ANDI instruction
;; loadpool move a constant into a MIPS16 register by loading it
;; from the pool
;; shift_shift a shift left followed by a shift right
;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
;;
;; This attribute is used to determine the instruction's length and
;; scheduling type. For doubleword moves, the attribute always describes
;; the split instructions; in some cases, it is more appropriate for the
;; scheduling type to be "multi" instead.
(define_attr "move_type"
"unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
(const_string "unknown"))
;; Main data type used by the insn
(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
(const_string "unknown"))
;; True if the main data type is twice the size of a word.
(define_attr "dword_mode" "no,yes"
(cond [(and (eq_attr "mode" "DI,DF")
(eq (symbol_ref "TARGET_64BIT") (const_int 0)))
(const_string "yes")
(and (eq_attr "mode" "TI,TF")
(ne (symbol_ref "TARGET_64BIT") (const_int 0)))
(const_string "yes")]
(const_string "no")))
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
;; call unconditional call
;; load load instruction(s)
;; fpload floating point load
;; fpidxload floating point indexed load
;; store store instruction(s)
;; fpstore floating point store
;; fpidxstore floating point indexed store
;; prefetch memory prefetch (register + offset)
;; prefetchx memory indexed prefetch (register + register)
;; condmove conditional moves
;; mtc transfer to coprocessor
;; mfc transfer from coprocessor
;; mthilo transfer to hi/lo registers
;; mfhilo transfer from hi/lo registers
;; const load constant
;; arith integer arithmetic instructions
;; logical integer logical instructions
;; shift integer shift instructions
;; slt set less than instructions
;; signext sign extend instructions
;; clz the clz and clo instructions
;; pop the pop instruction
;; trap trap if instructions
;; imul integer multiply 2 operands
;; imul3 integer multiply 3 operands
;; imul3nc integer multiply 3 operands without clobbering HI/LO
;; imadd integer multiply-add
;; idiv integer divide 2 operands
;; idiv3 integer divide 3 operands
;; move integer register move ({,D}ADD{,U} with rt = 0)
;; fmove floating point register move
;; fadd floating point add/subtract
;; fmul floating point multiply
;; fmadd floating point multiply-add
;; fdiv floating point divide
;; frdiv floating point reciprocal divide
;; frdiv1 floating point reciprocal divide step 1
;; frdiv2 floating point reciprocal divide step 2
;; fabs floating point absolute value
;; fneg floating point negation
;; fcmp floating point compare
;; fcvt floating point convert
;; fsqrt floating point square root
;; frsqrt floating point reciprocal square root
;; frsqrt1 floating point reciprocal square root step1
;; frsqrt2 floating point reciprocal square root step2
;; multi multiword sequence (or user asm statements)
;; nop no operation
;; ghost an instruction that produces no real code
(define_attr "type"
"unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")
;; If a doubleword move uses these expensive instructions,
;; it is usually better to schedule them in the same way
;; as the singleword form, rather than as "multi".
(eq_attr "move_type" "load") (const_string "load")
(eq_attr "move_type" "fpload") (const_string "fpload")
(eq_attr "move_type" "store") (const_string "store")
(eq_attr "move_type" "fpstore") (const_string "fpstore")
(eq_attr "move_type" "mtc") (const_string "mtc")
(eq_attr "move_type" "mfc") (const_string "mfc")
(eq_attr "move_type" "mthilo") (const_string "mthilo")
(eq_attr "move_type" "mfhilo") (const_string "mfhilo")
;; These types of move are always single insns.
(eq_attr "move_type" "fmove") (const_string "fmove")
(eq_attr "move_type" "loadpool") (const_string "load")
(eq_attr "move_type" "signext") (const_string "signext")
(eq_attr "move_type" "sll0") (const_string "shift")
(eq_attr "move_type" "andi") (const_string "logical")
;; These types of move are always split.
(eq_attr "move_type" "constN,shift_shift")
(const_string "multi")
;; These types of move are split for doubleword modes only.
(and (eq_attr "move_type" "move,const")
(eq_attr "dword_mode" "yes"))
(const_string "multi")
(eq_attr "move_type" "move") (const_string "move")
(eq_attr "move_type" "const") (const_string "const")]
;; We classify "lui_movf" as "unknown" rather than "multi"
;; because we don't split it. FIXME: we should split instead.
(const_string "unknown")))
;; Mode for conversion types (fcvt)
;; I2S integer to float single (SI/DI to SF)
;; I2D integer to float double (SI/DI to DF)
;; S2I float to integer (SF to SI/DI)
;; D2I float to integer (DF to SI/DI)
;; D2S double to float single
;; S2D float single to double
(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
(const_string "unknown"))
;; Is this an extended instruction in mips16 mode?
(define_attr "extended_mips16" "no,yes"
(if_then_else (ior (eq_attr "move_type" "sll0")
(eq_attr "type" "branch")
(eq_attr "jal" "direct"))
(const_string "yes")
(const_string "no")))
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [(and (eq_attr "extended_mips16" "yes")
(ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
(const_int 8)
;; Direct branch instructions have a range of [-0x40000,0x3fffc].
;; If a branch is outside this range, we have a choice of two
;; sequences. For PIC, an out-of-range branch like:
;;
;; bne r1,r2,target
;; dslot
;;
;; becomes the equivalent of:
;;
;; beq r1,r2,1f
;; dslot
;; la $at,target
;; jr $at
;; nop
;; 1:
;;
;; where the load address can be up to three instructions long
;; (lw, nop, addiu).
;;
;; The non-PIC case is similar except that we use a direct
;; jump instead of an la/jr pair. Since the target of this
;; jump is an absolute 28-bit bit address (the other bits
;; coming from the address of the delay slot) this form cannot
;; cross a 256MB boundary. We could provide the option of
;; using la/jr in this case too, but we do not do so at
;; present.
;;
;; Note that this value does not account for the delay slot
;; instruction, whose length is added separately. If the RTL
;; pattern has no explicit delay slot, mips_adjust_insn_length
;; will add the length of the implicit nop. The values for
;; forward and backward branches will be different as well.
(eq_attr "type" "branch")
(cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
(le (minus (pc) (match_dup 1)) (const_int 131068)))
(const_int 4)
(ne (symbol_ref "flag_pic") (const_int 0))
(const_int 24)
] (const_int 12))
;; "Ghost" instructions occupy no space.
(eq_attr "type" "ghost")
(const_int 0)
(eq_attr "got" "load")
(if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
(const_int 8)
(const_int 4))
(eq_attr "got" "xgot_high")
(const_int 8)
;; In general, constant-pool loads are extended instructions.
(eq_attr "move_type" "loadpool")
(const_int 8)
;; LUI_MOVFs are decomposed into two separate instructions.
(eq_attr "move_type" "lui_movf")
(const_int 8)
;; SHIFT_SHIFTs are decomposed into two separate instructions.
;; They are extended instructions on MIPS16 targets.
(eq_attr "move_type" "shift_shift")
(if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
(const_int 16)
(const_int 8))
;; Check for doubleword moves that are decomposed into two
;; instructions.
(and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
(eq_attr "dword_mode" "yes"))
(const_int 8)
;; Doubleword CONST{,N} moves are split into two word
;; CONST{,N} moves.
(and (eq_attr "move_type" "const,constN")
(eq_attr "dword_mode" "yes"))
(symbol_ref "mips_split_const_insns (operands[1]) * 4")
;; Otherwise, constants, loads and stores are handled by external
;; routines.
(eq_attr "move_type" "const,constN")
(symbol_ref "mips_const_insns (operands[1]) * 4")
(eq_attr "move_type" "load,fpload")
(symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
(eq_attr "move_type" "store,fpstore")
(symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
;; In the worst case, a call macro will take 8 instructions:
;;
;; lui $25,%call_hi(FOO)
;; addu $25,$25,$28
;; lw $25,%call_lo(FOO)($25)
;; nop
;; jalr $25
;; nop
;; lw $gp,X($sp)
;; nop
(eq_attr "jal_macro" "yes")
(const_int 32)
;; Various VR4120 errata require a nop to be inserted after a macc
;; instruction. The assembler does this for us, so account for
;; the worst-case length here.
(and (eq_attr "type" "imadd")
(ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
(const_int 8)
;; VR4120 errata MD(4): if there are consecutive dmult instructions,
;; the result of the second one is missed. The assembler should work
;; around this by inserting a nop after the first dmult.
(and (eq_attr "type" "imul,imul3")
(and (eq_attr "mode" "DI")
(ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
(const_int 8)
(eq_attr "type" "idiv,idiv3")
(symbol_ref "mips_idiv_insns () * 4")
] (const_int 4)))
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
;; DELAY means that the next instruction cannot read the result
;; of this one. HILO means that the next two instructions cannot
;; write to HI or LO.
(define_attr "hazard" "none,delay,hilo"
(cond [(and (eq_attr "type" "load,fpload,fpidxload")
(ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
(const_string "delay")
(and (eq_attr "type" "mfc,mtc")
(ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
(const_string "delay")
(and (eq_attr "type" "fcmp")
(ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
(const_string "delay")
;; The r4000 multiplication patterns include an mflo instruction.
(and (eq_attr "type" "imul")
(ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
(const_string "hilo")
(and (eq_attr "type" "mfhilo")
(eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
(const_string "hilo")]
(const_string "none")))
;; Is it a single instruction?
(define_attr "single_insn" "no,yes"
(symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
;; Can the instruction be put into a delay slot?
(define_attr "can_delay" "no,yes"
(if_then_else (and (eq_attr "type" "!branch,call,jump")
(and (eq_attr "hazard" "none")
(eq_attr "single_insn" "yes")))
(const_string "yes")
(const_string "no")))
;; Attribute defining whether or not we can use the branch-likely
;; instructions.
(define_attr "branch_likely" "no,yes"
(if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
(const_string "yes")
(const_string "no")))
;; True if an instruction might assign to hi or lo when reloaded.
;; This is used by the TUNE_MACC_CHAINS code.
(define_attr "may_clobber_hilo" "no,yes"
(if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
(const_string "yes")
(const_string "no")))
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "type" "multi")
(set_attr "can_delay" "no")])
;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
;; from the same template.
(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
;; A copy of GPR that can be used when a pattern has two independent
;; modes.
(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
;; This mode iterator allows :HILO to be used as the mode of the
;; concatenated HI and LO registers.
(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
;; This mode iterator allows :MOVECC to be used anywhere that a
;; conditional-move-type condition is needed.
(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
(CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
;; 32-bit integer moves for which we provide move patterns.
(define_mode_iterator IMOVE32
[SI
(V2HI "TARGET_DSP")
(V4QI "TARGET_DSP")
(V2HQ "TARGET_DSP")
(V2UHQ "TARGET_DSP")
(V2HA "TARGET_DSP")
(V2UHA "TARGET_DSP")
(V4QQ "TARGET_DSP")
(V4UQQ "TARGET_DSP")])
;; 64-bit modes for which we provide move patterns.
(define_mode_iterator MOVE64
[DI DF
(V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
(V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
(V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
(V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
;; 128-bit modes for which we provide move patterns on 64-bit targets.
(define_mode_iterator MOVE128 [TI TF])
;; This mode iterator allows the QI and HI extension patterns to be
;; defined from the same template.
(define_mode_iterator SHORT [QI HI])
;; Likewise the 64-bit truncate-and-shift patterns.
(define_mode_iterator SUBDI [QI HI SI])
;; This mode iterator allows :ANYF to be used wherever a scalar or vector
;; floating-point mode is allowed.
(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
(DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
(V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
;; Like ANYF, but only applies to scalar modes.
(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
(DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
;; A floating-point mode for which moves involving FPRs may need to be split.
(define_mode_iterator SPLITF
[(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
(DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
(V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
(V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(TF "TARGET_64BIT && TARGET_FLOAT64")])
;; In GPR templates, a string like "subu" will expand to "subu" in the
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr d [(SI "") (DI "d")
(QQ "") (HQ "") (SQ "") (DQ "d")
(UQQ "") (UHQ "") (USQ "") (UDQ "d")
(HA "") (SA "") (DA "d")
(UHA "") (USA "") (UDA "d")])
;; Same as d but upper-case.
(define_mode_attr D [(SI "") (DI "D")
(QQ "") (HQ "") (SQ "") (DQ "D")
(UQQ "") (UHQ "") (USQ "") (UDQ "D")
(HA "") (SA "") (DA "D")
(UHA "") (USA "") (UDA "D")])
;; This attribute gives the length suffix for a sign- or zero-extension
;; instruction.
(define_mode_attr size [(QI "b") (HI "h")])
;; This attributes gives the mode mask of a SHORT.
(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
;; Mode attributes for GPR loads and stores.
(define_mode_attr load [(SI "lw") (DI "ld")])
(define_mode_attr store [(SI "sw") (DI "sd")])
;; Similarly for MIPS IV indexed FPR loads and stores.
(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
;; The unextended ranges of the MIPS16 addiu and daddiu instructions
;; are different. Some forms of unextended addiu have an 8-bit immediate
;; field but the equivalent daddiu has only a 5-bit field.
(define_mode_attr si8_di5 [(SI "8") (DI "5")])
;; This attribute gives the best constraint to use for registers of
;; a given mode.
(define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
;; This attribute gives the format suffix for floating-point operations.
(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
;; This attribute gives the upper-case mode name for one unit of a
;; floating-point mode.
(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
;; This attribute gives the integer mode that has the same size as a
;; fixed-point mode.
(define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
(UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
(HA "HI") (SA "SI") (DA "DI")
(UHA "HI") (USA "SI") (UDA "DI")
(V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
(V2HQ "SI") (V2HA "SI")])
;; This attribute gives the integer mode that has half the size of
;; the controlling mode.
(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
(V2SI "SI") (V4HI "SI") (V8QI "SI")
(TF "DI")])
;; This attribute works around the early SB-1 rev2 core "F2" erratum:
;;
;; In certain cases, div.s and div.ps may have a rounding error
;; and/or wrong inexact flag.
;;
;; Therefore, we only allow div.s if not working around SB-1 rev2
;; errata or if a slight loss of precision is OK.
(define_mode_attr divide_condition
[DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
(V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
;; This attribute gives the conditions under which SQRT.fmt instructions
;; can be used.
(define_mode_attr sqrt_condition
[(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
;; so for safety's sake, we apply this restriction to all targets.
(define_mode_attr recip_condition
[(SF "ISA_HAS_FP4")
(DF "ISA_HAS_FP4 && TARGET_FLOAT64")
(V2SF "TARGET_SB1")])
;; This code iterator allows all branch instructions to be generated from
;; a single define_expand template.
(define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
eq ne gt ge lt le gtu geu ltu leu])
;; This code iterator allows signed and unsigned widening multiplications
;; to use the same template.
(define_code_iterator any_extend [sign_extend zero_extend])
;; This code iterator allows the two right shift instructions to be
;; generated from the same template.
(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
;; This code iterator allows the three shift instructions to be generated
;; from the same template.
(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
;; This code iterator allows unsigned and signed division to be generated
;; from the same template.
(define_code_iterator any_div [div udiv])
;; This code iterator allows unsigned and signed modulus to be generated
;; from the same template.
(define_code_iterator any_mod [mod umod])
;; This code iterator allows all native floating-point comparisons to be
;; generated from the same template.
(define_code_iterator fcond [unordered uneq unlt unle eq lt le])
;; This code iterator is used for comparisons that can be implemented
;; by swapping the operands.
(define_code_iterator swapped_fcond [ge gt unge ungt])
;; Equality operators.
(define_code_iterator equality_op [eq ne])
;; These code iterators allow the signed and unsigned scc operations to use
;; the same template.
(define_code_iterator any_gt [gt gtu])
(define_code_iterator any_ge [ge geu])
(define_code_iterator any_lt [lt ltu])
(define_code_iterator any_le [le leu])
;; expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
(define_code_attr u [(sign_extend "") (zero_extend "u")
(div "") (udiv "u")
(mod "") (umod "u")
(gt "") (gtu "u")
(ge "") (geu "u")
(lt "") (ltu "u")
(le "") (leu "u")])
;; is like , but the signed form expands to "s" rather than "".
(define_code_attr su [(sign_extend "s") (zero_extend "u")])
;; expands to the name of the optab for a particular code.
(define_code_attr optab [(ashift "ashl")
(ashiftrt "ashr")
(lshiftrt "lshr")
(ior "ior")
(xor "xor")
(and "and")
(plus "add")
(minus "sub")])
;; expands to the name of the insn that implements a particular code.
(define_code_attr insn [(ashift "sll")
(ashiftrt "sra")
(lshiftrt "srl")
(ior "or")
(xor "xor")
(and "and")
(plus "addu")
(minus "subu")])
;; expands to the name of the insn that implements
;; a particular code to operate on immediate values.
(define_code_attr immediate_insn [(ior "ori")
(xor "xori")
(and "andi")])
;; is the c.cond.fmt condition associated with a particular code.
(define_code_attr fcond [(unordered "un")
(uneq "ueq")
(unlt "ult")
(unle "ule")
(eq "eq")
(lt "lt")
(le "le")])
;; Similar, but for swapped conditions.
(define_code_attr swapped_fcond [(ge "le")
(gt "lt")
(unge "ule")
(ungt "ult")])
;; The value of the bit when the branch is taken for branch_bit patterns.
;; Comparison is always against zero so this depends on the operator.
(define_code_attr bbv [(eq "0") (ne "1")])
;; This is the inverse value of bbv.
(define_code_attr bbinv [(eq "1") (ne "0")])
;; .........................
;;
;; Branch, call and jump delay slots
;;
;; .........................
(define_delay (and (eq_attr "type" "branch")
(eq (symbol_ref "TARGET_MIPS16") (const_int 0))
(eq_attr "branch_likely" "yes"))
[(eq_attr "can_delay" "yes")
(nil)
(eq_attr "can_delay" "yes")])
;; Branches that don't have likely variants do not annul on false.
(define_delay (and (eq_attr "type" "branch")
(eq (symbol_ref "TARGET_MIPS16") (const_int 0))
(eq_attr "branch_likely" "no"))
[(eq_attr "can_delay" "yes")
(nil)
(nil)])
(define_delay (eq_attr "type" "jump")
[(eq_attr "can_delay" "yes")
(nil)
(nil)])
(define_delay (and (eq_attr "type" "call")
(eq_attr "jal_macro" "no"))
[(eq_attr "can_delay" "yes")
(nil)
(nil)])
;; Pipeline descriptions.
;;
;; generic.md provides a fallback for processors without a specific
;; pipeline description. It is derived from the old define_function_unit
;; version and uses the "alu" and "imuldiv" units declared below.
;;
;; Some of the processor-specific files are also derived from old
;; define_function_unit descriptions and simply override the parts of
;; generic.md that don't apply. The other processor-specific files
;; are self-contained.
(define_automaton "alu,imuldiv")
(define_cpu_unit "alu" "alu")
(define_cpu_unit "imuldiv" "imuldiv")
;; Ghost instructions produce no real code and introduce no hazards.
;; They exist purely to express an effect on dataflow.
(define_insn_reservation "ghost" 0
(eq_attr "type" "ghost")
"nothing")
(include "4k.md")
(include "5k.md")
(include "20kc.md")
(include "24k.md")
(include "74k.md")
(include "3000.md")
(include "4000.md")
(include "4100.md")
(include "4130.md")
(include "4300.md")
(include "4600.md")
(include "5000.md")
(include "5400.md")
(include "5500.md")
(include "6000.md")
(include "7000.md")
(include "9000.md")
(include "10000.md")
(include "loongson2ef.md")
(include "octeon.md")
(include "sb1.md")
(include "sr71k.md")
(include "xlr.md")
(include "generic.md")
;;
;; ....................
;;
;; CONDITIONAL TRAPS
;;
;; ....................
;;
(define_insn "trap"
[(trap_if (const_int 1) (const_int 0))]
""
{
if (ISA_HAS_COND_TRAP)
return "teq\t$0,$0";
else if (TARGET_MIPS16)
return "break 0";
else
return "break";
}
[(set_attr "type" "trap")])
(define_expand "conditional_trap"
[(trap_if (match_operator 0 "comparison_operator"
[(match_dup 2) (match_dup 3)])
(match_operand 1 "const_int_operand"))]
"ISA_HAS_COND_TRAP"
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
&& operands[1] == const0_rtx)
{
mips_expand_conditional_trap (GET_CODE (operands[0]));
DONE;
}
FAIL;
})
(define_insn "*conditional_trap"
[(trap_if (match_operator:GPR 0 "trap_comparison_operator"
[(match_operand:GPR 1 "reg_or_0_operand" "dJ")
(match_operand:GPR 2 "arith_operand" "dI")])
(const_int 0))]
"ISA_HAS_COND_TRAP"
"t%C0\t%z1,%2"
[(set_attr "type" "trap")])
;;
;; ....................
;;
;; ADDITION
;;
;; ....................
;;
(define_insn "add3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
""
"add.\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "")])
(define_expand "add3"
[(set (match_operand:GPR 0 "register_operand")
(plus:GPR (match_operand:GPR 1 "register_operand")
(match_operand:GPR 2 "arith_operand")))]
"")
(define_insn "*add3"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
(match_operand:GPR 2 "arith_operand" "d,Q")))]
"!TARGET_MIPS16"
"@
addu\t%0,%1,%2
addiu\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "")])
(define_insn "*add3_mips16"
[(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
(plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
(match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
"TARGET_MIPS16"
"@
addiu\t%0,%2
addiu\t%0,%1,%2
addiu\t%0,%2
addiu\t%0,%1,%2
addu\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "")
(set_attr_alternative "length"
[(if_then_else (match_operand 2 "m16_simm8_8")
(const_int 4)
(const_int 8))
(if_then_else (match_operand 2 "m16_uimm_4")
(const_int 4)
(const_int 8))
(if_then_else (match_operand 2 "m16_simm_1")
(const_int 4)
(const_int 8))
(if_then_else (match_operand 2 "m16_simm4_1")
(const_int 4)
(const_int 8))
(const_int 4)])])
;; On the mips16, we can sometimes split an add of a constant which is
;; a 4 byte instruction into two adds which are both 2 byte
;; instructions. There are two cases: one where we are adding a
;; constant plus a register to another register, and one where we are
;; simply adding a constant to a register.
(define_split
[(set (match_operand:SI 0 "d_operand")
(plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& ((INTVAL (operands[1]) > 0x7f
&& INTVAL (operands[1]) <= 0x7f + 0x7f)
|| (INTVAL (operands[1]) < - 0x80
&& INTVAL (operands[1]) >= - 0x80 - 0x80))"
[(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
{
HOST_WIDE_INT val = INTVAL (operands[1]);
if (val >= 0)
{
operands[1] = GEN_INT (0x7f);
operands[2] = GEN_INT (val - 0x7f);
}
else
{
operands[1] = GEN_INT (- 0x80);
operands[2] = GEN_INT (val + 0x80);
}
})
(define_split
[(set (match_operand:SI 0 "d_operand")
(plus:SI (match_operand:SI 1 "d_operand")
(match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& REGNO (operands[0]) != REGNO (operands[1])
&& ((INTVAL (operands[2]) > 0x7
&& INTVAL (operands[2]) <= 0x7 + 0x7f)
|| (INTVAL (operands[2]) < - 0x8
&& INTVAL (operands[2]) >= - 0x8 - 0x80))"
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
{
HOST_WIDE_INT val = INTVAL (operands[2]);
if (val >= 0)
{
operands[2] = GEN_INT (0x7);
operands[3] = GEN_INT (val - 0x7);
}
else
{
operands[2] = GEN_INT (- 0x8);
operands[3] = GEN_INT (val + 0x8);
}
})
(define_split
[(set (match_operand:DI 0 "d_operand")
(plus:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
&& ((INTVAL (operands[1]) > 0xf
&& INTVAL (operands[1]) <= 0xf + 0xf)
|| (INTVAL (operands[1]) < - 0x10
&& INTVAL (operands[1]) >= - 0x10 - 0x10))"
[(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
{
HOST_WIDE_INT val = INTVAL (operands[1]);
if (val >= 0)
{
operands[1] = GEN_INT (0xf);
operands[2] = GEN_INT (val - 0xf);
}
else
{
operands[1] = GEN_INT (- 0x10);
operands[2] = GEN_INT (val + 0x10);
}
})
(define_split
[(set (match_operand:DI 0 "d_operand")
(plus:DI (match_operand:DI 1 "d_operand")
(match_operand:DI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
&& REGNO (operands[0]) != REGNO (operands[1])
&& ((INTVAL (operands[2]) > 0x7
&& INTVAL (operands[2]) <= 0x7 + 0xf)
|| (INTVAL (operands[2]) < - 0x8
&& INTVAL (operands[2]) >= - 0x8 - 0x10))"
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
{
HOST_WIDE_INT val = INTVAL (operands[2]);
if (val >= 0)
{
operands[2] = GEN_INT (0x7);
operands[3] = GEN_INT (val - 0x7);
}
else
{
operands[2] = GEN_INT (- 0x8);
operands[3] = GEN_INT (val + 0x8);
}
})
(define_insn "*addsi3_extended"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(sign_extend:DI
(plus:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "arith_operand" "d,Q"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"@
addu\t%0,%1,%2
addiu\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
;; Split this insn so that the addiu splitters can have a crack at it.
;; Use a conservative length estimate until the split.
(define_insn_and_split "*addsi3_extended_mips16"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI
(plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
(match_operand:SI 2 "arith_operand" "Q,O,d"))))]
"TARGET_64BIT && TARGET_MIPS16"
"#"
"&& reload_completed"
[(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
{ operands[3] = gen_lowpart (SImode, operands[0]); }
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr "extended_mips16" "yes")])
;; Combiner patterns for unsigned byte-add.
(define_insn "*baddu_si_eb"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI
(subreg:QI
(plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")) 3)))]
"ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
"baddu\\t%0,%1,%2"
[(set_attr "type" "arith")])
(define_insn "*baddu_si_el"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI
(subreg:QI
(plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")) 0)))]
"ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
"baddu\\t%0,%1,%2"
[(set_attr "type" "arith")])
(define_insn "*baddu_di"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extend:GPR
(truncate:QI
(plus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))))]
"ISA_HAS_BADDU && TARGET_64BIT"
"baddu\\t%0,%1,%2"
[(set_attr "type" "arith")])
;;
;; ....................
;;
;; SUBTRACTION
;;
;; ....................
;;
(define_insn "sub3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
""
"sub.\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "")])
(define_insn "sub3"
[(set (match_operand:GPR 0 "register_operand" "=d")
(minus:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))]
""
"subu\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "")])
(define_insn "*subsi3_extended"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI
(minus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
"TARGET_64BIT"
"subu\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
;;
;; ....................
;;
;; MULTIPLICATION
;;
;; ....................
;;
(define_expand "mul3"
[(set (match_operand:SCALARF 0 "register_operand")
(mult:SCALARF (match_operand:SCALARF 1 "register_operand")
(match_operand:SCALARF 2 "register_operand")))]
""
"")
(define_insn "*mul3"
[(set (match_operand:SCALARF 0 "register_operand" "=f")
(mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
(match_operand:SCALARF 2 "register_operand" "f")))]
"!TARGET_4300_MUL_FIX"
"mul.\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "")])
;; Early VR4300 silicon has a CPU bug where multiplies with certain
;; operands may corrupt immediately following multiplies. This is a
;; simple fix to insert NOPs.
(define_insn "*mul3_r4300"
[(set (match_operand:SCALARF 0 "register_operand" "=f")
(mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
(match_operand:SCALARF 2 "register_operand" "f")))]
"TARGET_4300_MUL_FIX"
"mul.\t%0,%1,%2\;nop"
[(set_attr "type" "fmul")
(set_attr "mode" "")
(set_attr "length" "8")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=f")
(mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"mul.ps\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
;; The original R4000 has a cpu bug. If a double-word or a variable
;; shift executes while an integer multiplication is in progress, the
;; shift may give an incorrect result. Avoid this by keeping the mflo
;; with the mult on the R4000.
;;
;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
;; (also valid for MIPS R4000MC processors):
;;
;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
;; this errata description.
;; The following code sequence causes the R4000 to incorrectly
;; execute the Double Shift Right Arithmetic 32 (dsra32)
;; instruction. If the dsra32 instruction is executed during an
;; integer multiply, the dsra32 will only shift by the amount in
;; specified in the instruction rather than the amount plus 32
;; bits.
;; instruction 1: mult rs,rt integer multiply
;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
;; right arithmetic + 32
;; Workaround: A dsra32 instruction placed after an integer
;; multiply should not be one of the 11 instructions after the
;; multiply instruction."
;;
;; and:
;;
;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
;; the following description.
;; All extended shifts (shift by n+32) and variable shifts (32 and
;; 64-bit versions) may produce incorrect results under the
;; following conditions:
;; 1) An integer multiply is currently executing
;; 2) These types of shift instructions are executed immediately
;; following an integer divide instruction.
;; Workaround:
;; 1) Make sure no integer multiply is running wihen these
;; instruction are executed. If this cannot be predicted at
;; compile time, then insert a "mfhi" to R0 instruction
;; immediately after the integer multiply instruction. This
;; will cause the integer multiply to complete before the shift
;; is executed.
;; 2) Separate integer divide and these two classes of shift
;; instructions by another instruction or a noop."
;;
;; These processors have PRId values of 0x00004220 and 0x00004300,
;; respectively.
(define_expand "mul3"
[(set (match_operand:GPR 0 "register_operand")
(mult:GPR (match_operand:GPR 1 "register_operand")
(match_operand:GPR 2 "register_operand")))]
""
{
if (TARGET_LOONGSON_2EF)
emit_insn (gen_mul3_mul3_ls2ef (operands[0], operands[1],
operands[2]));
else if (ISA_HAS_MUL3)
emit_insn (gen_mul3_mul3 (operands[0], operands[1], operands[2]));
else if (TARGET_FIX_R4000)
emit_insn (gen_mul3_r4000 (operands[0], operands[1], operands[2]));
else
emit_insn
(gen_mul3_internal (operands[0], operands[1], operands[2]));
DONE;
})
(define_insn "mul3_mul3_ls2ef"
[(set (match_operand:GPR 0 "register_operand" "=d")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))]
"TARGET_LOONGSON_2EF"
"multu.g\t%0,%1,%2"
[(set_attr "type" "imul3nc")
(set_attr "mode" "")])
(define_insn "mul3_mul3"
[(set (match_operand:GPR 0 "register_operand" "=d,l")
(mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
(match_operand:GPR 2 "register_operand" "d,d")))
(clobber (match_scratch:GPR 3 "=l,X"))]
"ISA_HAS_MUL3"
{
if (which_alternative == 1)
return "mult\t%1,%2";
if (mode == SImode && TARGET_MIPS3900)
return "mult\t%0,%1,%2";
return "mul\t%0,%1,%2";
}
[(set_attr "type" "imul3,imul")
(set_attr "mode" "")])
;; If a register gets allocated to LO, and we spill to memory, the reload
;; will include a move from LO to a GPR. Merge it into the multiplication
;; if it can set the GPR directly.
;;
;; Operand 0: LO
;; Operand 1: GPR (1st multiplication operand)
;; Operand 2: GPR (2nd multiplication operand)
;; Operand 3: GPR (destination)
(define_peephole2
[(parallel
[(set (match_operand:SI 0 "lo_operand")
(mult:SI (match_operand:SI 1 "d_operand")
(match_operand:SI 2 "d_operand")))
(clobber (scratch:SI))])
(set (match_operand:SI 3 "d_operand")
(match_dup 0))]
"ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
[(parallel
[(set (match_dup 3)
(mult:SI (match_dup 1)
(match_dup 2)))
(clobber (match_dup 0))])])
(define_insn "mul3_internal"
[(set (match_operand:GPR 0 "register_operand" "=l")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))]
"!TARGET_FIX_R4000"
"mult\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "")])
(define_insn "mul3_r4000"
[(set (match_operand:GPR 0 "register_operand" "=d")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
(clobber (match_scratch:GPR 3 "=l"))]
"TARGET_FIX_R4000"
"mult\t%1,%2\;mflo\t%0"
[(set_attr "type" "imul")
(set_attr "mode" "")
(set_attr "length" "8")])
;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
;; of "mult; mflo". They have the same latency, but the first form gives
;; us an extra cycle to compute the operands.
;; Operand 0: LO
;; Operand 1: GPR (1st multiplication operand)
;; Operand 2: GPR (2nd multiplication operand)
;; Operand 3: GPR (destination)
(define_peephole2
[(set (match_operand:SI 0 "lo_operand")
(mult:SI (match_operand:SI 1 "d_operand")
(match_operand:SI 2 "d_operand")))
(set (match_operand:SI 3 "d_operand")
(match_dup 0))]
"ISA_HAS_MACC && !ISA_HAS_MUL3"
[(set (match_dup 0)
(const_int 0))
(parallel
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
(match_dup 0)))
(set (match_dup 3)
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
(match_dup 0)))])])
;; Multiply-accumulate patterns
;; This pattern is first matched by combine, which tries to use the
;; pattern wherever it can. We don't know until later whether it
;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
;; so we need to keep both options open.
;;
;; The second alternative has a "?" marker because it is generally
;; one instruction more costly than the first alternative. This "?"
;; marker is enough to convey the relative costs to the register
;; allocator.
;;
;; However, reload counts reloads of operands 4 and 5 in the same way as
;; reloads of the other operands, even though operands 4 and 5 need no
;; copy instructions. Reload therefore thinks that the second alternative
;; is two reloads more costly than the first. We add "*?*?" to the first
;; alternative as a counterweight.
(define_insn "*mul_acc_si"
[(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d"))
(match_operand:SI 3 "register_operand" "0,d")))
(clobber (match_scratch:SI 4 "=X,l"))
(clobber (match_scratch:SI 5 "=X,&d"))]
"GENERATE_MADD_MSUB && !TARGET_MIPS16"
"@
madd\t%1,%2
#"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")
(set_attr "length" "4,8")])
;; The same idea applies here. The middle alternative needs one less
;; clobber than the final alternative, so we add "*?" as a counterweight.
(define_insn "*mul_acc_si_r3900"
[(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
(match_operand:SI 2 "register_operand" "d,d,d"))
(match_operand:SI 3 "register_operand" "0,l,d")))
(clobber (match_scratch:SI 4 "=X,3,l"))
(clobber (match_scratch:SI 5 "=X,X,&d"))]
"TARGET_MIPS3900 && !TARGET_MIPS16"
"@
madd\t%1,%2
madd\t%0,%1,%2
#"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")
(set_attr "length" "4,4,8")])
;; Split *mul_acc_si if both the source and destination accumulator
;; values are GPRs.
(define_split
[(set (match_operand:SI 0 "d_operand")
(plus:SI (mult:SI (match_operand:SI 1 "d_operand")
(match_operand:SI 2 "d_operand"))
(match_operand:SI 3 "d_operand")))
(clobber (match_operand:SI 4 "lo_operand"))
(clobber (match_operand:SI 5 "d_operand"))]
"reload_completed"
[(parallel [(set (match_dup 5)
(mult:SI (match_dup 1) (match_dup 2)))
(clobber (match_dup 4))])
(set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
"")
(define_insn "*macc"
[(set (match_operand:SI 0 "register_operand" "=l,d")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d"))
(match_operand:SI 3 "register_operand" "0,l")))
(clobber (match_scratch:SI 4 "=X,3"))]
"ISA_HAS_MACC"
{
if (which_alternative == 1)
return "macc\t%0,%1,%2";
else if (TARGET_MIPS5500)
return "madd\t%1,%2";
else
/* The VR4130 assumes that there is a two-cycle latency between a macc
that "writes" to $0 and an instruction that reads from it. We avoid
this by assigning to $1 instead. */
return "%[macc\t%@,%1,%2%]";
}
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(define_insn "*msac"
[(set (match_operand:SI 0 "register_operand" "=l,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,l")
(mult:SI (match_operand:SI 2 "register_operand" "d,d")
(match_operand:SI 3 "register_operand" "d,d"))))
(clobber (match_scratch:SI 4 "=X,1"))]
"ISA_HAS_MSAC"
{
if (which_alternative == 1)
return "msac\t%0,%2,%3";
else if (TARGET_MIPS5500)
return "msub\t%2,%3";
else
return "msac\t$0,%2,%3";
}
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
;; An msac-like instruction implemented using negation and a macc.
(define_insn_and_split "*msac_using_macc"
[(set (match_operand:SI 0 "register_operand" "=l,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,l")
(mult:SI (match_operand:SI 2 "register_operand" "d,d")
(match_operand:SI 3 "register_operand" "d,d"))))
(clobber (match_scratch:SI 4 "=X,1"))
(clobber (match_scratch:SI 5 "=d,d"))]
"ISA_HAS_MACC && !ISA_HAS_MSAC"
"#"
"&& reload_completed"
[(set (match_dup 5)
(neg:SI (match_dup 3)))
(parallel
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 2)
(match_dup 5))
(match_dup 1)))
(clobber (match_dup 4))])]
""
[(set_attr "type" "imadd")
(set_attr "length" "8")])
;; Patterns generated by the define_peephole2 below.
(define_insn "*macc2"
[(set (match_operand:SI 0 "register_operand" "=l")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))
(match_dup 0)))
(set (match_operand:SI 3 "register_operand" "=d")
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
(match_dup 0)))]
"ISA_HAS_MACC && reload_completed"
"macc\t%3,%1,%2"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(define_insn "*msac2"
[(set (match_operand:SI 0 "register_operand" "=l")
(minus:SI (match_dup 0)
(mult:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))
(set (match_operand:SI 3 "register_operand" "=d")
(minus:SI (match_dup 0)
(mult:SI (match_dup 1)
(match_dup 2))))]
"ISA_HAS_MSAC && reload_completed"
"msac\t%3,%1,%2"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
;; Convert macc $0,, & mflo into macc ,,
;; Similarly msac.
;;
;; Operand 0: LO
;; Operand 1: macc/msac
;; Operand 2: GPR (destination)
(define_peephole2
[(parallel
[(set (match_operand:SI 0 "lo_operand")
(match_operand:SI 1 "macc_msac_operand"))
(clobber (scratch:SI))])
(set (match_operand:SI 2 "d_operand")
(match_dup 0))]
""
[(parallel [(set (match_dup 0)
(match_dup 1))
(set (match_dup 2)
(match_dup 1))])])
;; When we have a three-address multiplication instruction, it should
;; be faster to do a separate multiply and add, rather than moving
;; something into LO in order to use a macc instruction.
;;
;; This peephole needs a scratch register to cater for the case when one
;; of the multiplication operands is the same as the destination.
;;
;; Operand 0: GPR (scratch)
;; Operand 1: LO
;; Operand 2: GPR (addend)
;; Operand 3: GPR (destination)
;; Operand 4: macc/msac
;; Operand 5: new multiplication
;; Operand 6: new addition/subtraction
(define_peephole2
[(match_scratch:SI 0 "d")
(set (match_operand:SI 1 "lo_operand")
(match_operand:SI 2 "d_operand"))
(match_dup 0)
(parallel
[(set (match_operand:SI 3 "d_operand")
(match_operand:SI 4 "macc_msac_operand"))
(clobber (match_dup 1))])]
"ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
[(parallel [(set (match_dup 0)
(match_dup 5))
(clobber (match_dup 1))])
(set (match_dup 3)
(match_dup 6))]
{
operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
operands[2], operands[0]);
})
;; Same as above, except LO is the initial target of the macc.
;;
;; Operand 0: GPR (scratch)
;; Operand 1: LO
;; Operand 2: GPR (addend)
;; Operand 3: macc/msac
;; Operand 4: GPR (destination)
;; Operand 5: new multiplication
;; Operand 6: new addition/subtraction
(define_peephole2
[(match_scratch:SI 0 "d")
(set (match_operand:SI 1 "lo_operand")
(match_operand:SI 2 "d_operand"))
(match_dup 0)
(parallel
[(set (match_dup 1)
(match_operand:SI 3 "macc_msac_operand"))
(clobber (scratch:SI))])
(match_dup 0)
(set (match_operand:SI 4 "d_operand")
(match_dup 1))]
"ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
[(parallel [(set (match_dup 0)
(match_dup 5))
(clobber (match_dup 1))])
(set (match_dup 4)
(match_dup 6))]
{
operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
operands[2], operands[0]);
})
;; See the comment above *mul_add_si for details.
(define_insn "*mul_sub_si"
[(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
(minus:SI (match_operand:SI 1 "register_operand" "0,d")
(mult:SI (match_operand:SI 2 "register_operand" "d,d")
(match_operand:SI 3 "register_operand" "d,d"))))
(clobber (match_scratch:SI 4 "=X,l"))
(clobber (match_scratch:SI 5 "=X,&d"))]
"GENERATE_MADD_MSUB"
"@
msub\t%2,%3
#"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")
(set_attr "length" "4,8")])
;; Split *mul_sub_si if both the source and destination accumulator
;; values are GPRs.
(define_split
[(set (match_operand:SI 0 "d_operand")
(minus:SI (match_operand:SI 1 "d_operand")
(mult:SI (match_operand:SI 2 "d_operand")
(match_operand:SI 3 "d_operand"))))
(clobber (match_operand:SI 4 "lo_operand"))
(clobber (match_operand:SI 5 "d_operand"))]
"reload_completed"
[(parallel [(set (match_dup 5)
(mult:SI (match_dup 2) (match_dup 3)))
(clobber (match_dup 4))])
(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
"")
(define_insn "*muls"
[(set (match_operand:SI 0 "register_operand" "=l,d")
(neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d"))))
(clobber (match_scratch:SI 3 "=X,l"))]
"ISA_HAS_MULS"
"@
muls\t$0,%1,%2
muls\t%0,%1,%2"
[(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
(define_expand "mulsidi3"
[(set (match_operand:DI 0 "register_operand")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
(any_extend:DI (match_operand:SI 2 "register_operand"))))]
"!TARGET_64BIT || !TARGET_FIX_R4000"
{
if (TARGET_64BIT)
emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2]));
else if (TARGET_FIX_R4000)
emit_insn (gen_mulsidi3_32bit_r4000 (operands[0], operands[1],
operands[2]));
else
emit_insn (gen_mulsidi3_32bit (operands[0], operands[1], operands[2]));
DONE;
})
(define_insn "mulsidi3_32bit"
[(set (match_operand:DI 0 "register_operand" "=x")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
"!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
"mult\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(define_insn "mulsidi3_32bit_r4000"
[(set (match_operand:DI 0 "register_operand" "=d")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(clobber (match_scratch:DI 3 "=x"))]
"!TARGET_64BIT && TARGET_FIX_R4000"
"mult\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
[(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "12")])
(define_insn_and_split "mulsidi3_64bit"
[(set (match_operand:DI 0 "register_operand" "=d")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(clobber (match_scratch:TI 3 "=x"))
(clobber (match_scratch:DI 4 "=d"))]
"TARGET_64BIT && !TARGET_FIX_R4000"
"#"
"&& reload_completed"
[(set (match_dup 3)
(unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
(any_extend:DI (match_dup 2)))]
UNSPEC_SET_HILO))
;; OP4 <- LO, OP0 <- HI
(set (match_dup 4) (match_dup 5))
(set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
;; Zero-extend OP4.
(set (match_dup 4)
(ashift:DI (match_dup 4)
(const_int 32)))
(set (match_dup 4)
(lshiftrt:DI (match_dup 4)
(const_int 32)))
;; Shift OP0 into place.
(set (match_dup 0)
(ashift:DI (match_dup 0)
(const_int 32)))
;; OR the two halves together
(set (match_dup 0)
(ior:DI (match_dup 0)
(match_dup 4)))]
{ operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
[(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "24")])
(define_insn "mulsidi3_64bit_hilo"
[(set (match_operand:TI 0 "register_operand" "=x")
(unspec:TI
[(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
UNSPEC_SET_HILO))]
"TARGET_64BIT && !TARGET_FIX_R4000"
"mult\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
;; Widening multiply with negation.
(define_insn "*muls_di"
[(set (match_operand:DI 0 "register_operand" "=x")
(neg:DI
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
"!TARGET_64BIT && ISA_HAS_MULS"
"muls\t$0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(define_insn "msubsidi4"
[(set (match_operand:DI 0 "register_operand" "=ka")
(minus:DI
(match_operand:DI 3 "register_operand" "0")
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
"!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
{
if (ISA_HAS_DSPR2)
return "msub\t%q0,%1,%2";
else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
return "msub\t%1,%2";
else
return "msac\t$0,%1,%2";
}
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
;; _highpart patterns
(define_expand "mulsi3_highpart"
[(set (match_operand:SI 0 "register_operand")
(truncate:SI
(lshiftrt:DI
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
(any_extend:DI (match_operand:SI 2 "register_operand")))
(const_int 32))))]
""
{
if (ISA_HAS_MULHI)
emit_insn (gen_mulsi3_highpart_mulhi_internal (operands[0],
operands[1],
operands[2]));
else
emit_insn (gen_mulsi3_highpart_internal (operands[0], operands[1],
operands[2]));
DONE;
})
(define_insn_and_split "mulsi3_highpart_internal"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=l"))]
"!ISA_HAS_MULHI"
{ return TARGET_FIX_R4000 ? "mult\t%1,%2\n\tmfhi\t%0" : "#"; }
"&& reload_completed && !TARGET_FIX_R4000"
[(const_int 0)]
{
rtx hilo;
if (TARGET_64BIT)
{
hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
emit_insn (gen_mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
emit_insn (gen_mfhisi_ti (operands[0], hilo));
}
else
{
hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
emit_insn (gen_mulsidi3_32bit (hilo, operands[1], operands[2]));
emit_insn (gen_mfhisi_di (operands[0], hilo));
}
DONE;
}
[(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "8")])
(define_insn "mulsi3_highpart_mulhi_internal"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=l"))]
"ISA_HAS_MULHI"
"mulhi\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(define_insn "*mulsi3_highpart_neg_mulhi_internal"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
(neg:DI
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(const_int 32))))
(clobber (match_scratch:SI 3 "=l"))]
"ISA_HAS_MULHI"
"mulshi\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
;; errata MD(0), which says that dmultu does not always produce the
;; correct result.
(define_insn_and_split "muldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=d")
(truncate:DI
(lshiftrt:TI
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
(any_extend:TI (match_operand:DI 2 "register_operand" "d")))
(const_int 64))))
(clobber (match_scratch:DI 3 "=l"))]
"TARGET_64BIT && !( == ZERO_EXTEND && TARGET_FIX_VR4120)"
{ return TARGET_FIX_R4000 ? "dmult\t%1,%2\n\tmfhi\t%0" : "#"; }
"&& reload_completed && !TARGET_FIX_R4000"
[(const_int 0)]
{
rtx hilo;
hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
emit_insn (gen_mulditi3_internal (hilo, operands[1], operands[2]));
emit_insn (gen_mfhidi_ti (operands[0], hilo));
DONE;
}
[(set_attr "type" "imul")
(set_attr "mode" "DI")
(set_attr "length" "8")])
(define_expand "mulditi3"
[(set (match_operand:TI 0 "register_operand")
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
(any_extend:TI (match_operand:DI 2 "register_operand"))))]
"TARGET_64BIT && !( == ZERO_EXTEND && TARGET_FIX_VR4120)"
{
if (TARGET_FIX_R4000)
emit_insn (gen_mulditi3_r4000 (operands[0], operands[1], operands[2]));
else
emit_insn (gen_mulditi3_internal (operands[0], operands[1],
operands[2]));
DONE;
})
(define_insn "mulditi3_internal"
[(set (match_operand:TI 0 "register_operand" "=x")
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
(any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
"TARGET_64BIT
&& !TARGET_FIX_R4000
&& !( == ZERO_EXTEND && TARGET_FIX_VR4120)"
"dmult\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
(define_insn "mulditi3_r4000"
[(set (match_operand:TI 0 "register_operand" "=d")
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
(any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
(clobber (match_scratch:TI 3 "=x"))]
"TARGET_64BIT
&& TARGET_FIX_R4000
&& !( == ZERO_EXTEND && TARGET_FIX_VR4120)"
"dmult\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
[(set_attr "type" "imul")
(set_attr "mode" "DI")
(set_attr "length" "12")])
;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
;; instruction. The HI/LO registers are used as a 64-bit accumulator.
(define_insn "madsi"
[(set (match_operand:SI 0 "register_operand" "+l")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))
(match_dup 0)))]
"TARGET_MAD"
"mad\t%1,%2"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(define_insn "maddsidi4"
[(set (match_operand:DI 0 "register_operand" "=ka")
(plus:DI
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(match_operand:DI 3 "register_operand" "0")))]
"(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
&& !TARGET_64BIT"
{
if (TARGET_MAD)
return "mad\t%1,%2";
else if (ISA_HAS_DSPR2)
return "madd\t%q0,%1,%2";
else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
return "madd\t%1,%2";
else
/* See comment in *macc. */
return "%[macc\t%@,%1,%2%]";
}
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
;; Floating point multiply accumulate instructions.
(define_insn "*madd4"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
"ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
"madd.\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*madd3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "0")))]
"ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
"madd.\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*msub4"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
"ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
"msub.\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*msub3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "0")))]
"ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
"msub.\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*nmadd4"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (plus:ANYF
(mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f"))))]
"ISA_HAS_NMADD4_NMSUB4 (mode)
&& TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (mode)
&& !HONOR_NANS (mode)"
"nmadd.\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*nmadd3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (plus:ANYF
(mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "0"))))]
"ISA_HAS_NMADD3_NMSUB3 (mode)
&& TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (mode)
&& !HONOR_NANS (mode)"
"nmadd.\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*nmadd4_fastmath"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF
(mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
"ISA_HAS_NMADD4_NMSUB4 (mode)
&& TARGET_FUSED_MADD
&& !HONOR_SIGNED_ZEROS (mode)
&& !HONOR_NANS (mode)"
"nmadd.\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*nmadd3_fastmath"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF
(mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "0")))]
"ISA_HAS_NMADD3_NMSUB3 (mode)
&& TARGET_FUSED_MADD
&& !HONOR_SIGNED_ZEROS (mode)
&& !HONOR_NANS (mode)"
"nmadd.\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*nmsub4"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (minus:ANYF
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))
(match_operand:ANYF 1 "register_operand" "f"))))]
"ISA_HAS_NMADD4_NMSUB4 (mode)
&& TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (mode)
&& !HONOR_NANS (mode)"
"nmsub.\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*nmsub3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (minus:ANYF
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))
(match_operand:ANYF 1 "register_operand" "0"))))]
"ISA_HAS_NMADD3_NMSUB3 (mode)
&& TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (mode)
&& !HONOR_NANS (mode)"
"nmsub.\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*nmsub4_fastmath"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF
(match_operand:ANYF 1 "register_operand" "f")
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))))]
"ISA_HAS_NMADD4_NMSUB4 (mode)
&& TARGET_FUSED_MADD
&& !HONOR_SIGNED_ZEROS (mode)
&& !HONOR_NANS (mode)"
"nmsub.\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
(define_insn "*nmsub3_fastmath"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF
(match_operand:ANYF 1 "register_operand" "f")
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "0"))))]
"ISA_HAS_NMADD3_NMSUB3 (mode)
&& TARGET_FUSED_MADD
&& !HONOR_SIGNED_ZEROS (mode)
&& !HONOR_NANS (mode)"
"nmsub.\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "")])
;;
;; ....................
;;
;; DIVISION and REMAINDER
;;
;; ....................
;;
(define_expand "div3"
[(set (match_operand:ANYF 0 "register_operand")
(div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
(match_operand:ANYF 2 "register_operand")))]
""
{
if (const_1_operand (operands[1], mode))
if (!( && flag_unsafe_math_optimizations))
operands[1] = force_reg (mode, operands[1]);
})
;; These patterns work around the early SB-1 rev2 core "F1" erratum:
;;
;; If an mfc1 or dmfc1 happens to access the floating point register
;; file at the same time a long latency operation (div, sqrt, recip,
;; sqrt) iterates an intermediate result back through the floating
;; point register file bypass, then instead returning the correct
;; register value the mfc1 or dmfc1 operation returns the intermediate
;; result of the long latency operation.
;;
;; The workaround is to insert an unconditional 'mov' from/to the
;; long latency op destination register.
(define_insn "*div3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
""
{
if (TARGET_FIX_SB1)
return "div.\t%0,%1,%2\;mov.\t%0,%0";
else
return "div.\t%0,%1,%2";
}
[(set_attr "type" "fdiv")
(set_attr "mode" "")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
(define_insn "*recip3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
(match_operand:ANYF 2 "register_operand" "f")))]
" && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
return "recip.\t%0,%2\;mov.\t%0,%0";
else
return "recip.\t%0,%2";
}
[(set_attr "type" "frdiv")
(set_attr "mode" "")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
;; VR4120 errata MD(A1): signed division instructions do not work correctly
;; with negative operands. We use special libgcc functions instead.
(define_insn_and_split "divmod4"
[(set (match_operand:GPR 0 "register_operand" "=l")
(div:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
(set (match_operand:GPR 3 "register_operand" "=d")
(mod:GPR (match_dup 1)
(match_dup 2)))]
"!TARGET_FIX_VR4120"
"#"
"&& reload_completed"
[(const_int 0)]
{
rtx hilo;
if (TARGET_64BIT)
{
hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
emit_insn (gen_divmod4_hilo_ti (hilo, operands[1], operands[2]));
emit_insn (gen_mfhi_ti (operands[3], hilo));
}
else
{
hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
emit_insn (gen_divmod4_hilo_di (hilo, operands[1], operands[2]));
emit_insn (gen_mfhi_di (operands[3], hilo));
}
DONE;
}
[(set_attr "type" "idiv")
(set_attr "mode" "")
(set_attr "length" "8")])
(define_insn_and_split "udivmod4"
[(set (match_operand:GPR 0 "register_operand" "=l")
(udiv:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
(set (match_operand:GPR 3 "register_operand" "=d")
(umod:GPR (match_dup 1)
(match_dup 2)))]
""
"#"
"reload_completed"
[(const_int 0)]
{
rtx hilo;
if (TARGET_64BIT)
{
hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
emit_insn (gen_udivmod4_hilo_ti (hilo, operands[1], operands[2]));
emit_insn (gen_mfhi_ti (operands[3], hilo));
}
else
{
hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
emit_insn (gen_udivmod4_hilo_di (hilo, operands[1], operands[2]));
emit_insn (gen_mfhi_di (operands[3], hilo));
}
DONE;
}
[(set_attr "type" "idiv")
(set_attr "mode" "")
(set_attr "length" "8")])
(define_insn "divmod4_hilo_"
[(set (match_operand:HILO 0 "register_operand" "=x")
(unspec:HILO
[(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d"))]
UNSPEC_SET_HILO))]
""
{ return mips_output_division ("div\t%.,%1,%2", operands); }
[(set_attr "type" "idiv")
(set_attr "mode" "")])
;;
;; ....................
;;
;; SQUARE ROOT
;;
;; ....................
;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
;; "*div[sd]f3" comment for details).
(define_insn "sqrt2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
""
{
if (TARGET_FIX_SB1)
return "sqrt.\t%0,%1\;mov.\t%0,%0";
else
return "sqrt.\t%0,%1";
}
[(set_attr "type" "fsqrt")
(set_attr "mode" "")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
(define_insn "*rsqrta"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
(sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
" && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
return "rsqrt.\t%0,%2\;mov.\t%0,%0";
else
return "rsqrt.\t%0,%2";
}
[(set_attr "type" "frsqrt")
(set_attr "mode" "")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
(define_insn "*rsqrtb"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
(match_operand:ANYF 2 "register_operand" "f"))))]
" && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
return "rsqrt.\t%0,%2\;mov.\t%0,%0";
else
return "rsqrt.\t%0,%2";
}
[(set_attr "type" "frsqrt")
(set_attr "mode" "")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
;;
;; ....................
;;
;; ABSOLUTE VALUE
;;
;; ....................
;; Do not use the integer abs macro instruction, since that signals an
;; exception on -2147483648 (sigh).
;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
;; invalid; it does not clear their sign bits. We therefore can't use
;; abs.fmt if the signs of NaNs matter.
(define_insn "abs2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
"!HONOR_NANS (mode)"
"abs.\t%0,%1"
[(set_attr "type" "fabs")
(set_attr "mode" "")])
;;
;; ...................
;;
;; Count leading zeroes.
;;
;; ...................
;;
(define_insn "clz2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
"ISA_HAS_CLZ_CLO"
"clz\t%0,%1"
[(set_attr "type" "clz")
(set_attr "mode" "")])
;;
;; ...................
;;
;; Count number of set bits.
;;
;; ...................
;;
(define_insn "popcount2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
"ISA_HAS_POP"
"pop\t%0,%1"
[(set_attr "type" "pop")
(set_attr "mode" "")])
;;
;; ....................
;;
;; NEGATION and ONE'S COMPLEMENT
;;
;; ....................
(define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(neg:SI (match_operand:SI 1 "register_operand" "d")))]
""
{
if (TARGET_MIPS16)
return "neg\t%0,%1";
else
return "subu\t%0,%.,%1";
}
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(define_insn "negdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && !TARGET_MIPS16"
"dsubu\t%0,%.,%1"
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
;; invalid; it does not flip their sign bit. We therefore can't use
;; neg.fmt if the signs of NaNs matter.
(define_insn "neg2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
"!HONOR_NANS (mode)"
"neg.\t%0,%1"
[(set_attr "type" "fneg")
(set_attr "mode" "")])
(define_insn "one_cmpl2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(not:GPR (match_operand:GPR 1 "register_operand" "d")))]
""
{
if (TARGET_MIPS16)
return "not\t%0,%1";
else
return "nor\t%0,%.,%1";
}
[(set_attr "type" "logical")
(set_attr "mode" "")])
;;
;; ....................
;;
;; LOGICAL
;;
;; ....................
;;
;; Many of these instructions use trivial define_expands, because we
;; want to use a different set of constraints when TARGET_MIPS16.
(define_expand "and3"
[(set (match_operand:GPR 0 "register_operand")
(and:GPR (match_operand:GPR 1 "register_operand")
(match_operand:GPR 2 "uns_arith_operand")))]
""
{
if (TARGET_MIPS16)
operands[2] = force_reg (mode, operands[2]);
})
(define_insn "*and3"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
(match_operand:GPR 2 "uns_arith_operand" "d,K")))]
"!TARGET_MIPS16"
"@
and\t%0,%1,%2
andi\t%0,%1,%x2"
[(set_attr "type" "logical")
(set_attr "mode" "")])
(define_insn "*and3_mips16"
[(set (match_operand:GPR 0 "register_operand" "=d")
(and:GPR (match_operand:GPR 1 "register_operand" "%0")
(match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
"and\t%0,%2"
[(set_attr "type" "logical")
(set_attr "mode" "")])
(define_expand "ior3"
[(set (match_operand:GPR 0 "register_operand")
(ior:GPR (match_operand:GPR 1 "register_operand")
(match_operand:GPR 2 "uns_arith_operand")))]
""
{
if (TARGET_MIPS16)
operands[2] = force_reg (mode, operands[2]);
})
(define_insn "*ior3"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
(match_operand:GPR 2 "uns_arith_operand" "d,K")))]
"!TARGET_MIPS16"
"@
or\t%0,%1,%2
ori\t%0,%1,%x2"
[(set_attr "type" "logical")
(set_attr "mode" "")])
(define_insn "*ior