annotate gcc/config/h8300/shiftrotate.md @ 19:2b5abeee2509 default tip

update gcc11
author anatofuz
date Mon, 25 May 2020 07:50:57 +0900
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1 ;; ----------------------------------------------------------------------
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2 ;; SHIFTS
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3 ;; ----------------------------------------------------------------------
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4 ;;
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5 ;; We make some attempt to provide real efficient shifting. One example is
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6 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
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7 ;; reg and moving 0 into the former reg.
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8 ;;
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9 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
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10 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
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11 ;; give the optimizer more cracks at the code. However, we wish to do things
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12 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
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13 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
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14 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
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15 ;; to detect cases it can optimize.
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16 ;;
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17 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
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18 ;; easier "do it at insn emit time" route.
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19
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20
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21 (define_expand "ashl<mode>3"
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22 [(set (match_operand:QHSI 0 "register_operand" "")
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23 (ashift:QHSI (match_operand:QHSI 1 "register_operand" "")
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24 (match_operand:QI 2 "nonmemory_operand" "")))]
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25 ""
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26 {
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27 if (expand_a_shift (<MODE>mode, ASHIFT, operands))
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28 DONE;
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29 })
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30
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31 (define_expand "ashr<mode>3"
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32 [(set (match_operand:QHSI 0 "register_operand" "")
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33 (ashiftrt:QHSI (match_operand:QHSI 1 "register_operand" "")
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34 (match_operand:QI 2 "nonmemory_operand" "")))]
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35 ""
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36 {
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37 if (expand_a_shift (<MODE>mode, ASHIFTRT, operands))
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38 DONE;
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39 })
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40
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41 (define_expand "lshr<mode>3"
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42 [(set (match_operand:QHSI 0 "register_operand" "")
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43 (lshiftrt:QHSI (match_operand:QHSI 1 "register_operand" "")
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44 (match_operand:QI 2 "nonmemory_operand" "")))]
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45 ""
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46 {
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47 if (expand_a_shift (<MODE>mode, LSHIFTRT, operands))
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48 DONE;
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49 })
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50
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51 ;; QI/HI/SI BIT SHIFTS
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52
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53 (define_insn ""
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54 [(set (match_operand:QHSI 0 "h8300_dst_operand" "=rQ")
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55 (match_operator:QHSI 3 "h8sx_unary_shift_operator"
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56 [(match_operand:QHSI 1 "h8300_dst_operand" "0")
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57 (match_operand:QI 2 "const_int_operand" "")]))]
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58 "h8300_operands_match_p (operands)"
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59 {
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60 if (<MODE>mode == E_QImode)
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61 return output_h8sx_shift (operands, 'b', 'X');
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62 if (<MODE>mode == E_HImode)
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63 return output_h8sx_shift (operands, 'w', 'T');
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64 if (<MODE>mode == E_SImode)
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65 return output_h8sx_shift (operands, 'l', 'S');
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66 gcc_unreachable ();
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67 }
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68 [(set_attr "length_table" "unary")
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69 (set_attr "cc" "set_znv")])
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70
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71 (define_insn ""
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72 [(set (match_operand:QHSI 0 "register_operand" "=r")
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73 (match_operator:QHSI 3 "h8sx_binary_shift_operator"
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74 [(match_operand:QHSI 1 "register_operand" "0")
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75 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
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76 ""
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77 {
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78 if (<MODE>mode == QImode)
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79 return output_h8sx_shift (operands, 'b', 'X');
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80 if (<MODE>mode == HImode)
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81 return output_h8sx_shift (operands, 'w', 'T');
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82 if (<MODE>mode == SImode)
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83 return output_h8sx_shift (operands, 'l', 'S');
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84 gcc_unreachable ();
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85 }
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86 [(set_attr "length" "4")
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87 (set_attr "cc" "set_znv")])
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88
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89 (define_insn "*shiftqi"
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90 [(set (match_operand:QI 0 "register_operand" "=r,r")
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91 (match_operator:QI 3 "nshift_operator"
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92 [(match_operand:QI 1 "register_operand" "0,0")
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93 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
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94 (clobber (match_scratch:QI 4 "=X,&r"))]
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95 ""
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96 {
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97 return output_a_shift (operands);
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98 }
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99 [(set (attr "length")
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100 (symbol_ref "compute_a_shift_length (insn, operands)"))
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101 (set (attr "cc")
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102 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
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103
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104 (define_insn "*shifthi"
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105 [(set (match_operand:HI 0 "register_operand" "=r,r")
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106 (match_operator:HI 3 "nshift_operator"
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107 [(match_operand:HI 1 "register_operand" "0,0")
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108 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
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109 (clobber (match_scratch:QI 4 "=X,&r"))]
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110 ""
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111 {
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112 return output_a_shift (operands);
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113 }
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114 [(set (attr "length")
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115 (symbol_ref "compute_a_shift_length (insn, operands)"))
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116 (set (attr "cc")
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117 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
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118
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119 (define_insn "*shiftsi"
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120 [(set (match_operand:SI 0 "register_operand" "=r,r")
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121 (match_operator:SI 3 "nshift_operator"
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122 [(match_operand:SI 1 "register_operand" "0,0")
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123 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
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124 (clobber (match_scratch:QI 4 "=X,&r"))]
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125 ""
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126 {
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127 return output_a_shift (operands);
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128 }
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129 [(set (attr "length")
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130 (symbol_ref "compute_a_shift_length (insn, operands)"))
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131 (set (attr "cc")
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132 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
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133
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134
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135 ;; Split a variable shift into a loop. If the register containing
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136 ;; the shift count dies, then we just use that register.
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137
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138 (define_split
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139 [(set (match_operand 0 "register_operand" "")
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140 (match_operator 2 "nshift_operator"
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141 [(match_dup 0)
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142 (match_operand:QI 1 "register_operand" "")]))
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143 (clobber (match_operand:QI 3 "register_operand" ""))]
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144 "epilogue_completed
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145 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
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146 [(set (cc0) (compare (match_dup 1) (const_int 0)))
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147 (set (pc)
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148 (if_then_else (le (cc0) (const_int 0))
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149 (label_ref (match_dup 5))
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150 (pc)))
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151 (match_dup 4)
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152 (parallel
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153 [(set (match_dup 0)
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154 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
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155 (clobber (scratch:QI))])
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156 (set (match_dup 1) (plus:QI (match_dup 1) (const_int -1)))
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157 (set (cc0) (compare (match_dup 1) (const_int 0)))
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158 (set (pc)
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159 (if_then_else (ne (cc0) (const_int 0))
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160 (label_ref (match_dup 4))
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161 (pc)))
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162 (match_dup 5)]
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163 {
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164 operands[4] = gen_label_rtx ();
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165 operands[5] = gen_label_rtx ();
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166 })
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167
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168 (define_split
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169 [(set (match_operand 0 "register_operand" "")
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170 (match_operator 2 "nshift_operator"
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171 [(match_dup 0)
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172 (match_operand:QI 1 "register_operand" "")]))
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173 (clobber (match_operand:QI 3 "register_operand" ""))]
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174 "epilogue_completed
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175 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
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176 [(set (match_dup 3)
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177 (match_dup 1))
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178 (set (cc0) (compare (match_dup 3) (const_int 0)))
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179 (set (pc)
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180 (if_then_else (le (cc0) (const_int 0))
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181 (label_ref (match_dup 5))
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182 (pc)))
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183 (match_dup 4)
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184 (parallel
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185 [(set (match_dup 0)
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186 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
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187 (clobber (scratch:QI))])
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188 (set (match_dup 3) (plus:QI (match_dup 3) (const_int -1)))
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189 (set (cc0) (compare (match_dup 3) (const_int 0)))
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190 (set (pc)
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191 (if_then_else (ne (cc0) (const_int 0))
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192 (label_ref (match_dup 4))
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193 (pc)))
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194 (match_dup 5)]
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195 {
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196 operands[4] = gen_label_rtx ();
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197 operands[5] = gen_label_rtx ();
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198 })
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199
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200 ;; ----------------------------------------------------------------------
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201 ;; ROTATIONS
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202 ;; ----------------------------------------------------------------------
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203
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204 (define_expand "rotl<mode>3"
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205 [(set (match_operand:QHSI 0 "register_operand" "")
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206 (rotate:QHSI (match_operand:QHSI 1 "register_operand" "")
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207 (match_operand:QI 2 "nonmemory_operand" "")))]
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208 ""
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209 {
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210 if (expand_a_rotate (operands))
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211 DONE;
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212 })
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213
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214 (define_insn "rotl<mode>3_1"
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215 [(set (match_operand:QHSI 0 "register_operand" "=r")
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216 (rotate:QHSI (match_operand:QHSI 1 "register_operand" "0")
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217 (match_operand:QI 2 "immediate_operand" "")))]
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218 ""
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219 {
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220 return output_a_rotate (ROTATE, operands);
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221 }
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222 [(set (attr "length")
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223 (symbol_ref "compute_a_rotate_length (operands)"))])