comparison gcc/recog.c @ 16:04ced10e8804

gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
comparison
equal deleted inserted replaced
15:561a7518be6b 16:04ced10e8804
1 /* Subroutines used by or related to instruction recognition. 1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 3
6 This file is part of GCC. 4 This file is part of GCC.
7 5
8 GCC is free software; you can redistribute it and/or modify it under 6 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free 7 the terms of the GNU General Public License as published by the Free
21 19
22 20
23 #include "config.h" 21 #include "config.h"
24 #include "system.h" 22 #include "system.h"
25 #include "coretypes.h" 23 #include "coretypes.h"
26 #include "tm.h" 24 #include "backend.h"
27 #include "rtl-error.h" 25 #include "target.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "cfghooks.h"
29 #include "df.h"
30 #include "memmodel.h"
28 #include "tm_p.h" 31 #include "tm_p.h"
29 #include "insn-config.h" 32 #include "insn-config.h"
33 #include "regs.h"
34 #include "emit-rtl.h"
35 #include "recog.h"
30 #include "insn-attr.h" 36 #include "insn-attr.h"
31 #include "hard-reg-set.h"
32 #include "recog.h"
33 #include "regs.h"
34 #include "addresses.h" 37 #include "addresses.h"
35 #include "expr.h" 38 #include "cfgrtl.h"
36 #include "function.h" 39 #include "cfgbuild.h"
37 #include "flags.h" 40 #include "cfgcleanup.h"
38 #include "basic-block.h"
39 #include "output.h"
40 #include "reload.h" 41 #include "reload.h"
41 #include "target.h"
42 #include "timevar.h"
43 #include "tree-pass.h" 42 #include "tree-pass.h"
44 #include "df.h"
45
46 #ifndef STACK_PUSH_CODE
47 #ifdef STACK_GROWS_DOWNWARD
48 #define STACK_PUSH_CODE PRE_DEC
49 #else
50 #define STACK_PUSH_CODE PRE_INC
51 #endif
52 #endif
53 43
54 #ifndef STACK_POP_CODE 44 #ifndef STACK_POP_CODE
55 #ifdef STACK_GROWS_DOWNWARD 45 #if STACK_GROWS_DOWNWARD
56 #define STACK_POP_CODE POST_INC 46 #define STACK_POP_CODE POST_INC
57 #else 47 #else
58 #define STACK_POP_CODE POST_DEC 48 #define STACK_POP_CODE POST_DEC
59 #endif 49 #endif
60 #endif 50 #endif
61 51
62 #ifndef HAVE_ATTR_enabled 52 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool);
63 static inline bool 53 static void validate_replace_src_1 (rtx *, void *);
64 get_attr_enabled (rtx insn ATTRIBUTE_UNUSED) 54 static rtx_insn *split_insn (rtx_insn *);
65 { 55
66 return true; 56 struct target_recog default_target_recog;
67 } 57 #if SWITCHABLE_TARGET
58 struct target_recog *this_target_recog = &default_target_recog;
68 #endif 59 #endif
69
70 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx, bool);
71 static void validate_replace_src_1 (rtx *, void *);
72 static rtx split_insn (rtx);
73 60
74 /* Nonzero means allow operands to be volatile. 61 /* Nonzero means allow operands to be volatile.
75 This should be 0 if you are generating rtl, such as if you are calling 62 This should be 0 if you are generating rtl, such as if you are calling
76 the functions in optabs.c and expmed.c (most of the time). 63 the functions in optabs.c and expmed.c (most of the time).
77 This should be 1 if all valid insns need to be recognized, 64 This should be 1 if all valid insns need to be recognized,
79 66
80 init_recog and init_recog_no_volatile are responsible for setting this. */ 67 init_recog and init_recog_no_volatile are responsible for setting this. */
81 68
82 int volatile_ok; 69 int volatile_ok;
83 70
84 struct recog_data recog_data; 71 struct recog_data_d recog_data;
85 72
86 /* Contains a vector of operand_alternative structures for every operand. 73 /* Contains a vector of operand_alternative structures, such that
74 operand OP of alternative A is at index A * n_operands + OP.
87 Set up by preprocess_constraints. */ 75 Set up by preprocess_constraints. */
88 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES]; 76 const operand_alternative *recog_op_alt;
77
78 /* Used to provide recog_op_alt for asms. */
79 static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS
80 * MAX_RECOG_ALTERNATIVES];
89 81
90 /* On return from `constrain_operands', indicate which alternative 82 /* On return from `constrain_operands', indicate which alternative
91 was satisfied. */ 83 was satisfied. */
92 84
93 int which_alternative; 85 int which_alternative;
116 { 108 {
117 volatile_ok = 1; 109 volatile_ok = 1;
118 } 110 }
119 111
120 112
113 /* Return true if labels in asm operands BODY are LABEL_REFs. */
114
115 static bool
116 asm_labels_ok (rtx body)
117 {
118 rtx asmop;
119 int i;
120
121 asmop = extract_asm_operands (body);
122 if (asmop == NULL_RTX)
123 return true;
124
125 for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
126 if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
127 return false;
128
129 return true;
130 }
131
121 /* Check that X is an insn-body for an `asm' with operands 132 /* Check that X is an insn-body for an `asm' with operands
122 and that the operands mentioned in it are legitimate. */ 133 and that the operands mentioned in it are legitimate. */
123 134
124 int 135 int
125 check_asm_operands (rtx x) 136 check_asm_operands (rtx x)
127 int noperands; 138 int noperands;
128 rtx *operands; 139 rtx *operands;
129 const char **constraints; 140 const char **constraints;
130 int i; 141 int i;
131 142
143 if (!asm_labels_ok (x))
144 return 0;
145
132 /* Post-reload, be more strict with things. */ 146 /* Post-reload, be more strict with things. */
133 if (reload_completed) 147 if (reload_completed)
134 { 148 {
135 /* ??? Doh! We've not got the wrapping insn. Cook one up. */ 149 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
136 extract_insn (make_insn_raw (x)); 150 rtx_insn *insn = make_insn_raw (x);
137 constrain_operands (1); 151 extract_insn (insn);
152 constrain_operands (1, get_enabled_alternatives (insn));
138 return which_alternative >= 0; 153 return which_alternative >= 0;
139 } 154 }
140 155
141 noperands = asm_noperands (x); 156 noperands = asm_noperands (x);
142 if (noperands < 0) 157 if (noperands < 0)
161 return 1; 176 return 1;
162 } 177 }
163 178
164 /* Static data for the next two routines. */ 179 /* Static data for the next two routines. */
165 180
166 typedef struct change_t 181 struct change_t
167 { 182 {
168 rtx object; 183 rtx object;
169 int old_code; 184 int old_code;
185 bool unshare;
170 rtx *loc; 186 rtx *loc;
171 rtx old; 187 rtx old;
172 bool unshare; 188 };
173 } change_t;
174 189
175 static change_t *changes; 190 static change_t *changes;
176 static int changes_allocated; 191 static int changes_allocated;
177 192
178 static int num_changes = 0; 193 static int num_changes = 0;
267 modifies the operands of X, not (for example) its code. Simplifications 282 modifies the operands of X, not (for example) its code. Simplifications
268 are not the job of this routine. 283 are not the job of this routine.
269 284
270 Return true if anything was changed. */ 285 Return true if anything was changed. */
271 bool 286 bool
272 canonicalize_change_group (rtx insn, rtx x) 287 canonicalize_change_group (rtx_insn *insn, rtx x)
273 { 288 {
274 if (COMMUTATIVE_P (x) 289 if (COMMUTATIVE_P (x)
275 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 290 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
276 { 291 {
277 /* Oops, the caller has made X no longer canonical. 292 /* Oops, the caller has made X no longer canonical.
278 Let's redo the changes in the correct order. */ 293 Let's redo the changes in the correct order. */
279 rtx tem = XEXP (x, 0); 294 rtx tem = XEXP (x, 0);
280 validate_change (insn, &XEXP (x, 0), XEXP (x, 1), 1); 295 validate_unshare_change (insn, &XEXP (x, 0), XEXP (x, 1), 1);
281 validate_change (insn, &XEXP (x, 1), tem, 1); 296 validate_unshare_change (insn, &XEXP (x, 1), tem, 1);
282 return true; 297 return true;
283 } 298 }
284 else 299 else
285 return false; 300 return false;
286 } 301 }
287 302
288 303
289 /* This subroutine of apply_change_group verifies whether the changes to INSN 304 /* This subroutine of apply_change_group verifies whether the changes to INSN
290 were valid; i.e. whether INSN can still be recognized. */ 305 were valid; i.e. whether INSN can still be recognized.
306
307 If IN_GROUP is true clobbers which have to be added in order to
308 match the instructions will be added to the current change group.
309 Otherwise the changes will take effect immediately. */
291 310
292 int 311 int
293 insn_invalid_p (rtx insn) 312 insn_invalid_p (rtx_insn *insn, bool in_group)
294 { 313 {
295 rtx pat = PATTERN (insn); 314 rtx pat = PATTERN (insn);
296 int num_clobbers = 0; 315 int num_clobbers = 0;
297 /* If we are before reload and the pattern is a SET, see if we can add 316 /* If we are before reload and the pattern is a SET, see if we can add
298 clobbers. */ 317 clobbers. */
299 int icode = recog (pat, insn, 318 int icode = recog (pat, insn,
300 (GET_CODE (pat) == SET 319 (GET_CODE (pat) == SET
301 && ! reload_completed && ! reload_in_progress) 320 && ! reload_completed
321 && ! reload_in_progress)
302 ? &num_clobbers : 0); 322 ? &num_clobbers : 0);
303 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; 323 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
304 324
305 325
306 /* If this is an asm and the operand aren't legal, then fail. Likewise if 326 /* If this is an asm and the operand aren't legal, then fail. Likewise if
320 return 1; 340 return 1;
321 341
322 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1)); 342 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
323 XVECEXP (newpat, 0, 0) = pat; 343 XVECEXP (newpat, 0, 0) = pat;
324 add_clobbers (newpat, icode); 344 add_clobbers (newpat, icode);
325 PATTERN (insn) = pat = newpat; 345 if (in_group)
346 validate_change (insn, &PATTERN (insn), newpat, 1);
347 else
348 PATTERN (insn) = pat = newpat;
326 } 349 }
327 350
328 /* After reload, verify that all constraints are satisfied. */ 351 /* After reload, verify that all constraints are satisfied. */
329 if (reload_completed) 352 if (reload_completed)
330 { 353 {
331 extract_insn (insn); 354 extract_insn (insn);
332 355
333 if (! constrain_operands (1)) 356 if (! constrain_operands (1, get_preferred_alternatives (insn)))
334 return 1; 357 return 1;
335 } 358 }
336 359
337 INSN_CODE (insn) = icode; 360 INSN_CODE (insn) = icode;
338 return 0; 361 return 0;
377 if (! memory_address_addr_space_p (GET_MODE (object), 400 if (! memory_address_addr_space_p (GET_MODE (object),
378 XEXP (object, 0), 401 XEXP (object, 0),
379 MEM_ADDR_SPACE (object))) 402 MEM_ADDR_SPACE (object)))
380 break; 403 break;
381 } 404 }
382 else if (REG_P (changes[i].old) 405 else if (/* changes[i].old might be zero, e.g. when putting a
406 REG_FRAME_RELATED_EXPR into a previously empty list. */
407 changes[i].old
408 && REG_P (changes[i].old)
383 && asm_noperands (PATTERN (object)) > 0 409 && asm_noperands (PATTERN (object)) > 0
384 && REG_EXPR (changes[i].old) != NULL_TREE 410 && REG_EXPR (changes[i].old) != NULL_TREE
411 && HAS_DECL_ASSEMBLER_NAME_P (REG_EXPR (changes[i].old))
385 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old)) 412 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old))
386 && DECL_REGISTER (REG_EXPR (changes[i].old))) 413 && DECL_REGISTER (REG_EXPR (changes[i].old)))
387 { 414 {
388 /* Don't allow changes of hard register operands to inline 415 /* Don't allow changes of hard register operands to inline
389 assemblies if they have been defined as register asm ("x"). */ 416 assemblies if they have been defined as register asm ("x"). */
390 break; 417 break;
391 } 418 }
392 else if (DEBUG_INSN_P (object)) 419 else if (DEBUG_INSN_P (object))
393 continue; 420 continue;
394 else if (insn_invalid_p (object)) 421 else if (insn_invalid_p (as_a <rtx_insn *> (object), true))
395 { 422 {
396 rtx pat = PATTERN (object); 423 rtx pat = PATTERN (object);
397 424
398 /* Perhaps we couldn't recognize the insn because there were 425 /* Perhaps we couldn't recognize the insn because there were
399 extra CLOBBERs at the end. If so, try to re-recognize 426 extra CLOBBERs at the end. If so, try to re-recognize
465 /* Avoid unnecessary rescanning when multiple changes to same instruction 492 /* Avoid unnecessary rescanning when multiple changes to same instruction
466 are made. */ 493 are made. */
467 if (object) 494 if (object)
468 { 495 {
469 if (object != last_object && last_object && INSN_P (last_object)) 496 if (object != last_object && last_object && INSN_P (last_object))
470 df_insn_rescan (last_object); 497 df_insn_rescan (as_a <rtx_insn *> (last_object));
471 last_object = object; 498 last_object = object;
472 } 499 }
473 } 500 }
474 501
475 if (last_object && INSN_P (last_object)) 502 if (last_object && INSN_P (last_object))
476 df_insn_rescan (last_object); 503 df_insn_rescan (as_a <rtx_insn *> (last_object));
477 num_changes = 0; 504 num_changes = 0;
478 } 505 }
479 506
480 /* Apply a group of changes previously issued with `validate_change'. 507 /* Apply a group of changes previously issued with `validate_change'.
481 If all changes are valid, call confirm_change_group and return 1, 508 If all changes are valid, call confirm_change_group and return 1,
521 INSN_CODE (changes[i].object) = changes[i].old_code; 548 INSN_CODE (changes[i].object) = changes[i].old_code;
522 } 549 }
523 num_changes = num; 550 num_changes = num;
524 } 551 }
525 552
553 /* Reduce conditional compilation elsewhere. */
526 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting 554 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
527 rtx. */ 555 rtx. */
528 556
529 static void 557 static void
530 simplify_while_replacing (rtx *loc, rtx to, rtx object, 558 simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object,
531 enum machine_mode op0_mode) 559 machine_mode op0_mode)
532 { 560 {
533 rtx x = *loc; 561 rtx x = *loc;
534 enum rtx_code code = GET_CODE (x); 562 enum rtx_code code = GET_CODE (x);
535 rtx new_rtx; 563 rtx new_rtx = NULL_RTX;
564 scalar_int_mode is_mode;
536 565
537 if (SWAPPABLE_OPERANDS_P (x) 566 if (SWAPPABLE_OPERANDS_P (x)
538 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 567 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
539 { 568 {
540 validate_unshare_change (object, loc, 569 validate_unshare_change (object, loc,
542 : swap_condition (code), 571 : swap_condition (code),
543 GET_MODE (x), XEXP (x, 1), 572 GET_MODE (x), XEXP (x, 1),
544 XEXP (x, 0)), 1); 573 XEXP (x, 0)), 1);
545 x = *loc; 574 x = *loc;
546 code = GET_CODE (x); 575 code = GET_CODE (x);
576 }
577
578 /* Canonicalize arithmetics with all constant operands. */
579 switch (GET_RTX_CLASS (code))
580 {
581 case RTX_UNARY:
582 if (CONSTANT_P (XEXP (x, 0)))
583 new_rtx = simplify_unary_operation (code, GET_MODE (x), XEXP (x, 0),
584 op0_mode);
585 break;
586 case RTX_COMM_ARITH:
587 case RTX_BIN_ARITH:
588 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
589 new_rtx = simplify_binary_operation (code, GET_MODE (x), XEXP (x, 0),
590 XEXP (x, 1));
591 break;
592 case RTX_COMPARE:
593 case RTX_COMM_COMPARE:
594 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
595 new_rtx = simplify_relational_operation (code, GET_MODE (x), op0_mode,
596 XEXP (x, 0), XEXP (x, 1));
597 break;
598 default:
599 break;
600 }
601 if (new_rtx)
602 {
603 validate_change (object, loc, new_rtx, 1);
604 return;
547 } 605 }
548 606
549 switch (code) 607 switch (code)
550 { 608 {
551 case PLUS: 609 case PLUS:
557 validate_change (object, loc, 615 validate_change (object, loc,
558 simplify_gen_binary 616 simplify_gen_binary
559 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1); 617 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
560 break; 618 break;
561 case MINUS: 619 case MINUS:
562 if (CONST_INT_P (XEXP (x, 1)) 620 if (CONST_SCALAR_INT_P (XEXP (x, 1)))
563 || GET_CODE (XEXP (x, 1)) == CONST_DOUBLE)
564 validate_change (object, loc, 621 validate_change (object, loc,
565 simplify_gen_binary 622 simplify_gen_binary
566 (PLUS, GET_MODE (x), XEXP (x, 0), 623 (PLUS, GET_MODE (x), XEXP (x, 0),
567 simplify_gen_unary (NEG, 624 simplify_gen_unary (NEG,
568 GET_MODE (x), XEXP (x, 1), 625 GET_MODE (x), XEXP (x, 1),
598 to be the mode required for memory in extract operations (this isn't 655 to be the mode required for memory in extract operations (this isn't
599 likely to be an insertion operation; if it was, nothing bad will 656 likely to be an insertion operation; if it was, nothing bad will
600 happen, we might just fail in some cases). */ 657 happen, we might just fail in some cases). */
601 658
602 if (MEM_P (XEXP (x, 0)) 659 if (MEM_P (XEXP (x, 0))
660 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &is_mode)
603 && CONST_INT_P (XEXP (x, 1)) 661 && CONST_INT_P (XEXP (x, 1))
604 && CONST_INT_P (XEXP (x, 2)) 662 && CONST_INT_P (XEXP (x, 2))
605 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0)) 663 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0),
664 MEM_ADDR_SPACE (XEXP (x, 0)))
606 && !MEM_VOLATILE_P (XEXP (x, 0))) 665 && !MEM_VOLATILE_P (XEXP (x, 0)))
607 { 666 {
608 enum machine_mode wanted_mode = VOIDmode;
609 enum machine_mode is_mode = GET_MODE (XEXP (x, 0));
610 int pos = INTVAL (XEXP (x, 2)); 667 int pos = INTVAL (XEXP (x, 2));
611 668 machine_mode new_mode = is_mode;
612 if (GET_CODE (x) == ZERO_EXTRACT) 669 if (GET_CODE (x) == ZERO_EXTRACT && targetm.have_extzv ())
613 { 670 new_mode = insn_data[targetm.code_for_extzv].operand[1].mode;
614 enum machine_mode new_mode 671 else if (GET_CODE (x) == SIGN_EXTRACT && targetm.have_extv ())
615 = mode_for_extraction (EP_extzv, 1); 672 new_mode = insn_data[targetm.code_for_extv].operand[1].mode;
616 if (new_mode != MAX_MACHINE_MODE) 673 scalar_int_mode wanted_mode = (new_mode == VOIDmode
617 wanted_mode = new_mode; 674 ? word_mode
618 } 675 : as_a <scalar_int_mode> (new_mode));
619 else if (GET_CODE (x) == SIGN_EXTRACT)
620 {
621 enum machine_mode new_mode
622 = mode_for_extraction (EP_extv, 1);
623 if (new_mode != MAX_MACHINE_MODE)
624 wanted_mode = new_mode;
625 }
626 676
627 /* If we have a narrower mode, we can do something. */ 677 /* If we have a narrower mode, we can do something. */
628 if (wanted_mode != VOIDmode 678 if (GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
629 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
630 { 679 {
631 int offset = pos / BITS_PER_UNIT; 680 int offset = pos / BITS_PER_UNIT;
632 rtx newmem; 681 rtx newmem;
633 682
634 /* If the bytes and bits are counted differently, we 683 /* If the bytes and bits are counted differently, we
636 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN) 685 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
637 offset = 686 offset =
638 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) - 687 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
639 offset); 688 offset);
640 689
690 gcc_assert (GET_MODE_PRECISION (wanted_mode)
691 == GET_MODE_BITSIZE (wanted_mode));
641 pos %= GET_MODE_BITSIZE (wanted_mode); 692 pos %= GET_MODE_BITSIZE (wanted_mode);
642 693
643 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset); 694 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
644 695
645 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); 696 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
656 707
657 /* Replace every occurrence of FROM in X with TO. Mark each change with 708 /* Replace every occurrence of FROM in X with TO. Mark each change with
658 validate_change passing OBJECT. */ 709 validate_change passing OBJECT. */
659 710
660 static void 711 static void
661 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx object, 712 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
662 bool simplify) 713 bool simplify)
663 { 714 {
664 int i, j; 715 int i, j;
665 const char *fmt; 716 const char *fmt;
666 rtx x = *loc; 717 rtx x = *loc;
667 enum rtx_code code; 718 enum rtx_code code;
668 enum machine_mode op0_mode = VOIDmode; 719 machine_mode op0_mode = VOIDmode;
669 int prev_changes = num_changes; 720 int prev_changes = num_changes;
670 721
671 if (!x) 722 if (!x)
672 return; 723 return;
673 724
692 } 743 }
693 744
694 /* Call ourself recursively to perform the replacements. 745 /* Call ourself recursively to perform the replacements.
695 We must not replace inside already replaced expression, otherwise we 746 We must not replace inside already replaced expression, otherwise we
696 get infinite recursion for replacements like (reg X)->(subreg (reg X)) 747 get infinite recursion for replacements like (reg X)->(subreg (reg X))
697 done by regmove, so we must special case shared ASM_OPERANDS. */ 748 so we must special case shared ASM_OPERANDS. */
698 749
699 if (GET_CODE (x) == PARALLEL) 750 if (GET_CODE (x) == PARALLEL)
700 { 751 {
701 for (j = XVECLEN (x, 0) - 1; j >= 0; j--) 752 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
702 { 753 {
728 779
729 /* If we didn't substitute, there is nothing more to do. */ 780 /* If we didn't substitute, there is nothing more to do. */
730 if (num_changes == prev_changes) 781 if (num_changes == prev_changes)
731 return; 782 return;
732 783
784 /* ??? The regmove is no more, so is this aberration still necessary? */
733 /* Allow substituted expression to have different mode. This is used by 785 /* Allow substituted expression to have different mode. This is used by
734 regmove to change mode of pseudo register. */ 786 regmove to change mode of pseudo register. */
735 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode) 787 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
736 op0_mode = GET_MODE (XEXP (x, 0)); 788 op0_mode = GET_MODE (XEXP (x, 0));
737 789
744 /* Try replacing every occurrence of FROM in subexpression LOC of INSN 796 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
745 with TO. After all changes have been made, validate by seeing 797 with TO. After all changes have been made, validate by seeing
746 if INSN is still valid. */ 798 if INSN is still valid. */
747 799
748 int 800 int
749 validate_replace_rtx_subexp (rtx from, rtx to, rtx insn, rtx *loc) 801 validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
750 { 802 {
751 validate_replace_rtx_1 (loc, from, to, insn, true); 803 validate_replace_rtx_1 (loc, from, to, insn, true);
752 return apply_change_group (); 804 return apply_change_group ();
753 } 805 }
754 806
755 /* Try replacing every occurrence of FROM in INSN with TO. After all 807 /* Try replacing every occurrence of FROM in INSN with TO. After all
756 changes have been made, validate by seeing if INSN is still valid. */ 808 changes have been made, validate by seeing if INSN is still valid. */
757 809
758 int 810 int
759 validate_replace_rtx (rtx from, rtx to, rtx insn) 811 validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
760 { 812 {
761 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true); 813 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
762 return apply_change_group (); 814 return apply_change_group ();
763 } 815 }
764 816
767 INSN is still valid. 819 INSN is still valid.
768 validate_replace_rtx (from, to, insn) is equivalent to 820 validate_replace_rtx (from, to, insn) is equivalent to
769 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */ 821 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
770 822
771 int 823 int
772 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx insn) 824 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
773 { 825 {
774 validate_replace_rtx_1 (where, from, to, insn, true); 826 validate_replace_rtx_1 (where, from, to, insn, true);
775 return apply_change_group (); 827 return apply_change_group ();
776 } 828 }
777 829
778 /* Same as above, but do not simplify rtx afterwards. */ 830 /* Same as above, but do not simplify rtx afterwards. */
779 int 831 int
780 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where, 832 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
781 rtx insn) 833 rtx_insn *insn)
782 { 834 {
783 validate_replace_rtx_1 (where, from, to, insn, false); 835 validate_replace_rtx_1 (where, from, to, insn, false);
784 return apply_change_group (); 836 return apply_change_group ();
785 837
786 } 838 }
787 839
788 /* Try replacing every occurrence of FROM in INSN with TO. This also 840 /* Try replacing every occurrence of FROM in INSN with TO. This also
789 will replace in REG_EQUAL and REG_EQUIV notes. */ 841 will replace in REG_EQUAL and REG_EQUIV notes. */
790 842
791 void 843 void
792 validate_replace_rtx_group (rtx from, rtx to, rtx insn) 844 validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn)
793 { 845 {
794 rtx note; 846 rtx note;
795 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true); 847 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
796 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 848 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
797 if (REG_NOTE_KIND (note) == REG_EQUAL 849 if (REG_NOTE_KIND (note) == REG_EQUAL
802 /* Function called by note_uses to replace used subexpressions. */ 854 /* Function called by note_uses to replace used subexpressions. */
803 struct validate_replace_src_data 855 struct validate_replace_src_data
804 { 856 {
805 rtx from; /* Old RTX */ 857 rtx from; /* Old RTX */
806 rtx to; /* New RTX */ 858 rtx to; /* New RTX */
807 rtx insn; /* Insn in which substitution is occurring. */ 859 rtx_insn *insn; /* Insn in which substitution is occurring. */
808 }; 860 };
809 861
810 static void 862 static void
811 validate_replace_src_1 (rtx *x, void *data) 863 validate_replace_src_1 (rtx *x, void *data)
812 { 864 {
818 870
819 /* Try replacing every occurrence of FROM in INSN with TO, avoiding 871 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
820 SET_DESTs. */ 872 SET_DESTs. */
821 873
822 void 874 void
823 validate_replace_src_group (rtx from, rtx to, rtx insn) 875 validate_replace_src_group (rtx from, rtx to, rtx_insn *insn)
824 { 876 {
825 struct validate_replace_src_data d; 877 struct validate_replace_src_data d;
826 878
827 d.from = from; 879 d.from = from;
828 d.to = to; 880 d.to = to;
833 /* Try simplify INSN. 885 /* Try simplify INSN.
834 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's 886 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
835 pattern and return true if something was simplified. */ 887 pattern and return true if something was simplified. */
836 888
837 bool 889 bool
838 validate_simplify_insn (rtx insn) 890 validate_simplify_insn (rtx_insn *insn)
839 { 891 {
840 int i; 892 int i;
841 rtx pat = NULL; 893 rtx pat = NULL;
842 rtx newpat = NULL; 894 rtx newpat = NULL;
843 895
868 } 920 }
869 } 921 }
870 return ((num_changes_pending () > 0) && (apply_change_group () > 0)); 922 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
871 } 923 }
872 924
873 #ifdef HAVE_cc0
874 /* Return 1 if the insn using CC0 set by INSN does not contain 925 /* Return 1 if the insn using CC0 set by INSN does not contain
875 any ordered tests applied to the condition codes. 926 any ordered tests applied to the condition codes.
876 EQ and NE tests do not count. */ 927 EQ and NE tests do not count. */
877 928
878 int 929 int
879 next_insn_tests_no_inequality (rtx insn) 930 next_insn_tests_no_inequality (rtx_insn *insn)
880 { 931 {
881 rtx next = next_cc0_user (insn); 932 rtx_insn *next = next_cc0_user (insn);
882 933
883 /* If there is no next insn, we have to take the conservative choice. */ 934 /* If there is no next insn, we have to take the conservative choice. */
884 if (next == 0) 935 if (next == 0)
885 return 0; 936 return 0;
886 937
887 return (INSN_P (next) 938 return (INSN_P (next)
888 && ! inequality_comparisons_p (PATTERN (next))); 939 && ! inequality_comparisons_p (PATTERN (next)));
889 } 940 }
890 #endif
891 941
892 /* Return 1 if OP is a valid general operand for machine mode MODE. 942 /* Return 1 if OP is a valid general operand for machine mode MODE.
893 This is either a register reference, a memory reference, 943 This is either a register reference, a memory reference,
894 or a constant. In the case of a memory reference, the address 944 or a constant. In the case of a memory reference, the address
895 is checked for general validity for the target machine. 945 is checked for general validity for the target machine.
899 949
900 If MODE is VOIDmode, OP is checked for validity for whatever mode 950 If MODE is VOIDmode, OP is checked for validity for whatever mode
901 it has. 951 it has.
902 952
903 The main use of this function is as a predicate in match_operand 953 The main use of this function is as a predicate in match_operand
904 expressions in the machine description. 954 expressions in the machine description. */
905
906 For an explanation of this function's behavior for registers of
907 class NO_REGS, see the comment for `register_operand'. */
908 955
909 int 956 int
910 general_operand (rtx op, enum machine_mode mode) 957 general_operand (rtx op, machine_mode mode)
911 { 958 {
912 enum rtx_code code = GET_CODE (op); 959 enum rtx_code code = GET_CODE (op);
913 960
914 if (mode == VOIDmode) 961 if (mode == VOIDmode)
915 mode = GET_MODE (op); 962 mode = GET_MODE (op);
928 975
929 if (CONSTANT_P (op)) 976 if (CONSTANT_P (op))
930 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode 977 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
931 || mode == VOIDmode) 978 || mode == VOIDmode)
932 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 979 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
933 && LEGITIMATE_CONSTANT_P (op)); 980 && targetm.legitimate_constant_p (mode == VOIDmode
981 ? GET_MODE (op)
982 : mode, op));
934 983
935 /* Except for certain constants with VOIDmode, already checked for, 984 /* Except for certain constants with VOIDmode, already checked for,
936 OP's mode must match MODE if MODE specifies a mode. */ 985 OP's mode must match MODE if MODE specifies a mode. */
937 986
938 if (GET_MODE (op) != mode) 987 if (GET_MODE (op) != mode)
946 /* On machines that have insn scheduling, we want all memory 995 /* On machines that have insn scheduling, we want all memory
947 reference to be explicit, so outlaw paradoxical SUBREGs. 996 reference to be explicit, so outlaw paradoxical SUBREGs.
948 However, we must allow them after reload so that they can 997 However, we must allow them after reload so that they can
949 get cleaned up by cleanup_subreg_operands. */ 998 get cleaned up by cleanup_subreg_operands. */
950 if (!reload_completed && MEM_P (sub) 999 if (!reload_completed && MEM_P (sub)
951 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub))) 1000 && paradoxical_subreg_p (op))
952 return 0; 1001 return 0;
953 #endif 1002 #endif
954 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory 1003 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
955 may result in incorrect reference. We should simplify all valid 1004 may result in incorrect reference. We should simplify all valid
956 subregs of MEM anyway. But allow this after reload because we 1005 subregs of MEM anyway. But allow this after reload because we
959 ??? This is a kludge. */ 1008 ??? This is a kludge. */
960 if (!reload_completed && SUBREG_BYTE (op) != 0 1009 if (!reload_completed && SUBREG_BYTE (op) != 0
961 && MEM_P (sub)) 1010 && MEM_P (sub))
962 return 0; 1011 return 0;
963 1012
1013 if (REG_P (sub)
1014 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1015 && !REG_CAN_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1016 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1017 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT
1018 /* LRA can generate some invalid SUBREGS just for matched
1019 operand reload presentation. LRA needs to treat them as
1020 valid. */
1021 && ! LRA_SUBREG_P (op))
1022 return 0;
1023
964 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally 1024 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
965 create such rtl, and we must reject it. */ 1025 create such rtl, and we must reject it. */
966 if (SCALAR_FLOAT_MODE_P (GET_MODE (op)) 1026 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
967 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub))) 1027 /* LRA can use subreg to store a floating point value in an
1028 integer mode. Although the floating point and the
1029 integer modes need the same number of hard registers, the
1030 size of floating point mode can be less than the integer
1031 mode. */
1032 && ! lra_in_progress
1033 && paradoxical_subreg_p (op))
968 return 0; 1034 return 0;
969 1035
970 op = sub; 1036 op = sub;
971 code = GET_CODE (op); 1037 code = GET_CODE (op);
972 } 1038 }
973 1039
974 if (code == REG) 1040 if (code == REG)
975 /* A register whose class is NO_REGS is not a general operand. */
976 return (REGNO (op) >= FIRST_PSEUDO_REGISTER 1041 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
977 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS); 1042 || in_hard_reg_set_p (operand_reg_set, GET_MODE (op), REGNO (op)));
978 1043
979 if (code == MEM) 1044 if (code == MEM)
980 { 1045 {
981 rtx y = XEXP (op, 0); 1046 rtx y = XEXP (op, 0);
982 1047
983 if (! volatile_ok && MEM_VOLATILE_P (op)) 1048 if (! volatile_ok && MEM_VOLATILE_P (op))
984 return 0; 1049 return 0;
985 1050
986 /* Use the mem's mode, since it will be reloaded thus. */ 1051 /* Use the mem's mode, since it will be reloaded thus. LRA can
987 if (memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op))) 1052 generate move insn with invalid addresses which is made valid
1053 and efficiently calculated by LRA through further numerous
1054 transformations. */
1055 if (lra_in_progress
1056 || memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op)))
988 return 1; 1057 return 1;
989 } 1058 }
990 1059
991 return 0; 1060 return 0;
992 } 1061 }
996 1065
997 The main use of this function is as a predicate in match_operand 1066 The main use of this function is as a predicate in match_operand
998 expressions in the machine description. */ 1067 expressions in the machine description. */
999 1068
1000 int 1069 int
1001 address_operand (rtx op, enum machine_mode mode) 1070 address_operand (rtx op, machine_mode mode)
1002 { 1071 {
1003 return memory_address_p (mode, op); 1072 return memory_address_p (mode, op);
1004 } 1073 }
1005 1074
1006 /* Return 1 if OP is a register reference of mode MODE. 1075 /* Return 1 if OP is a register reference of mode MODE.
1007 If MODE is VOIDmode, accept a register in any mode. 1076 If MODE is VOIDmode, accept a register in any mode.
1008 1077
1009 The main use of this function is as a predicate in match_operand 1078 The main use of this function is as a predicate in match_operand
1010 expressions in the machine description. 1079 expressions in the machine description. */
1011
1012 As a special exception, registers whose class is NO_REGS are
1013 not accepted by `register_operand'. The reason for this change
1014 is to allow the representation of special architecture artifacts
1015 (such as a condition code register) without extending the rtl
1016 definitions. Since registers of class NO_REGS cannot be used
1017 as registers in any case where register classes are examined,
1018 it is most consistent to keep this function from accepting them. */
1019 1080
1020 int 1081 int
1021 register_operand (rtx op, enum machine_mode mode) 1082 register_operand (rtx op, machine_mode mode)
1022 { 1083 {
1023 if (GET_MODE (op) != mode && mode != VOIDmode)
1024 return 0;
1025
1026 if (GET_CODE (op) == SUBREG) 1084 if (GET_CODE (op) == SUBREG)
1027 { 1085 {
1028 rtx sub = SUBREG_REG (op); 1086 rtx sub = SUBREG_REG (op);
1029 1087
1030 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand 1088 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1031 because it is guaranteed to be reloaded into one. 1089 because it is guaranteed to be reloaded into one.
1032 Just make sure the MEM is valid in itself. 1090 Just make sure the MEM is valid in itself.
1033 (Ideally, (SUBREG (MEM)...) should not exist after reload, 1091 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1034 but currently it does result from (SUBREG (REG)...) where the 1092 but currently it does result from (SUBREG (REG)...) where the
1035 reg went on the stack.) */ 1093 reg went on the stack.) */
1036 if (! reload_completed && MEM_P (sub)) 1094 if (!REG_P (sub) && (reload_completed || !MEM_P (sub)))
1037 return general_operand (op, mode);
1038
1039 #ifdef CANNOT_CHANGE_MODE_CLASS
1040 if (REG_P (sub)
1041 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1042 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1043 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1044 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT)
1045 return 0; 1095 return 0;
1046 #endif 1096 }
1047 1097 else if (!REG_P (op))
1048 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally 1098 return 0;
1049 create such rtl, and we must reject it. */ 1099 return general_operand (op, mode);
1050 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
1051 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
1052 return 0;
1053
1054 op = sub;
1055 }
1056
1057 /* We don't consider registers whose class is NO_REGS
1058 to be a register operand. */
1059 return (REG_P (op)
1060 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1061 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1062 } 1100 }
1063 1101
1064 /* Return 1 for a register in Pmode; ignore the tested mode. */ 1102 /* Return 1 for a register in Pmode; ignore the tested mode. */
1065 1103
1066 int 1104 int
1067 pmode_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1105 pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
1068 { 1106 {
1069 return register_operand (op, Pmode); 1107 return register_operand (op, Pmode);
1070 } 1108 }
1071 1109
1072 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH 1110 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1073 or a hard register. */ 1111 or a hard register. */
1074 1112
1075 int 1113 int
1076 scratch_operand (rtx op, enum machine_mode mode) 1114 scratch_operand (rtx op, machine_mode mode)
1077 { 1115 {
1078 if (GET_MODE (op) != mode && mode != VOIDmode) 1116 if (GET_MODE (op) != mode && mode != VOIDmode)
1079 return 0; 1117 return 0;
1080 1118
1081 return (GET_CODE (op) == SCRATCH 1119 return (GET_CODE (op) == SCRATCH
1082 || (REG_P (op) 1120 || (REG_P (op)
1083 && REGNO (op) < FIRST_PSEUDO_REGISTER)); 1121 && (lra_in_progress
1122 || (REGNO (op) < FIRST_PSEUDO_REGISTER
1123 && REGNO_REG_CLASS (REGNO (op)) != NO_REGS))));
1084 } 1124 }
1085 1125
1086 /* Return 1 if OP is a valid immediate operand for mode MODE. 1126 /* Return 1 if OP is a valid immediate operand for mode MODE.
1087 1127
1088 The main use of this function is as a predicate in match_operand 1128 The main use of this function is as a predicate in match_operand
1089 expressions in the machine description. */ 1129 expressions in the machine description. */
1090 1130
1091 int 1131 int
1092 immediate_operand (rtx op, enum machine_mode mode) 1132 immediate_operand (rtx op, machine_mode mode)
1093 { 1133 {
1094 /* Don't accept CONST_INT or anything similar 1134 /* Don't accept CONST_INT or anything similar
1095 if the caller wants something floating. */ 1135 if the caller wants something floating. */
1096 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1136 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1097 && GET_MODE_CLASS (mode) != MODE_INT 1137 && GET_MODE_CLASS (mode) != MODE_INT
1105 1145
1106 return (CONSTANT_P (op) 1146 return (CONSTANT_P (op)
1107 && (GET_MODE (op) == mode || mode == VOIDmode 1147 && (GET_MODE (op) == mode || mode == VOIDmode
1108 || GET_MODE (op) == VOIDmode) 1148 || GET_MODE (op) == VOIDmode)
1109 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1149 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1110 && LEGITIMATE_CONSTANT_P (op)); 1150 && targetm.legitimate_constant_p (mode == VOIDmode
1111 } 1151 ? GET_MODE (op)
1112 1152 : mode, op));
1113 /* Returns 1 if OP is an operand that is a CONST_INT. */ 1153 }
1154
1155 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1114 1156
1115 int 1157 int
1116 const_int_operand (rtx op, enum machine_mode mode) 1158 const_int_operand (rtx op, machine_mode mode)
1117 { 1159 {
1118 if (!CONST_INT_P (op)) 1160 if (!CONST_INT_P (op))
1119 return 0; 1161 return 0;
1120 1162
1121 if (mode != VOIDmode 1163 if (mode != VOIDmode
1123 return 0; 1165 return 0;
1124 1166
1125 return 1; 1167 return 1;
1126 } 1168 }
1127 1169
1170 #if TARGET_SUPPORTS_WIDE_INT
1171 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1172 of mode MODE. */
1173 int
1174 const_scalar_int_operand (rtx op, machine_mode mode)
1175 {
1176 if (!CONST_SCALAR_INT_P (op))
1177 return 0;
1178
1179 if (CONST_INT_P (op))
1180 return const_int_operand (op, mode);
1181
1182 if (mode != VOIDmode)
1183 {
1184 scalar_int_mode int_mode = as_a <scalar_int_mode> (mode);
1185 int prec = GET_MODE_PRECISION (int_mode);
1186 int bitsize = GET_MODE_BITSIZE (int_mode);
1187
1188 if (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT > bitsize)
1189 return 0;
1190
1191 if (prec == bitsize)
1192 return 1;
1193 else
1194 {
1195 /* Multiword partial int. */
1196 HOST_WIDE_INT x
1197 = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1);
1198 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT - 1)) == x);
1199 }
1200 }
1201 return 1;
1202 }
1203
1128 /* Returns 1 if OP is an operand that is a constant integer or constant 1204 /* Returns 1 if OP is an operand that is a constant integer or constant
1129 floating-point number. */ 1205 floating-point number of MODE. */
1130 1206
1131 int 1207 int
1132 const_double_operand (rtx op, enum machine_mode mode) 1208 const_double_operand (rtx op, machine_mode mode)
1209 {
1210 return (GET_CODE (op) == CONST_DOUBLE)
1211 && (GET_MODE (op) == mode || mode == VOIDmode);
1212 }
1213 #else
1214 /* Returns 1 if OP is an operand that is a constant integer or constant
1215 floating-point number of MODE. */
1216
1217 int
1218 const_double_operand (rtx op, machine_mode mode)
1133 { 1219 {
1134 /* Don't accept CONST_INT or anything similar 1220 /* Don't accept CONST_INT or anything similar
1135 if the caller wants something floating. */ 1221 if the caller wants something floating. */
1136 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1222 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1137 && GET_MODE_CLASS (mode) != MODE_INT 1223 && GET_MODE_CLASS (mode) != MODE_INT
1138 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 1224 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1139 return 0; 1225 return 0;
1140 1226
1141 return ((GET_CODE (op) == CONST_DOUBLE || CONST_INT_P (op)) 1227 return ((CONST_DOUBLE_P (op) || CONST_INT_P (op))
1142 && (mode == VOIDmode || GET_MODE (op) == mode 1228 && (mode == VOIDmode || GET_MODE (op) == mode
1143 || GET_MODE (op) == VOIDmode)); 1229 || GET_MODE (op) == VOIDmode));
1144 } 1230 }
1145 1231 #endif
1146 /* Return 1 if OP is a general operand that is not an immediate operand. */ 1232 /* Return 1 if OP is a general operand that is not an immediate
1233 operand of mode MODE. */
1147 1234
1148 int 1235 int
1149 nonimmediate_operand (rtx op, enum machine_mode mode) 1236 nonimmediate_operand (rtx op, machine_mode mode)
1150 { 1237 {
1151 return (general_operand (op, mode) && ! CONSTANT_P (op)); 1238 return (general_operand (op, mode) && ! CONSTANT_P (op));
1152 } 1239 }
1153 1240
1154 /* Return 1 if OP is a register reference or immediate value of mode MODE. */ 1241 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1155 1242
1156 int 1243 int
1157 nonmemory_operand (rtx op, enum machine_mode mode) 1244 nonmemory_operand (rtx op, machine_mode mode)
1158 { 1245 {
1159 if (CONSTANT_P (op)) 1246 if (CONSTANT_P (op))
1160 return immediate_operand (op, mode); 1247 return immediate_operand (op, mode);
1161 1248 return register_operand (op, mode);
1162 if (GET_MODE (op) != mode && mode != VOIDmode)
1163 return 0;
1164
1165 if (GET_CODE (op) == SUBREG)
1166 {
1167 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1168 because it is guaranteed to be reloaded into one.
1169 Just make sure the MEM is valid in itself.
1170 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1171 but currently it does result from (SUBREG (REG)...) where the
1172 reg went on the stack.) */
1173 if (! reload_completed && MEM_P (SUBREG_REG (op)))
1174 return general_operand (op, mode);
1175 op = SUBREG_REG (op);
1176 }
1177
1178 /* We don't consider registers whose class is NO_REGS
1179 to be a register operand. */
1180 return (REG_P (op)
1181 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1182 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1183 } 1249 }
1184 1250
1185 /* Return 1 if OP is a valid operand that stands for pushing a 1251 /* Return 1 if OP is a valid operand that stands for pushing a
1186 value of mode MODE onto the stack. 1252 value of mode MODE onto the stack.
1187 1253
1188 The main use of this function is as a predicate in match_operand 1254 The main use of this function is as a predicate in match_operand
1189 expressions in the machine description. */ 1255 expressions in the machine description. */
1190 1256
1191 int 1257 int
1192 push_operand (rtx op, enum machine_mode mode) 1258 push_operand (rtx op, machine_mode mode)
1193 { 1259 {
1194 unsigned int rounded_size = GET_MODE_SIZE (mode); 1260 unsigned int rounded_size = GET_MODE_SIZE (mode);
1195 1261
1196 #ifdef PUSH_ROUNDING 1262 #ifdef PUSH_ROUNDING
1197 rounded_size = PUSH_ROUNDING (rounded_size); 1263 rounded_size = PUSH_ROUNDING (rounded_size);
1214 { 1280 {
1215 if (GET_CODE (op) != PRE_MODIFY 1281 if (GET_CODE (op) != PRE_MODIFY
1216 || GET_CODE (XEXP (op, 1)) != PLUS 1282 || GET_CODE (XEXP (op, 1)) != PLUS
1217 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0) 1283 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1218 || !CONST_INT_P (XEXP (XEXP (op, 1), 1)) 1284 || !CONST_INT_P (XEXP (XEXP (op, 1), 1))
1219 #ifdef STACK_GROWS_DOWNWARD 1285 || INTVAL (XEXP (XEXP (op, 1), 1))
1220 || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size 1286 != ((STACK_GROWS_DOWNWARD ? -1 : 1) * (int) rounded_size))
1221 #else
1222 || INTVAL (XEXP (XEXP (op, 1), 1)) != (int) rounded_size
1223 #endif
1224 )
1225 return 0; 1287 return 0;
1226 } 1288 }
1227 1289
1228 return XEXP (op, 0) == stack_pointer_rtx; 1290 return XEXP (op, 0) == stack_pointer_rtx;
1229 } 1291 }
1233 1295
1234 The main use of this function is as a predicate in match_operand 1296 The main use of this function is as a predicate in match_operand
1235 expressions in the machine description. */ 1297 expressions in the machine description. */
1236 1298
1237 int 1299 int
1238 pop_operand (rtx op, enum machine_mode mode) 1300 pop_operand (rtx op, machine_mode mode)
1239 { 1301 {
1240 if (!MEM_P (op)) 1302 if (!MEM_P (op))
1241 return 0; 1303 return 0;
1242 1304
1243 if (mode != VOIDmode && GET_MODE (op) != mode) 1305 if (mode != VOIDmode && GET_MODE (op) != mode)
1253 1315
1254 /* Return 1 if ADDR is a valid memory address 1316 /* Return 1 if ADDR is a valid memory address
1255 for mode MODE in address space AS. */ 1317 for mode MODE in address space AS. */
1256 1318
1257 int 1319 int
1258 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED, 1320 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED,
1259 rtx addr, addr_space_t as) 1321 rtx addr, addr_space_t as)
1260 { 1322 {
1261 #ifdef GO_IF_LEGITIMATE_ADDRESS 1323 #ifdef GO_IF_LEGITIMATE_ADDRESS
1262 gcc_assert (ADDR_SPACE_GENERIC_P (as)); 1324 gcc_assert (ADDR_SPACE_GENERIC_P (as));
1263 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); 1325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1275 1337
1276 The main use of this function is as a predicate in match_operand 1338 The main use of this function is as a predicate in match_operand
1277 expressions in the machine description. */ 1339 expressions in the machine description. */
1278 1340
1279 int 1341 int
1280 memory_operand (rtx op, enum machine_mode mode) 1342 memory_operand (rtx op, machine_mode mode)
1281 { 1343 {
1282 rtx inner; 1344 rtx inner;
1283 1345
1284 if (! reload_completed) 1346 if (! reload_completed)
1285 /* Note that no SUBREG is a memory operand before end of reload pass, 1347 /* Note that no SUBREG is a memory operand before end of reload pass,
1298 1360
1299 /* Return 1 if OP is a valid indirect memory reference with mode MODE; 1361 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1300 that is, a memory reference whose address is a general_operand. */ 1362 that is, a memory reference whose address is a general_operand. */
1301 1363
1302 int 1364 int
1303 indirect_operand (rtx op, enum machine_mode mode) 1365 indirect_operand (rtx op, machine_mode mode)
1304 { 1366 {
1305 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ 1367 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1306 if (! reload_completed 1368 if (! reload_completed
1307 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))) 1369 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
1308 { 1370 {
1331 1393
1332 /* Return 1 if this is an ordered comparison operator (not including 1394 /* Return 1 if this is an ordered comparison operator (not including
1333 ORDERED and UNORDERED). */ 1395 ORDERED and UNORDERED). */
1334 1396
1335 int 1397 int
1336 ordered_comparison_operator (rtx op, enum machine_mode mode) 1398 ordered_comparison_operator (rtx op, machine_mode mode)
1337 { 1399 {
1338 if (mode != VOIDmode && GET_MODE (op) != mode) 1400 if (mode != VOIDmode && GET_MODE (op) != mode)
1339 return false; 1401 return false;
1340 switch (GET_CODE (op)) 1402 switch (GET_CODE (op))
1341 { 1403 {
1357 1419
1358 /* Return 1 if this is a comparison operator. This allows the use of 1420 /* Return 1 if this is a comparison operator. This allows the use of
1359 MATCH_OPERATOR to recognize all the branch insns. */ 1421 MATCH_OPERATOR to recognize all the branch insns. */
1360 1422
1361 int 1423 int
1362 comparison_operator (rtx op, enum machine_mode mode) 1424 comparison_operator (rtx op, machine_mode mode)
1363 { 1425 {
1364 return ((mode == VOIDmode || GET_MODE (op) == mode) 1426 return ((mode == VOIDmode || GET_MODE (op) == mode)
1365 && COMPARISON_P (op)); 1427 && COMPARISON_P (op));
1366 } 1428 }
1367 1429
1401 return NULL; 1463 return NULL;
1402 } 1464 }
1403 1465
1404 /* If BODY is an insn body that uses ASM_OPERANDS, 1466 /* If BODY is an insn body that uses ASM_OPERANDS,
1405 return the number of operands (both input and output) in the insn. 1467 return the number of operands (both input and output) in the insn.
1468 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1469 return 0.
1406 Otherwise return -1. */ 1470 Otherwise return -1. */
1407 1471
1408 int 1472 int
1409 asm_noperands (const_rtx body) 1473 asm_noperands (const_rtx body)
1410 { 1474 {
1411 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body)); 1475 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
1412 int n_sets = 0; 1476 int i, n_sets = 0;
1413 1477
1414 if (asm_op == NULL) 1478 if (asm_op == NULL)
1415 return -1; 1479 {
1480 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) >= 2
1481 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
1482 {
1483 /* body is [(asm_input ...) (clobber (reg ...))...]. */
1484 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1485 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1486 return -1;
1487 return 0;
1488 }
1489 return -1;
1490 }
1416 1491
1417 if (GET_CODE (body) == SET) 1492 if (GET_CODE (body) == SET)
1418 n_sets = 1; 1493 n_sets = 1;
1419 else if (GET_CODE (body) == PARALLEL) 1494 else if (GET_CODE (body) == PARALLEL)
1420 { 1495 {
1421 int i;
1422 if (GET_CODE (XVECEXP (body, 0, 0)) == SET) 1496 if (GET_CODE (XVECEXP (body, 0, 0)) == SET)
1423 { 1497 {
1424 /* Multiple output operands, or 1 output plus some clobbers: 1498 /* Multiple output operands, or 1 output plus some clobbers:
1425 body is 1499 body is
1426 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ 1500 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1471 /* Assuming BODY is an insn body that uses ASM_OPERANDS, 1545 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1472 copy its operands (both input and output) into the vector OPERANDS, 1546 copy its operands (both input and output) into the vector OPERANDS,
1473 the locations of the operands within the insn into the vector OPERAND_LOCS, 1547 the locations of the operands within the insn into the vector OPERAND_LOCS,
1474 and the constraints for the operands into CONSTRAINTS. 1548 and the constraints for the operands into CONSTRAINTS.
1475 Write the modes of the operands into MODES. 1549 Write the modes of the operands into MODES.
1550 Write the location info into LOC.
1476 Return the assembler-template. 1551 Return the assembler-template.
1477 1552 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1478 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, 1553 return the basic assembly string.
1554
1555 If LOC, MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1479 we don't store that info. */ 1556 we don't store that info. */
1480 1557
1481 const char * 1558 const char *
1482 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs, 1559 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
1483 const char **constraints, enum machine_mode *modes, 1560 const char **constraints, machine_mode *modes,
1484 location_t *loc) 1561 location_t *loc)
1485 { 1562 {
1486 int nbase = 0, n, i; 1563 int nbase = 0, n, i;
1487 rtx asmop; 1564 rtx asmop;
1488 1565
1534 if (modes) 1611 if (modes)
1535 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); 1612 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1536 } 1613 }
1537 nbase = i; 1614 nbase = i;
1538 } 1615 }
1616 else if (GET_CODE (asmop) == ASM_INPUT)
1617 {
1618 if (loc)
1619 *loc = ASM_INPUT_SOURCE_LOCATION (asmop);
1620 return XSTR (asmop, 0);
1621 }
1539 break; 1622 break;
1540 } 1623 }
1541 1624
1542 default: 1625 default:
1543 gcc_unreachable (); 1626 gcc_unreachable ();
1574 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop); 1657 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
1575 1658
1576 return ASM_OPERANDS_TEMPLATE (asmop); 1659 return ASM_OPERANDS_TEMPLATE (asmop);
1577 } 1660 }
1578 1661
1662 /* Parse inline assembly string STRING and determine which operands are
1663 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1664 to true if operand I is referenced.
1665
1666 This is intended to distinguish barrier-like asms such as:
1667
1668 asm ("" : "=m" (...));
1669
1670 from real references such as:
1671
1672 asm ("sw\t$0, %0" : "=m" (...)); */
1673
1674 void
1675 get_referenced_operands (const char *string, bool *used,
1676 unsigned int noperands)
1677 {
1678 memset (used, 0, sizeof (bool) * noperands);
1679 const char *p = string;
1680 while (*p)
1681 switch (*p)
1682 {
1683 case '%':
1684 p += 1;
1685 /* A letter followed by a digit indicates an operand number. */
1686 if (ISALPHA (p[0]) && ISDIGIT (p[1]))
1687 p += 1;
1688 if (ISDIGIT (*p))
1689 {
1690 char *endptr;
1691 unsigned long opnum = strtoul (p, &endptr, 10);
1692 if (endptr != p && opnum < noperands)
1693 used[opnum] = true;
1694 p = endptr;
1695 }
1696 else
1697 p += 1;
1698 break;
1699
1700 default:
1701 p++;
1702 break;
1703 }
1704 }
1705
1579 /* Check if an asm_operand matches its constraints. 1706 /* Check if an asm_operand matches its constraints.
1580 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */ 1707 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1581 1708
1582 int 1709 int
1583 asm_operand_ok (rtx op, const char *constraint, const char **constraints) 1710 asm_operand_ok (rtx op, const char *constraint, const char **constraints)
1584 { 1711 {
1585 int result = 0; 1712 int result = 0;
1586 #ifdef AUTO_INC_DEC
1587 bool incdec_ok = false; 1713 bool incdec_ok = false;
1588 #endif
1589 1714
1590 /* Use constrain_operands after reload. */ 1715 /* Use constrain_operands after reload. */
1591 gcc_assert (!reload_completed); 1716 gcc_assert (!reload_completed);
1592 1717
1593 /* Empty constraint string is the same as "X,...,X", i.e. X for as 1718 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1595 if (*constraint == '\0') 1720 if (*constraint == '\0')
1596 result = 1; 1721 result = 1;
1597 1722
1598 while (*constraint) 1723 while (*constraint)
1599 { 1724 {
1725 enum constraint_num cn;
1600 char c = *constraint; 1726 char c = *constraint;
1601 int len; 1727 int len;
1602 switch (c) 1728 switch (c)
1603 { 1729 {
1604 case ',': 1730 case ',':
1605 constraint++; 1731 constraint++;
1606 continue; 1732 continue;
1607 case '=':
1608 case '+':
1609 case '*':
1610 case '%':
1611 case '!':
1612 case '#':
1613 case '&':
1614 case '?':
1615 break;
1616 1733
1617 case '0': case '1': case '2': case '3': case '4': 1734 case '0': case '1': case '2': case '3': case '4':
1618 case '5': case '6': case '7': case '8': case '9': 1735 case '5': case '6': case '7': case '8': case '9':
1619 /* If caller provided constraints pointer, look up 1736 /* If caller provided constraints pointer, look up
1620 the maching constraint. Otherwise, our caller should have 1737 the matching constraint. Otherwise, our caller should have
1621 given us the proper matching constraint, but we can't 1738 given us the proper matching constraint, but we can't
1622 actually fail the check if they didn't. Indicate that 1739 actually fail the check if they didn't. Indicate that
1623 results are inconclusive. */ 1740 results are inconclusive. */
1624 if (constraints) 1741 if (constraints)
1625 { 1742 {
1639 if (! result) 1756 if (! result)
1640 result = -1; 1757 result = -1;
1641 } 1758 }
1642 continue; 1759 continue;
1643 1760
1644 case 'p': 1761 /* The rest of the compiler assumes that reloading the address
1645 if (address_operand (op, VOIDmode)) 1762 of a MEM into a register will make it fit an 'o' constraint.
1646 result = 1; 1763 That is, if it sees a MEM operand for an 'o' constraint,
1647 break; 1764 it assumes that (mem (base-reg)) will fit.
1648 1765
1649 case TARGET_MEM_CONSTRAINT: 1766 That assumption fails on targets that don't have offsettable
1650 case 'V': /* non-offsettable */ 1767 addresses at all. We therefore need to treat 'o' asm
1651 if (memory_operand (op, VOIDmode)) 1768 constraints as a special case and only accept operands that
1652 result = 1; 1769 are already offsettable, thus proving that at least one
1653 break; 1770 offsettable address exists. */
1654
1655 case 'o': /* offsettable */ 1771 case 'o': /* offsettable */
1656 if (offsettable_nonstrict_memref_p (op)) 1772 if (offsettable_nonstrict_memref_p (op))
1657 result = 1; 1773 result = 1;
1658 break; 1774 break;
1659 1775
1660 case '<':
1661 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1662 excepting those that expand_call created. Further, on some
1663 machines which do not have generalized auto inc/dec, an inc/dec
1664 is not a memory_operand.
1665
1666 Match any memory and hope things are resolved after reload. */
1667
1668 if (MEM_P (op)
1669 && (1
1670 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1671 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1672 result = 1;
1673 #ifdef AUTO_INC_DEC
1674 incdec_ok = true;
1675 #endif
1676 break;
1677
1678 case '>':
1679 if (MEM_P (op)
1680 && (1
1681 || GET_CODE (XEXP (op, 0)) == PRE_INC
1682 || GET_CODE (XEXP (op, 0)) == POST_INC))
1683 result = 1;
1684 #ifdef AUTO_INC_DEC
1685 incdec_ok = true;
1686 #endif
1687 break;
1688
1689 case 'E':
1690 case 'F':
1691 if (GET_CODE (op) == CONST_DOUBLE
1692 || (GET_CODE (op) == CONST_VECTOR
1693 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT))
1694 result = 1;
1695 break;
1696
1697 case 'G':
1698 if (GET_CODE (op) == CONST_DOUBLE
1699 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', constraint))
1700 result = 1;
1701 break;
1702 case 'H':
1703 if (GET_CODE (op) == CONST_DOUBLE
1704 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'H', constraint))
1705 result = 1;
1706 break;
1707
1708 case 's':
1709 if (CONST_INT_P (op)
1710 || (GET_CODE (op) == CONST_DOUBLE
1711 && GET_MODE (op) == VOIDmode))
1712 break;
1713 /* Fall through. */
1714
1715 case 'i':
1716 if (CONSTANT_P (op) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))
1717 result = 1;
1718 break;
1719
1720 case 'n':
1721 if (CONST_INT_P (op)
1722 || (GET_CODE (op) == CONST_DOUBLE
1723 && GET_MODE (op) == VOIDmode))
1724 result = 1;
1725 break;
1726
1727 case 'I':
1728 if (CONST_INT_P (op)
1729 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'I', constraint))
1730 result = 1;
1731 break;
1732 case 'J':
1733 if (CONST_INT_P (op)
1734 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'J', constraint))
1735 result = 1;
1736 break;
1737 case 'K':
1738 if (CONST_INT_P (op)
1739 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'K', constraint))
1740 result = 1;
1741 break;
1742 case 'L':
1743 if (CONST_INT_P (op)
1744 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'L', constraint))
1745 result = 1;
1746 break;
1747 case 'M':
1748 if (CONST_INT_P (op)
1749 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'M', constraint))
1750 result = 1;
1751 break;
1752 case 'N':
1753 if (CONST_INT_P (op)
1754 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'N', constraint))
1755 result = 1;
1756 break;
1757 case 'O':
1758 if (CONST_INT_P (op)
1759 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'O', constraint))
1760 result = 1;
1761 break;
1762 case 'P':
1763 if (CONST_INT_P (op)
1764 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'P', constraint))
1765 result = 1;
1766 break;
1767
1768 case 'X':
1769 result = 1;
1770 break;
1771
1772 case 'g': 1776 case 'g':
1773 if (general_operand (op, VOIDmode)) 1777 if (general_operand (op, VOIDmode))
1774 result = 1; 1778 result = 1;
1775 break; 1779 break;
1776 1780
1781 case '<':
1782 case '>':
1783 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1784 to exist, excepting those that expand_call created. Further,
1785 on some machines which do not have generalized auto inc/dec,
1786 an inc/dec is not a memory_operand.
1787
1788 Match any memory and hope things are resolved after reload. */
1789 incdec_ok = true;
1790 /* FALLTHRU */
1777 default: 1791 default:
1778 /* For all other letters, we first check for a register class, 1792 cn = lookup_constraint (constraint);
1779 otherwise it is an EXTRA_CONSTRAINT. */ 1793 switch (get_constraint_type (cn))
1780 if (REG_CLASS_FROM_CONSTRAINT (c, constraint) != NO_REGS)
1781 { 1794 {
1782 case 'r': 1795 case CT_REGISTER:
1783 if (GET_MODE (op) == BLKmode) 1796 if (!result
1784 break; 1797 && reg_class_for_constraint (cn) != NO_REGS
1785 if (register_operand (op, VOIDmode)) 1798 && GET_MODE (op) != BLKmode
1799 && register_operand (op, VOIDmode))
1786 result = 1; 1800 result = 1;
1801 break;
1802
1803 case CT_CONST_INT:
1804 if (!result
1805 && CONST_INT_P (op)
1806 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
1807 result = 1;
1808 break;
1809
1810 case CT_MEMORY:
1811 case CT_SPECIAL_MEMORY:
1812 /* Every memory operand can be reloaded to fit. */
1813 result = result || memory_operand (op, VOIDmode);
1814 break;
1815
1816 case CT_ADDRESS:
1817 /* Every address operand can be reloaded to fit. */
1818 result = result || address_operand (op, VOIDmode);
1819 break;
1820
1821 case CT_FIXED_FORM:
1822 result = result || constraint_satisfied_p (op, cn);
1823 break;
1787 } 1824 }
1788 #ifdef EXTRA_CONSTRAINT_STR
1789 else if (EXTRA_MEMORY_CONSTRAINT (c, constraint))
1790 /* Every memory operand can be reloaded to fit. */
1791 result = result || memory_operand (op, VOIDmode);
1792 else if (EXTRA_ADDRESS_CONSTRAINT (c, constraint))
1793 /* Every address operand can be reloaded to fit. */
1794 result = result || address_operand (op, VOIDmode);
1795 else if (EXTRA_CONSTRAINT_STR (op, c, constraint))
1796 result = 1;
1797 #endif
1798 break; 1825 break;
1799 } 1826 }
1800 len = CONSTRAINT_LEN (c, constraint); 1827 len = CONSTRAINT_LEN (c, constraint);
1801 do 1828 do
1802 constraint++; 1829 constraint++;
1803 while (--len && *constraint); 1830 while (--len && *constraint);
1804 if (len) 1831 if (len)
1805 return 0; 1832 return 0;
1806 } 1833 }
1807 1834
1808 #ifdef AUTO_INC_DEC
1809 /* For operands without < or > constraints reject side-effects. */ 1835 /* For operands without < or > constraints reject side-effects. */
1810 if (!incdec_ok && result && MEM_P (op)) 1836 if (AUTO_INC_DEC && !incdec_ok && result && MEM_P (op))
1811 switch (GET_CODE (XEXP (op, 0))) 1837 switch (GET_CODE (XEXP (op, 0)))
1812 { 1838 {
1813 case PRE_INC: 1839 case PRE_INC:
1814 case POST_INC: 1840 case POST_INC:
1815 case PRE_DEC: 1841 case PRE_DEC:
1818 case POST_MODIFY: 1844 case POST_MODIFY:
1819 return 0; 1845 return 0;
1820 default: 1846 default:
1821 break; 1847 break;
1822 } 1848 }
1823 #endif
1824 1849
1825 return result; 1850 return result;
1826 } 1851 }
1827 1852
1828 /* Given an rtx *P, if it is a sum containing an integer constant term, 1853 /* Given an rtx *P, if it is a sum containing an integer constant term,
1910 1935
1911 If STRICTP is nonzero, we require a strictly valid address, 1936 If STRICTP is nonzero, we require a strictly valid address,
1912 for the sake of use in reload.c. */ 1937 for the sake of use in reload.c. */
1913 1938
1914 int 1939 int
1915 offsettable_address_addr_space_p (int strictp, enum machine_mode mode, rtx y, 1940 offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y,
1916 addr_space_t as) 1941 addr_space_t as)
1917 { 1942 {
1918 enum rtx_code ycode = GET_CODE (y); 1943 enum rtx_code ycode = GET_CODE (y);
1919 rtx z; 1944 rtx z;
1920 rtx y1 = y; 1945 rtx y1 = y;
1921 rtx *y2; 1946 rtx *y2;
1922 int (*addressp) (enum machine_mode, rtx, addr_space_t) = 1947 int (*addressp) (machine_mode, rtx, addr_space_t) =
1923 (strictp ? strict_memory_address_addr_space_p 1948 (strictp ? strict_memory_address_addr_space_p
1924 : memory_address_addr_space_p); 1949 : memory_address_addr_space_p);
1925 unsigned int mode_sz = GET_MODE_SIZE (mode); 1950 unsigned int mode_sz = GET_MODE_SIZE (mode);
1926 1951
1927 if (CONSTANT_ADDRESS_P (y)) 1952 if (CONSTANT_ADDRESS_P (y))
1928 return 1; 1953 return 1;
1929 1954
1930 /* Adjusting an offsettable address involves changing to a narrower mode. 1955 /* Adjusting an offsettable address involves changing to a narrower mode.
1931 Make sure that's OK. */ 1956 Make sure that's OK. */
1932 1957
1933 if (mode_dependent_address_p (y)) 1958 if (mode_dependent_address_p (y, as))
1934 return 0; 1959 return 0;
1960
1961 machine_mode address_mode = GET_MODE (y);
1962 if (address_mode == VOIDmode)
1963 address_mode = targetm.addr_space.address_mode (as);
1964 #ifdef POINTERS_EXTEND_UNSIGNED
1965 machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
1966 #endif
1935 1967
1936 /* ??? How much offset does an offsettable BLKmode reference need? 1968 /* ??? How much offset does an offsettable BLKmode reference need?
1937 Clearly that depends on the situation in which it's being used. 1969 Clearly that depends on the situation in which it's being used.
1938 However, the current situation in which we test 0xffffffff is 1970 However, the current situation in which we test 0xffffffff is
1939 less than ideal. Caveat user. */ 1971 less than ideal. Caveat user. */
1946 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) 1978 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1947 { 1979 {
1948 int good; 1980 int good;
1949 1981
1950 y1 = *y2; 1982 y1 = *y2;
1951 *y2 = plus_constant (*y2, mode_sz - 1); 1983 *y2 = plus_constant (address_mode, *y2, mode_sz - 1);
1952 /* Use QImode because an odd displacement may be automatically invalid 1984 /* Use QImode because an odd displacement may be automatically invalid
1953 for any wider mode. But it should be valid for a single byte. */ 1985 for any wider mode. But it should be valid for a single byte. */
1954 good = (*addressp) (QImode, y, as); 1986 good = (*addressp) (QImode, y, as);
1955 1987
1956 /* In any case, restore old contents of memory. */ 1988 /* In any case, restore old contents of memory. */
1967 valid addresses then so is Y+d for all 0<d<c. adjust_address will 1999 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1968 go inside a LO_SUM here, so we do so as well. */ 2000 go inside a LO_SUM here, so we do so as well. */
1969 if (GET_CODE (y) == LO_SUM 2001 if (GET_CODE (y) == LO_SUM
1970 && mode != BLKmode 2002 && mode != BLKmode
1971 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT) 2003 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
1972 z = gen_rtx_LO_SUM (GET_MODE (y), XEXP (y, 0), 2004 z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0),
1973 plus_constant (XEXP (y, 1), mode_sz - 1)); 2005 plus_constant (address_mode, XEXP (y, 1),
2006 mode_sz - 1));
2007 #ifdef POINTERS_EXTEND_UNSIGNED
2008 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2009 else if (POINTERS_EXTEND_UNSIGNED > 0
2010 && GET_CODE (y) == ZERO_EXTEND
2011 && GET_MODE (XEXP (y, 0)) == pointer_mode)
2012 z = gen_rtx_ZERO_EXTEND (address_mode,
2013 plus_constant (pointer_mode, XEXP (y, 0),
2014 mode_sz - 1));
2015 #endif
1974 else 2016 else
1975 z = plus_constant (y, mode_sz - 1); 2017 z = plus_constant (address_mode, y, mode_sz - 1);
1976 2018
1977 /* Use QImode because an odd displacement may be automatically invalid 2019 /* Use QImode because an odd displacement may be automatically invalid
1978 for any wider mode. But it should be valid for a single byte. */ 2020 for any wider mode. But it should be valid for a single byte. */
1979 return (*addressp) (QImode, z, as); 2021 return (*addressp) (QImode, z, as);
1980 } 2022 }
1981 2023
1982 /* Return 1 if ADDR is an address-expression whose effect depends 2024 /* Return 1 if ADDR is an address-expression whose effect depends
1983 on the mode of the memory reference it is used in. 2025 on the mode of the memory reference it is used in.
1984 2026
2027 ADDRSPACE is the address space associated with the address.
2028
1985 Autoincrement addressing is a typical example of mode-dependence 2029 Autoincrement addressing is a typical example of mode-dependence
1986 because the amount of the increment depends on the mode. */ 2030 because the amount of the increment depends on the mode. */
1987 2031
1988 bool 2032 bool
1989 mode_dependent_address_p (rtx addr) 2033 mode_dependent_address_p (rtx addr, addr_space_t addrspace)
1990 { 2034 {
1991 /* Auto-increment addressing with anything other than post_modify 2035 /* Auto-increment addressing with anything other than post_modify
1992 or pre_modify always introduces a mode dependency. Catch such 2036 or pre_modify always introduces a mode dependency. Catch such
1993 cases now instead of deferring to the target. */ 2037 cases now instead of deferring to the target. */
1994 if (GET_CODE (addr) == PRE_INC 2038 if (GET_CODE (addr) == PRE_INC
1995 || GET_CODE (addr) == POST_INC 2039 || GET_CODE (addr) == POST_INC
1996 || GET_CODE (addr) == PRE_DEC 2040 || GET_CODE (addr) == PRE_DEC
1997 || GET_CODE (addr) == POST_DEC) 2041 || GET_CODE (addr) == POST_DEC)
1998 return true; 2042 return true;
1999 2043
2000 return targetm.mode_dependent_address_p (addr); 2044 return targetm.mode_dependent_address_p (addr, addrspace);
2001 } 2045 }
2002 2046
2047 /* Return true if boolean attribute ATTR is supported. */
2048
2049 static bool
2050 have_bool_attr (bool_attr attr)
2051 {
2052 switch (attr)
2053 {
2054 case BA_ENABLED:
2055 return HAVE_ATTR_enabled;
2056 case BA_PREFERRED_FOR_SIZE:
2057 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_size;
2058 case BA_PREFERRED_FOR_SPEED:
2059 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_speed;
2060 }
2061 gcc_unreachable ();
2062 }
2063
2064 /* Return the value of ATTR for instruction INSN. */
2065
2066 static bool
2067 get_bool_attr (rtx_insn *insn, bool_attr attr)
2068 {
2069 switch (attr)
2070 {
2071 case BA_ENABLED:
2072 return get_attr_enabled (insn);
2073 case BA_PREFERRED_FOR_SIZE:
2074 return get_attr_enabled (insn) && get_attr_preferred_for_size (insn);
2075 case BA_PREFERRED_FOR_SPEED:
2076 return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn);
2077 }
2078 gcc_unreachable ();
2079 }
2080
2081 /* Like get_bool_attr_mask, but don't use the cache. */
2082
2083 static alternative_mask
2084 get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr)
2085 {
2086 /* Temporarily install enough information for get_attr_<foo> to assume
2087 that the insn operands are already cached. As above, the attribute
2088 mustn't depend on the values of operands, so we don't provide their
2089 real values here. */
2090 rtx_insn *old_insn = recog_data.insn;
2091 int old_alternative = which_alternative;
2092
2093 recog_data.insn = insn;
2094 alternative_mask mask = ALL_ALTERNATIVES;
2095 int n_alternatives = insn_data[INSN_CODE (insn)].n_alternatives;
2096 for (int i = 0; i < n_alternatives; i++)
2097 {
2098 which_alternative = i;
2099 if (!get_bool_attr (insn, attr))
2100 mask &= ~ALTERNATIVE_BIT (i);
2101 }
2102
2103 recog_data.insn = old_insn;
2104 which_alternative = old_alternative;
2105 return mask;
2106 }
2107
2108 /* Return the mask of operand alternatives that are allowed for INSN
2109 by boolean attribute ATTR. This mask depends only on INSN and on
2110 the current target; it does not depend on things like the values of
2111 operands. */
2112
2113 static alternative_mask
2114 get_bool_attr_mask (rtx_insn *insn, bool_attr attr)
2115 {
2116 /* Quick exit for asms and for targets that don't use these attributes. */
2117 int code = INSN_CODE (insn);
2118 if (code < 0 || !have_bool_attr (attr))
2119 return ALL_ALTERNATIVES;
2120
2121 /* Calling get_attr_<foo> can be expensive, so cache the mask
2122 for speed. */
2123 if (!this_target_recog->x_bool_attr_masks[code][attr])
2124 this_target_recog->x_bool_attr_masks[code][attr]
2125 = get_bool_attr_mask_uncached (insn, attr);
2126 return this_target_recog->x_bool_attr_masks[code][attr];
2127 }
2128
2129 /* Return the set of alternatives of INSN that are allowed by the current
2130 target. */
2131
2132 alternative_mask
2133 get_enabled_alternatives (rtx_insn *insn)
2134 {
2135 return get_bool_attr_mask (insn, BA_ENABLED);
2136 }
2137
2138 /* Return the set of alternatives of INSN that are allowed by the current
2139 target and are preferred for the current size/speed optimization
2140 choice. */
2141
2142 alternative_mask
2143 get_preferred_alternatives (rtx_insn *insn)
2144 {
2145 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
2146 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2147 else
2148 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2149 }
2150
2151 /* Return the set of alternatives of INSN that are allowed by the current
2152 target and are preferred for the size/speed optimization choice
2153 associated with BB. Passing a separate BB is useful if INSN has not
2154 been emitted yet or if we are considering moving it to a different
2155 block. */
2156
2157 alternative_mask
2158 get_preferred_alternatives (rtx_insn *insn, basic_block bb)
2159 {
2160 if (optimize_bb_for_speed_p (bb))
2161 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2162 else
2163 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2164 }
2165
2166 /* Assert that the cached boolean attributes for INSN are still accurate.
2167 The backend is required to define these attributes in a way that only
2168 depends on the current target (rather than operands, compiler phase,
2169 etc.). */
2170
2171 bool
2172 check_bool_attrs (rtx_insn *insn)
2173 {
2174 int code = INSN_CODE (insn);
2175 if (code >= 0)
2176 for (int i = 0; i <= BA_LAST; ++i)
2177 {
2178 enum bool_attr attr = (enum bool_attr) i;
2179 if (this_target_recog->x_bool_attr_masks[code][attr])
2180 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr]
2181 == get_bool_attr_mask_uncached (insn, attr));
2182 }
2183 return true;
2184 }
2185
2003 /* Like extract_insn, but save insn extracted and don't extract again, when 2186 /* Like extract_insn, but save insn extracted and don't extract again, when
2004 called again for the same insn expecting that recog_data still contain the 2187 called again for the same insn expecting that recog_data still contain the
2005 valid information. This is used primary by gen_attr infrastructure that 2188 valid information. This is used primary by gen_attr infrastructure that
2006 often does extract insn again and again. */ 2189 often does extract insn again and again. */
2007 void 2190 void
2008 extract_insn_cached (rtx insn) 2191 extract_insn_cached (rtx_insn *insn)
2009 { 2192 {
2010 if (recog_data.insn == insn && INSN_CODE (insn) >= 0) 2193 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2011 return; 2194 return;
2012 extract_insn (insn); 2195 extract_insn (insn);
2013 recog_data.insn = insn; 2196 recog_data.insn = insn;
2014 } 2197 }
2015 2198
2199 /* Do uncached extract_insn, constrain_operands and complain about failures.
2200 This should be used when extracting a pre-existing constrained instruction
2201 if the caller wants to know which alternative was chosen. */
2202 void
2203 extract_constrain_insn (rtx_insn *insn)
2204 {
2205 extract_insn (insn);
2206 if (!constrain_operands (reload_completed, get_enabled_alternatives (insn)))
2207 fatal_insn_not_found (insn);
2208 }
2209
2016 /* Do cached extract_insn, constrain_operands and complain about failures. 2210 /* Do cached extract_insn, constrain_operands and complain about failures.
2017 Used by insn_attrtab. */ 2211 Used by insn_attrtab. */
2018 void 2212 void
2019 extract_constrain_insn_cached (rtx insn) 2213 extract_constrain_insn_cached (rtx_insn *insn)
2020 { 2214 {
2021 extract_insn_cached (insn); 2215 extract_insn_cached (insn);
2022 if (which_alternative == -1 2216 if (which_alternative == -1
2023 && !constrain_operands (reload_completed)) 2217 && !constrain_operands (reload_completed,
2218 get_enabled_alternatives (insn)))
2024 fatal_insn_not_found (insn); 2219 fatal_insn_not_found (insn);
2025 } 2220 }
2026 2221
2027 /* Do cached constrain_operands and complain about failures. */ 2222 /* Do cached constrain_operands on INSN and complain about failures. */
2028 int 2223 int
2029 constrain_operands_cached (int strict) 2224 constrain_operands_cached (rtx_insn *insn, int strict)
2030 { 2225 {
2031 if (which_alternative == -1) 2226 if (which_alternative == -1)
2032 return constrain_operands (strict); 2227 return constrain_operands (strict, get_enabled_alternatives (insn));
2033 else 2228 else
2034 return 1; 2229 return 1;
2035 } 2230 }
2036 2231
2037 /* Analyze INSN and fill in recog_data. */ 2232 /* Analyze INSN and fill in recog_data. */
2038 2233
2039 void 2234 void
2040 extract_insn (rtx insn) 2235 extract_insn (rtx_insn *insn)
2041 { 2236 {
2042 int i; 2237 int i;
2043 int icode; 2238 int icode;
2044 int noperands; 2239 int noperands;
2045 rtx body = PATTERN (insn); 2240 rtx body = PATTERN (insn);
2065 else 2260 else
2066 goto normal_insn; 2261 goto normal_insn;
2067 case PARALLEL: 2262 case PARALLEL:
2068 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET 2263 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2069 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) 2264 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2070 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) 2265 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS
2266 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
2071 goto asm_insn; 2267 goto asm_insn;
2072 else 2268 else
2073 goto normal_insn; 2269 goto normal_insn;
2074 case ASM_OPERANDS: 2270 case ASM_OPERANDS:
2075 asm_insn: 2271 asm_insn:
2130 : recog_data.constraints[i][0] == '+' ? OP_INOUT 2326 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2131 : OP_IN); 2327 : OP_IN);
2132 2328
2133 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES); 2329 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
2134 2330
2135 if (INSN_CODE (insn) < 0)
2136 for (i = 0; i < recog_data.n_alternatives; i++)
2137 recog_data.alternative_enabled_p[i] = true;
2138 else
2139 {
2140 recog_data.insn = insn;
2141 for (i = 0; i < recog_data.n_alternatives; i++)
2142 {
2143 which_alternative = i;
2144 recog_data.alternative_enabled_p[i] = get_attr_enabled (insn);
2145 }
2146 }
2147
2148 recog_data.insn = NULL; 2331 recog_data.insn = NULL;
2149 which_alternative = -1; 2332 which_alternative = -1;
2150 } 2333 }
2151 2334
2152 /* After calling extract_insn, you can use this function to extract some 2335 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2153 information from the constraint strings into a more usable form. 2336 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2154 The collected data is stored in recog_op_alt. */ 2337 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2338 has N_OPERANDS entries. */
2339
2155 void 2340 void
2156 preprocess_constraints (void) 2341 preprocess_constraints (int n_operands, int n_alternatives,
2157 { 2342 const char **constraints,
2158 int i; 2343 operand_alternative *op_alt_base)
2159 2344 {
2160 for (i = 0; i < recog_data.n_operands; i++) 2345 for (int i = 0; i < n_operands; i++)
2161 memset (recog_op_alt[i], 0, (recog_data.n_alternatives
2162 * sizeof (struct operand_alternative)));
2163
2164 for (i = 0; i < recog_data.n_operands; i++)
2165 { 2346 {
2166 int j; 2347 int j;
2167 struct operand_alternative *op_alt; 2348 struct operand_alternative *op_alt;
2168 const char *p = recog_data.constraints[i]; 2349 const char *p = constraints[i];
2169 2350
2170 op_alt = recog_op_alt[i]; 2351 op_alt = op_alt_base;
2171 2352
2172 for (j = 0; j < recog_data.n_alternatives; j++) 2353 for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
2173 { 2354 {
2174 op_alt[j].cl = NO_REGS; 2355 op_alt[i].cl = NO_REGS;
2175 op_alt[j].constraint = p; 2356 op_alt[i].constraint = p;
2176 op_alt[j].matches = -1; 2357 op_alt[i].matches = -1;
2177 op_alt[j].matched = -1; 2358 op_alt[i].matched = -1;
2178
2179 if (!recog_data.alternative_enabled_p[j])
2180 {
2181 p = skip_alternative (p);
2182 continue;
2183 }
2184 2359
2185 if (*p == '\0' || *p == ',') 2360 if (*p == '\0' || *p == ',')
2186 { 2361 {
2187 op_alt[j].anything_ok = 1; 2362 op_alt[i].anything_ok = 1;
2188 continue; 2363 continue;
2189 } 2364 }
2190 2365
2191 for (;;) 2366 for (;;)
2192 { 2367 {
2201 break; 2376 break;
2202 } 2377 }
2203 2378
2204 switch (c) 2379 switch (c)
2205 { 2380 {
2206 case '=': case '+': case '*': case '%':
2207 case 'E': case 'F': case 'G': case 'H':
2208 case 's': case 'i': case 'n':
2209 case 'I': case 'J': case 'K': case 'L':
2210 case 'M': case 'N': case 'O': case 'P':
2211 /* These don't say anything we care about. */
2212 break;
2213
2214 case '?': 2381 case '?':
2215 op_alt[j].reject += 6; 2382 op_alt[i].reject += 6;
2216 break; 2383 break;
2217 case '!': 2384 case '!':
2218 op_alt[j].reject += 600; 2385 op_alt[i].reject += 600;
2219 break; 2386 break;
2220 case '&': 2387 case '&':
2221 op_alt[j].earlyclobber = 1; 2388 op_alt[i].earlyclobber = 1;
2222 break; 2389 break;
2223 2390
2224 case '0': case '1': case '2': case '3': case '4': 2391 case '0': case '1': case '2': case '3': case '4':
2225 case '5': case '6': case '7': case '8': case '9': 2392 case '5': case '6': case '7': case '8': case '9':
2226 { 2393 {
2227 char *end; 2394 char *end;
2228 op_alt[j].matches = strtoul (p, &end, 10); 2395 op_alt[i].matches = strtoul (p, &end, 10);
2229 recog_op_alt[op_alt[j].matches][j].matched = i; 2396 op_alt[op_alt[i].matches].matched = i;
2230 p = end; 2397 p = end;
2231 } 2398 }
2232 continue; 2399 continue;
2233 2400
2234 case TARGET_MEM_CONSTRAINT: 2401 case 'X':
2235 op_alt[j].memory_ok = 1; 2402 op_alt[i].anything_ok = 1;
2236 break; 2403 break;
2237 case '<': 2404
2238 op_alt[j].decmem_ok = 1; 2405 case 'g':
2406 op_alt[i].cl =
2407 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS];
2239 break; 2408 break;
2240 case '>':
2241 op_alt[j].incmem_ok = 1;
2242 break;
2243 case 'V':
2244 op_alt[j].nonoffmem_ok = 1;
2245 break;
2246 case 'o':
2247 op_alt[j].offmem_ok = 1;
2248 break;
2249 case 'X':
2250 op_alt[j].anything_ok = 1;
2251 break;
2252
2253 case 'p':
2254 op_alt[j].is_address = 1;
2255 op_alt[j].cl = reg_class_subunion[(int) op_alt[j].cl]
2256 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
2257 break;
2258
2259 case 'g':
2260 case 'r':
2261 op_alt[j].cl =
2262 reg_class_subunion[(int) op_alt[j].cl][(int) GENERAL_REGS];
2263 break;
2264 2409
2265 default: 2410 default:
2266 if (EXTRA_MEMORY_CONSTRAINT (c, p)) 2411 enum constraint_num cn = lookup_constraint (p);
2412 enum reg_class cl;
2413 switch (get_constraint_type (cn))
2267 { 2414 {
2268 op_alt[j].memory_ok = 1; 2415 case CT_REGISTER:
2416 cl = reg_class_for_constraint (cn);
2417 if (cl != NO_REGS)
2418 op_alt[i].cl = reg_class_subunion[op_alt[i].cl][cl];
2419 break;
2420
2421 case CT_CONST_INT:
2422 break;
2423
2424 case CT_MEMORY:
2425 case CT_SPECIAL_MEMORY:
2426 op_alt[i].memory_ok = 1;
2427 break;
2428
2429 case CT_ADDRESS:
2430 op_alt[i].is_address = 1;
2431 op_alt[i].cl
2432 = (reg_class_subunion
2433 [(int) op_alt[i].cl]
2434 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2435 ADDRESS, SCRATCH)]);
2436 break;
2437
2438 case CT_FIXED_FORM:
2269 break; 2439 break;
2270 } 2440 }
2271 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
2272 {
2273 op_alt[j].is_address = 1;
2274 op_alt[j].cl
2275 = (reg_class_subunion
2276 [(int) op_alt[j].cl]
2277 [(int) base_reg_class (VOIDmode, ADDRESS,
2278 SCRATCH)]);
2279 break;
2280 }
2281
2282 op_alt[j].cl
2283 = (reg_class_subunion
2284 [(int) op_alt[j].cl]
2285 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
2286 break; 2441 break;
2287 } 2442 }
2288 p += CONSTRAINT_LEN (c, p); 2443 p += CONSTRAINT_LEN (c, p);
2289 } 2444 }
2290 } 2445 }
2291 } 2446 }
2292 } 2447 }
2293 2448
2449 /* Return an array of operand_alternative instructions for
2450 instruction ICODE. */
2451
2452 const operand_alternative *
2453 preprocess_insn_constraints (unsigned int icode)
2454 {
2455 gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1));
2456 if (this_target_recog->x_op_alt[icode])
2457 return this_target_recog->x_op_alt[icode];
2458
2459 int n_operands = insn_data[icode].n_operands;
2460 if (n_operands == 0)
2461 return 0;
2462 /* Always provide at least one alternative so that which_op_alt ()
2463 works correctly. If the instruction has 0 alternatives (i.e. all
2464 constraint strings are empty) then each operand in this alternative
2465 will have anything_ok set. */
2466 int n_alternatives = MAX (insn_data[icode].n_alternatives, 1);
2467 int n_entries = n_operands * n_alternatives;
2468
2469 operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries);
2470 const char **constraints = XALLOCAVEC (const char *, n_operands);
2471
2472 for (int i = 0; i < n_operands; ++i)
2473 constraints[i] = insn_data[icode].operand[i].constraint;
2474 preprocess_constraints (n_operands, n_alternatives, constraints, op_alt);
2475
2476 this_target_recog->x_op_alt[icode] = op_alt;
2477 return op_alt;
2478 }
2479
2480 /* After calling extract_insn, you can use this function to extract some
2481 information from the constraint strings into a more usable form.
2482 The collected data is stored in recog_op_alt. */
2483
2484 void
2485 preprocess_constraints (rtx_insn *insn)
2486 {
2487 int icode = INSN_CODE (insn);
2488 if (icode >= 0)
2489 recog_op_alt = preprocess_insn_constraints (icode);
2490 else
2491 {
2492 int n_operands = recog_data.n_operands;
2493 int n_alternatives = recog_data.n_alternatives;
2494 int n_entries = n_operands * n_alternatives;
2495 memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative));
2496 preprocess_constraints (n_operands, n_alternatives,
2497 recog_data.constraints, asm_op_alt);
2498 recog_op_alt = asm_op_alt;
2499 }
2500 }
2501
2294 /* Check the operands of an insn against the insn's operand constraints 2502 /* Check the operands of an insn against the insn's operand constraints
2295 and return 1 if they are valid. 2503 and return 1 if they match any of the alternatives in ALTERNATIVES.
2504
2296 The information about the insn's operands, constraints, operand modes 2505 The information about the insn's operands, constraints, operand modes
2297 etc. is obtained from the global variables set up by extract_insn. 2506 etc. is obtained from the global variables set up by extract_insn.
2298 2507
2299 WHICH_ALTERNATIVE is set to a number which indicates which 2508 WHICH_ALTERNATIVE is set to a number which indicates which
2300 alternative of constraints was matched: 0 for the first alternative, 2509 alternative of constraints was matched: 0 for the first alternative,
2322 { 2531 {
2323 int this_op, other; 2532 int this_op, other;
2324 }; 2533 };
2325 2534
2326 int 2535 int
2327 constrain_operands (int strict) 2536 constrain_operands (int strict, alternative_mask alternatives)
2328 { 2537 {
2329 const char *constraints[MAX_RECOG_OPERANDS]; 2538 const char *constraints[MAX_RECOG_OPERANDS];
2330 int matching_operands[MAX_RECOG_OPERANDS]; 2539 int matching_operands[MAX_RECOG_OPERANDS];
2331 int earlyclobber[MAX_RECOG_OPERANDS]; 2540 int earlyclobber[MAX_RECOG_OPERANDS];
2332 int c; 2541 int c;
2349 int seen_earlyclobber_at = -1; 2558 int seen_earlyclobber_at = -1;
2350 int opno; 2559 int opno;
2351 int lose = 0; 2560 int lose = 0;
2352 funny_match_index = 0; 2561 funny_match_index = 0;
2353 2562
2354 if (!recog_data.alternative_enabled_p[which_alternative]) 2563 if (!TEST_BIT (alternatives, which_alternative))
2355 { 2564 {
2356 int i; 2565 int i;
2357 2566
2358 for (i = 0; i < recog_data.n_operands; i++) 2567 for (i = 0; i < recog_data.n_operands; i++)
2359 constraints[i] = skip_alternative (constraints[i]); 2568 constraints[i] = skip_alternative (constraints[i]);
2363 } 2572 }
2364 2573
2365 for (opno = 0; opno < recog_data.n_operands; opno++) 2574 for (opno = 0; opno < recog_data.n_operands; opno++)
2366 { 2575 {
2367 rtx op = recog_data.operand[opno]; 2576 rtx op = recog_data.operand[opno];
2368 enum machine_mode mode = GET_MODE (op); 2577 machine_mode mode = GET_MODE (op);
2369 const char *p = constraints[opno]; 2578 const char *p = constraints[opno];
2370 int offset = 0; 2579 int offset = 0;
2371 int win = 0; 2580 int win = 0;
2372 int val; 2581 int val;
2373 int len; 2582 int len;
2401 case '\0': 2610 case '\0':
2402 len = 0; 2611 len = 0;
2403 break; 2612 break;
2404 case ',': 2613 case ',':
2405 c = '\0'; 2614 c = '\0';
2406 break;
2407
2408 case '?': case '!': case '*': case '%':
2409 case '=': case '+':
2410 break; 2615 break;
2411 2616
2412 case '#': 2617 case '#':
2413 /* Ignore rest of this alternative as far as 2618 /* Ignore rest of this alternative as far as
2414 constraint checking is concerned. */ 2619 constraint checking is concerned. */
2506 } 2711 }
2507 else if (strict < 0 || general_operand (op, mode)) 2712 else if (strict < 0 || general_operand (op, mode))
2508 win = 1; 2713 win = 1;
2509 break; 2714 break;
2510 2715
2511 case 'X':
2512 /* This is used for a MATCH_SCRATCH in the cases when
2513 we don't actually need anything. So anything goes
2514 any time. */
2515 win = 1;
2516 break;
2517
2518 case TARGET_MEM_CONSTRAINT:
2519 /* Memory operands must be valid, to the extent
2520 required by STRICT. */
2521 if (MEM_P (op))
2522 {
2523 if (strict > 0
2524 && !strict_memory_address_addr_space_p
2525 (GET_MODE (op), XEXP (op, 0),
2526 MEM_ADDR_SPACE (op)))
2527 break;
2528 if (strict == 0
2529 && !memory_address_addr_space_p
2530 (GET_MODE (op), XEXP (op, 0),
2531 MEM_ADDR_SPACE (op)))
2532 break;
2533 win = 1;
2534 }
2535 /* Before reload, accept what reload can turn into mem. */
2536 else if (strict < 0 && CONSTANT_P (op))
2537 win = 1;
2538 /* During reload, accept a pseudo */
2539 else if (reload_in_progress && REG_P (op)
2540 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2541 win = 1;
2542 break;
2543
2544 case '<':
2545 if (MEM_P (op)
2546 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2547 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2548 win = 1;
2549 break;
2550
2551 case '>':
2552 if (MEM_P (op)
2553 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2554 || GET_CODE (XEXP (op, 0)) == POST_INC))
2555 win = 1;
2556 break;
2557
2558 case 'E':
2559 case 'F':
2560 if (GET_CODE (op) == CONST_DOUBLE
2561 || (GET_CODE (op) == CONST_VECTOR
2562 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT))
2563 win = 1;
2564 break;
2565
2566 case 'G':
2567 case 'H':
2568 if (GET_CODE (op) == CONST_DOUBLE
2569 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
2570 win = 1;
2571 break;
2572
2573 case 's':
2574 if (CONST_INT_P (op)
2575 || (GET_CODE (op) == CONST_DOUBLE
2576 && GET_MODE (op) == VOIDmode))
2577 break;
2578 case 'i':
2579 if (CONSTANT_P (op))
2580 win = 1;
2581 break;
2582
2583 case 'n':
2584 if (CONST_INT_P (op)
2585 || (GET_CODE (op) == CONST_DOUBLE
2586 && GET_MODE (op) == VOIDmode))
2587 win = 1;
2588 break;
2589
2590 case 'I':
2591 case 'J':
2592 case 'K':
2593 case 'L':
2594 case 'M':
2595 case 'N':
2596 case 'O':
2597 case 'P':
2598 if (CONST_INT_P (op)
2599 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
2600 win = 1;
2601 break;
2602
2603 case 'V':
2604 if (MEM_P (op)
2605 && ((strict > 0 && ! offsettable_memref_p (op))
2606 || (strict < 0
2607 && !(CONSTANT_P (op) || MEM_P (op)))
2608 || (reload_in_progress
2609 && !(REG_P (op)
2610 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2611 win = 1;
2612 break;
2613
2614 case 'o':
2615 if ((strict > 0 && offsettable_memref_p (op))
2616 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2617 /* Before reload, accept what reload can handle. */
2618 || (strict < 0
2619 && (CONSTANT_P (op) || MEM_P (op)))
2620 /* During reload, accept a pseudo */
2621 || (reload_in_progress && REG_P (op)
2622 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2623 win = 1;
2624 break;
2625
2626 default: 2716 default:
2627 { 2717 {
2628 enum reg_class cl; 2718 enum constraint_num cn = lookup_constraint (p);
2629 2719 enum reg_class cl = reg_class_for_constraint (cn);
2630 cl = (c == 'r'
2631 ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, p));
2632 if (cl != NO_REGS) 2720 if (cl != NO_REGS)
2633 { 2721 {
2634 if (strict < 0 2722 if (strict < 0
2635 || (strict == 0 2723 || (strict == 0
2636 && REG_P (op) 2724 && REG_P (op)
2638 || (strict == 0 && GET_CODE (op) == SCRATCH) 2726 || (strict == 0 && GET_CODE (op) == SCRATCH)
2639 || (REG_P (op) 2727 || (REG_P (op)
2640 && reg_fits_class_p (op, cl, offset, mode))) 2728 && reg_fits_class_p (op, cl, offset, mode)))
2641 win = 1; 2729 win = 1;
2642 } 2730 }
2643 #ifdef EXTRA_CONSTRAINT_STR 2731
2644 else if (EXTRA_CONSTRAINT_STR (op, c, p)) 2732 else if (constraint_satisfied_p (op, cn))
2645 win = 1; 2733 win = 1;
2646 2734
2647 else if (EXTRA_MEMORY_CONSTRAINT (c, p) 2735 else if (insn_extra_memory_constraint (cn)
2648 /* Every memory operand can be reloaded to fit. */ 2736 /* Every memory operand can be reloaded to fit. */
2649 && ((strict < 0 && MEM_P (op)) 2737 && ((strict < 0 && MEM_P (op))
2650 /* Before reload, accept what reload can turn 2738 /* Before reload, accept what reload can turn
2651 into mem. */ 2739 into a mem. */
2652 || (strict < 0 && CONSTANT_P (op)) 2740 || (strict < 0 && CONSTANT_P (op))
2741 /* Before reload, accept a pseudo,
2742 since LRA can turn it into a mem. */
2743 || (strict < 0 && targetm.lra_p () && REG_P (op)
2744 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2653 /* During reload, accept a pseudo */ 2745 /* During reload, accept a pseudo */
2654 || (reload_in_progress && REG_P (op) 2746 || (reload_in_progress && REG_P (op)
2655 && REGNO (op) >= FIRST_PSEUDO_REGISTER))) 2747 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
2656 win = 1; 2748 win = 1;
2657 else if (EXTRA_ADDRESS_CONSTRAINT (c, p) 2749 else if (insn_extra_address_constraint (cn)
2658 /* Every address operand can be reloaded to fit. */ 2750 /* Every address operand can be reloaded to fit. */
2659 && strict < 0) 2751 && strict < 0)
2660 win = 1; 2752 win = 1;
2661 #endif 2753 /* Cater to architectures like IA-64 that define extra memory
2754 constraints without using define_memory_constraint. */
2755 else if (reload_in_progress
2756 && REG_P (op)
2757 && REGNO (op) >= FIRST_PSEUDO_REGISTER
2758 && reg_renumber[REGNO (op)] < 0
2759 && reg_equiv_mem (REGNO (op)) != 0
2760 && constraint_satisfied_p
2761 (reg_equiv_mem (REGNO (op)), cn))
2762 win = 1;
2662 break; 2763 break;
2663 } 2764 }
2664 } 2765 }
2665 while (p += len, c); 2766 while (p += len, c);
2666 2767
2707 { 2808 {
2708 recog_data.operand[funny_match[funny_match_index].other] 2809 recog_data.operand[funny_match[funny_match_index].other]
2709 = recog_data.operand[funny_match[funny_match_index].this_op]; 2810 = recog_data.operand[funny_match[funny_match_index].this_op];
2710 } 2811 }
2711 2812
2712 #ifdef AUTO_INC_DEC
2713 /* For operands without < or > constraints reject side-effects. */ 2813 /* For operands without < or > constraints reject side-effects. */
2714 if (recog_data.is_asm) 2814 if (AUTO_INC_DEC && recog_data.is_asm)
2715 { 2815 {
2716 for (opno = 0; opno < recog_data.n_operands; opno++) 2816 for (opno = 0; opno < recog_data.n_operands; opno++)
2717 if (MEM_P (recog_data.operand[opno])) 2817 if (MEM_P (recog_data.operand[opno]))
2718 switch (GET_CODE (XEXP (recog_data.operand[opno], 0))) 2818 switch (GET_CODE (XEXP (recog_data.operand[opno], 0)))
2719 { 2819 {
2730 break; 2830 break;
2731 default: 2831 default:
2732 break; 2832 break;
2733 } 2833 }
2734 } 2834 }
2735 #endif 2835
2736 return 1; 2836 return 1;
2737 } 2837 }
2738 } 2838 }
2739 2839
2740 which_alternative++; 2840 which_alternative++;
2743 2843
2744 which_alternative = -1; 2844 which_alternative = -1;
2745 /* If we are about to reject this, but we are not to test strictly, 2845 /* If we are about to reject this, but we are not to test strictly,
2746 try a very loose test. Only return failure if it fails also. */ 2846 try a very loose test. Only return failure if it fails also. */
2747 if (strict == 0) 2847 if (strict == 0)
2748 return constrain_operands (-1); 2848 return constrain_operands (-1, alternatives);
2749 else 2849 else
2750 return 0; 2850 return 0;
2751 } 2851 }
2752 2852
2753 /* Return true iff OPERAND (assumed to be a REG rtx) 2853 /* Return true iff OPERAND (assumed to be a REG rtx)
2755 and changed to mode MODE. 2855 and changed to mode MODE.
2756 If REG occupies multiple hard regs, all of them must be in CLASS. */ 2856 If REG occupies multiple hard regs, all of them must be in CLASS. */
2757 2857
2758 bool 2858 bool
2759 reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset, 2859 reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset,
2760 enum machine_mode mode) 2860 machine_mode mode)
2761 { 2861 {
2762 int regno = REGNO (operand); 2862 unsigned int regno = REGNO (operand);
2763 2863
2764 if (cl == NO_REGS) 2864 if (cl == NO_REGS)
2765 return false; 2865 return false;
2766 2866
2867 /* Regno must not be a pseudo register. Offset may be negative. */
2767 return (HARD_REGISTER_NUM_P (regno) 2868 return (HARD_REGISTER_NUM_P (regno)
2768 && in_hard_reg_set_p (reg_class_contents[(int) cl], 2869 && HARD_REGISTER_NUM_P (regno + offset)
2769 mode, regno + offset)); 2870 && in_hard_reg_set_p (reg_class_contents[(int) cl], mode,
2871 regno + offset));
2770 } 2872 }
2771 2873
2772 /* Split single instruction. Helper function for split_all_insns and 2874 /* Split single instruction. Helper function for split_all_insns and
2773 split_all_insns_noflow. Return last insn in the sequence if successful, 2875 split_all_insns_noflow. Return last insn in the sequence if successful,
2774 or NULL if unsuccessful. */ 2876 or NULL if unsuccessful. */
2775 2877
2776 static rtx 2878 static rtx_insn *
2777 split_insn (rtx insn) 2879 split_insn (rtx_insn *insn)
2778 { 2880 {
2779 /* Split insns here to get max fine-grain parallelism. */ 2881 /* Split insns here to get max fine-grain parallelism. */
2780 rtx first = PREV_INSN (insn); 2882 rtx_insn *first = PREV_INSN (insn);
2781 rtx last = try_split (PATTERN (insn), insn, 1); 2883 rtx_insn *last = try_split (PATTERN (insn), insn, 1);
2782 rtx insn_set, last_set, note; 2884 rtx insn_set, last_set, note;
2783 2885
2784 if (last == insn) 2886 if (last == insn)
2785 return NULL_RTX; 2887 return NULL;
2786 2888
2787 /* If the original instruction was a single set that was known to be 2889 /* If the original instruction was a single set that was known to be
2788 equivalent to a constant, see if we can say the same about the last 2890 equivalent to a constant, see if we can say the same about the last
2789 instruction in the split sequence. The two instructions must set 2891 instruction in the split sequence. The two instructions must set
2790 the same destination. */ 2892 the same destination. */
2796 { 2898 {
2797 note = find_reg_equal_equiv_note (insn); 2899 note = find_reg_equal_equiv_note (insn);
2798 if (note && CONSTANT_P (XEXP (note, 0))) 2900 if (note && CONSTANT_P (XEXP (note, 0)))
2799 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0)); 2901 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0));
2800 else if (CONSTANT_P (SET_SRC (insn_set))) 2902 else if (CONSTANT_P (SET_SRC (insn_set)))
2801 set_unique_reg_note (last, REG_EQUAL, SET_SRC (insn_set)); 2903 set_unique_reg_note (last, REG_EQUAL,
2904 copy_rtx (SET_SRC (insn_set)));
2802 } 2905 }
2803 } 2906 }
2804 2907
2805 /* try_split returns the NOTE that INSN became. */ 2908 /* try_split returns the NOTE that INSN became. */
2806 SET_INSN_DELETED (insn); 2909 SET_INSN_DELETED (insn);
2826 /* Split all insns in the function. If UPD_LIFE, update life info after. */ 2929 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2827 2930
2828 void 2931 void
2829 split_all_insns (void) 2932 split_all_insns (void)
2830 { 2933 {
2831 sbitmap blocks;
2832 bool changed; 2934 bool changed;
2833 basic_block bb; 2935 basic_block bb;
2834 2936
2835 blocks = sbitmap_alloc (last_basic_block); 2937 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
2836 sbitmap_zero (blocks); 2938 bitmap_clear (blocks);
2837 changed = false; 2939 changed = false;
2838 2940
2839 FOR_EACH_BB_REVERSE (bb) 2941 FOR_EACH_BB_REVERSE_FN (bb, cfun)
2840 { 2942 {
2841 rtx insn, next; 2943 rtx_insn *insn, *next;
2842 bool finish = false; 2944 bool finish = false;
2843 2945
2844 rtl_profile_for_bb (bb); 2946 rtl_profile_for_bb (bb);
2845 for (insn = BB_HEAD (bb); !finish ; insn = next) 2947 for (insn = BB_HEAD (bb); !finish ; insn = next)
2846 { 2948 {
2867 } 2969 }
2868 else 2970 else
2869 { 2971 {
2870 if (split_insn (insn)) 2972 if (split_insn (insn))
2871 { 2973 {
2872 SET_BIT (blocks, bb->index); 2974 bitmap_set_bit (blocks, bb->index);
2873 changed = true; 2975 changed = true;
2874 } 2976 }
2875 } 2977 }
2876 } 2978 }
2877 } 2979 }
2879 2981
2880 default_rtl_profile (); 2982 default_rtl_profile ();
2881 if (changed) 2983 if (changed)
2882 find_many_sub_basic_blocks (blocks); 2984 find_many_sub_basic_blocks (blocks);
2883 2985
2884 #ifdef ENABLE_CHECKING 2986 checking_verify_flow_info ();
2885 verify_flow_info ();
2886 #endif
2887
2888 sbitmap_free (blocks);
2889 } 2987 }
2890 2988
2891 /* Same as split_all_insns, but do not expect CFG to be available. 2989 /* Same as split_all_insns, but do not expect CFG to be available.
2892 Used by machine dependent reorg passes. */ 2990 Used by machine dependent reorg passes. */
2893 2991
2894 unsigned int 2992 unsigned int
2895 split_all_insns_noflow (void) 2993 split_all_insns_noflow (void)
2896 { 2994 {
2897 rtx next, insn; 2995 rtx_insn *next, *insn;
2898 2996
2899 for (insn = get_insns (); insn; insn = next) 2997 for (insn = get_insns (); insn; insn = next)
2900 { 2998 {
2901 next = NEXT_INSN (insn); 2999 next = NEXT_INSN (insn);
2902 if (INSN_P (insn)) 3000 if (INSN_P (insn))
2922 } 3020 }
2923 } 3021 }
2924 return 0; 3022 return 0;
2925 } 3023 }
2926 3024
2927 #ifdef HAVE_peephole2
2928 struct peep2_insn_data 3025 struct peep2_insn_data
2929 { 3026 {
2930 rtx insn; 3027 rtx_insn *insn;
2931 regset live_before; 3028 regset live_before;
2932 }; 3029 };
2933 3030
2934 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1]; 3031 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
2935 static int peep2_current; 3032 static int peep2_current;
2938 static bool peep2_do_cleanup_cfg; 3035 static bool peep2_do_cleanup_cfg;
2939 3036
2940 /* The number of instructions available to match a peep2. */ 3037 /* The number of instructions available to match a peep2. */
2941 int peep2_current_count; 3038 int peep2_current_count;
2942 3039
2943 /* A non-insn marker indicating the last insn of the block. 3040 /* A marker indicating the last insn of the block. The live_before regset
2944 The live_before regset for this element is correct, indicating 3041 for this element is correct, indicating DF_LIVE_OUT for the block. */
2945 DF_LIVE_OUT for the block. */ 3042 #define PEEP2_EOB invalid_insn_rtx
2946 #define PEEP2_EOB pc_rtx
2947 3043
2948 /* Wrap N to fit into the peep2_insn_data buffer. */ 3044 /* Wrap N to fit into the peep2_insn_data buffer. */
2949 3045
2950 static int 3046 static int
2951 peep2_buf_position (int n) 3047 peep2_buf_position (int n)
2957 3053
2958 /* Return the Nth non-note insn after `current', or return NULL_RTX if it 3054 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2959 does not exist. Used by the recognizer to find the next insn to match 3055 does not exist. Used by the recognizer to find the next insn to match
2960 in a multi-insn pattern. */ 3056 in a multi-insn pattern. */
2961 3057
2962 rtx 3058 rtx_insn *
2963 peep2_next_insn (int n) 3059 peep2_next_insn (int n)
2964 { 3060 {
2965 gcc_assert (n <= peep2_current_count); 3061 gcc_assert (n <= peep2_current_count);
2966 3062
2967 n = peep2_buf_position (peep2_current + n); 3063 n = peep2_buf_position (peep2_current + n);
2987 /* Similarly for a REG. */ 3083 /* Similarly for a REG. */
2988 3084
2989 int 3085 int
2990 peep2_reg_dead_p (int ofs, rtx reg) 3086 peep2_reg_dead_p (int ofs, rtx reg)
2991 { 3087 {
2992 int regno, n;
2993
2994 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); 3088 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
2995 3089
2996 ofs = peep2_buf_position (peep2_current + ofs); 3090 ofs = peep2_buf_position (peep2_current + ofs);
2997 3091
2998 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); 3092 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
2999 3093
3000 regno = REGNO (reg); 3094 unsigned int end_regno = END_REGNO (reg);
3001 n = hard_regno_nregs[regno][GET_MODE (reg)]; 3095 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
3002 while (--n >= 0) 3096 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno))
3003 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
3004 return 0; 3097 return 0;
3005 return 1; 3098 return 1;
3006 } 3099 }
3100
3101 /* Regno offset to be used in the register search. */
3102 static int search_ofs;
3007 3103
3008 /* Try to find a hard register of mode MODE, matching the register class in 3104 /* Try to find a hard register of mode MODE, matching the register class in
3009 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and 3105 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3010 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX, 3106 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3011 in which case the only condition is that the register must be available 3107 in which case the only condition is that the register must be available
3016 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is 3112 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3017 returned. */ 3113 returned. */
3018 3114
3019 rtx 3115 rtx
3020 peep2_find_free_register (int from, int to, const char *class_str, 3116 peep2_find_free_register (int from, int to, const char *class_str,
3021 enum machine_mode mode, HARD_REG_SET *reg_set) 3117 machine_mode mode, HARD_REG_SET *reg_set)
3022 { 3118 {
3023 static int search_ofs;
3024 enum reg_class cl; 3119 enum reg_class cl;
3025 HARD_REG_SET live; 3120 HARD_REG_SET live;
3121 df_ref def;
3026 int i; 3122 int i;
3027 3123
3028 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1); 3124 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
3029 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1); 3125 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
3030 3126
3034 gcc_assert (peep2_insn_data[from].insn != NULL_RTX); 3130 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3035 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); 3131 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3036 3132
3037 while (from != to) 3133 while (from != to)
3038 { 3134 {
3039 HARD_REG_SET this_live; 3135 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3136
3137 /* Don't use registers set or clobbered by the insn. */
3138 FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn)
3139 SET_HARD_REG_BIT (live, DF_REF_REGNO (def));
3040 3140
3041 from = peep2_buf_position (from + 1); 3141 from = peep2_buf_position (from + 1);
3042 gcc_assert (peep2_insn_data[from].insn != NULL_RTX); 3142 }
3043 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before); 3143
3044 IOR_HARD_REG_SET (live, this_live); 3144 cl = reg_class_for_constraint (lookup_constraint (class_str));
3045 }
3046
3047 cl = (class_str[0] == 'r' ? GENERAL_REGS
3048 : REG_CLASS_FROM_CONSTRAINT (class_str[0], class_str));
3049 3145
3050 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3146 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3051 { 3147 {
3052 int raw_regno, regno, success, j; 3148 int raw_regno, regno, success, j;
3053 3149
3059 regno = reg_alloc_order[raw_regno]; 3155 regno = reg_alloc_order[raw_regno];
3060 #else 3156 #else
3061 regno = raw_regno; 3157 regno = raw_regno;
3062 #endif 3158 #endif
3063 3159
3064 /* Don't allocate fixed registers. */ 3160 /* Can it support the mode we need? */
3065 if (fixed_regs[regno]) 3161 if (!targetm.hard_regno_mode_ok (regno, mode))
3066 continue; 3162 continue;
3067 /* Don't allocate global registers. */
3068 if (global_regs[regno])
3069 continue;
3070 /* Make sure the register is of the right class. */
3071 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno))
3072 continue;
3073 /* And can support the mode we need. */
3074 if (! HARD_REGNO_MODE_OK (regno, mode))
3075 continue;
3076 /* And that we don't create an extra save/restore. */
3077 if (! call_used_regs[regno] && ! df_regs_ever_live_p (regno))
3078 continue;
3079 if (! targetm.hard_regno_scratch_ok (regno))
3080 continue;
3081
3082 /* And we don't clobber traceback for noreturn functions. */
3083 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
3084 && (! reload_completed || frame_pointer_needed))
3085 continue;
3086 3163
3087 success = 1; 3164 success = 1;
3088 for (j = hard_regno_nregs[regno][mode] - 1; j >= 0; j--) 3165 for (j = 0; success && j < hard_regno_nregs (regno, mode); j++)
3089 { 3166 {
3167 /* Don't allocate fixed registers. */
3168 if (fixed_regs[regno + j])
3169 {
3170 success = 0;
3171 break;
3172 }
3173 /* Don't allocate global registers. */
3174 if (global_regs[regno + j])
3175 {
3176 success = 0;
3177 break;
3178 }
3179 /* Make sure the register is of the right class. */
3180 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j))
3181 {
3182 success = 0;
3183 break;
3184 }
3185 /* And that we don't create an extra save/restore. */
3186 if (! call_used_regs[regno + j] && ! df_regs_ever_live_p (regno + j))
3187 {
3188 success = 0;
3189 break;
3190 }
3191
3192 if (! targetm.hard_regno_scratch_ok (regno + j))
3193 {
3194 success = 0;
3195 break;
3196 }
3197
3198 /* And we don't clobber traceback for noreturn functions. */
3199 if ((regno + j == FRAME_POINTER_REGNUM
3200 || regno + j == HARD_FRAME_POINTER_REGNUM)
3201 && (! reload_completed || frame_pointer_needed))
3202 {
3203 success = 0;
3204 break;
3205 }
3206
3090 if (TEST_HARD_REG_BIT (*reg_set, regno + j) 3207 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3091 || TEST_HARD_REG_BIT (live, regno + j)) 3208 || TEST_HARD_REG_BIT (live, regno + j))
3092 { 3209 {
3093 success = 0; 3210 success = 0;
3094 break; 3211 break;
3095 } 3212 }
3096 } 3213 }
3214
3097 if (success) 3215 if (success)
3098 { 3216 {
3099 add_to_hard_reg_set (reg_set, mode, regno); 3217 add_to_hard_reg_set (reg_set, mode, regno);
3100 3218
3101 /* Start the next search with the next register. */ 3219 /* Start the next search with the next register. */
3119 { 3237 {
3120 int i; 3238 int i;
3121 3239
3122 /* Indicate that all slots except the last holds invalid data. */ 3240 /* Indicate that all slots except the last holds invalid data. */
3123 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i) 3241 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3124 peep2_insn_data[i].insn = NULL_RTX; 3242 peep2_insn_data[i].insn = NULL;
3125 peep2_current_count = 0; 3243 peep2_current_count = 0;
3126 3244
3127 /* Indicate that the last slot contains live_after data. */ 3245 /* Indicate that the last slot contains live_after data. */
3128 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB; 3246 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3129 peep2_current = MAX_INSNS_PER_PEEP2; 3247 peep2_current = MAX_INSNS_PER_PEEP2;
3134 /* While scanning basic block BB, we found a match of length MATCH_LEN, 3252 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3135 starting at INSN. Perform the replacement, removing the old insns and 3253 starting at INSN. Perform the replacement, removing the old insns and
3136 replacing them with ATTEMPT. Returns the last insn emitted, or NULL 3254 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3137 if the replacement is rejected. */ 3255 if the replacement is rejected. */
3138 3256
3139 static rtx 3257 static rtx_insn *
3140 peep2_attempt (basic_block bb, rtx insn, int match_len, rtx attempt) 3258 peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt)
3141 { 3259 {
3142 int i; 3260 int i;
3143 rtx last, note, before_try, x; 3261 rtx_insn *last, *before_try, *x;
3144 rtx old_insn, new_insn; 3262 rtx eh_note, as_note;
3263 rtx_insn *old_insn;
3264 rtx_insn *new_insn;
3145 bool was_call = false; 3265 bool was_call = false;
3146 3266
3147 /* If we are splittind an RTX_FRAME_RELATED_P insn, do not allow it to 3267 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3148 match more than one insn, or to be split into more than one insn. */ 3268 match more than one insn, or to be split into more than one insn. */
3149 old_insn = peep2_insn_data[peep2_current].insn; 3269 old_insn = peep2_insn_data[peep2_current].insn;
3150 if (RTX_FRAME_RELATED_P (old_insn)) 3270 if (RTX_FRAME_RELATED_P (old_insn))
3151 { 3271 {
3152 bool any_note = false; 3272 bool any_note = false;
3273 rtx note;
3153 3274
3154 if (match_len != 0) 3275 if (match_len != 0)
3155 return NULL; 3276 return NULL;
3156 3277
3157 /* Look for one "active" insn. I.e. ignore any "clobber" insns that 3278 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3228 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other 3349 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3229 cfg-related call notes. */ 3350 cfg-related call notes. */
3230 for (i = 0; i <= match_len; ++i) 3351 for (i = 0; i <= match_len; ++i)
3231 { 3352 {
3232 int j; 3353 int j;
3354 rtx note;
3233 3355
3234 j = peep2_buf_position (peep2_current + i); 3356 j = peep2_buf_position (peep2_current + i);
3235 old_insn = peep2_insn_data[j].insn; 3357 old_insn = peep2_insn_data[j].insn;
3236 if (!CALL_P (old_insn)) 3358 if (!CALL_P (old_insn))
3237 continue; 3359 continue;
3247 3369
3248 gcc_assert (new_insn != NULL_RTX); 3370 gcc_assert (new_insn != NULL_RTX);
3249 3371
3250 CALL_INSN_FUNCTION_USAGE (new_insn) 3372 CALL_INSN_FUNCTION_USAGE (new_insn)
3251 = CALL_INSN_FUNCTION_USAGE (old_insn); 3373 = CALL_INSN_FUNCTION_USAGE (old_insn);
3374 SIBLING_CALL_P (new_insn) = SIBLING_CALL_P (old_insn);
3252 3375
3253 for (note = REG_NOTES (old_insn); 3376 for (note = REG_NOTES (old_insn);
3254 note; 3377 note;
3255 note = XEXP (note, 1)) 3378 note = XEXP (note, 1))
3256 switch (REG_NOTE_KIND (note)) 3379 switch (REG_NOTE_KIND (note))
3257 { 3380 {
3258 case REG_NORETURN: 3381 case REG_NORETURN:
3259 case REG_SETJMP: 3382 case REG_SETJMP:
3383 case REG_TM:
3384 case REG_CALL_NOCF_CHECK:
3260 add_reg_note (new_insn, REG_NOTE_KIND (note), 3385 add_reg_note (new_insn, REG_NOTE_KIND (note),
3261 XEXP (note, 0)); 3386 XEXP (note, 0));
3262 break; 3387 break;
3263 default: 3388 default:
3264 /* Discard all other reg notes. */ 3389 /* Discard all other reg notes. */
3273 gcc_assert (!CALL_P (old_insn)); 3398 gcc_assert (!CALL_P (old_insn));
3274 } 3399 }
3275 break; 3400 break;
3276 } 3401 }
3277 3402
3403 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3404 move those notes over to the new sequence. */
3405 as_note = NULL;
3406 for (i = match_len; i >= 0; --i)
3407 {
3408 int j = peep2_buf_position (peep2_current + i);
3409 old_insn = peep2_insn_data[j].insn;
3410
3411 as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULL);
3412 if (as_note)
3413 break;
3414 }
3415
3278 i = peep2_buf_position (peep2_current + match_len); 3416 i = peep2_buf_position (peep2_current + match_len);
3279 3417 eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
3280 note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
3281 3418
3282 /* Replace the old sequence with the new. */ 3419 /* Replace the old sequence with the new. */
3420 rtx_insn *peepinsn = peep2_insn_data[i].insn;
3283 last = emit_insn_after_setloc (attempt, 3421 last = emit_insn_after_setloc (attempt,
3284 peep2_insn_data[i].insn, 3422 peep2_insn_data[i].insn,
3285 INSN_LOCATOR (peep2_insn_data[i].insn)); 3423 INSN_LOCATION (peepinsn));
3286 before_try = PREV_INSN (insn); 3424 before_try = PREV_INSN (insn);
3287 delete_insn_chain (insn, peep2_insn_data[i].insn, false); 3425 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3288 3426
3289 /* Re-insert the EH_REGION notes. */ 3427 /* Re-insert the EH_REGION notes. */
3290 if (note || (was_call && nonlocal_goto_handler_labels)) 3428 if (eh_note || (was_call && nonlocal_goto_handler_labels))
3291 { 3429 {
3292 edge eh_edge; 3430 edge eh_edge;
3293 edge_iterator ei; 3431 edge_iterator ei;
3294 3432
3295 FOR_EACH_EDGE (eh_edge, ei, bb->succs) 3433 FOR_EACH_EDGE (eh_edge, ei, bb->succs)
3296 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) 3434 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3297 break; 3435 break;
3298 3436
3299 if (note) 3437 if (eh_note)
3300 copy_reg_eh_region_note_backward (note, last, before_try); 3438 copy_reg_eh_region_note_backward (eh_note, last, before_try);
3301 3439
3302 if (eh_edge) 3440 if (eh_edge)
3303 for (x = last; x != before_try; x = PREV_INSN (x)) 3441 for (x = last; x != before_try; x = PREV_INSN (x))
3304 if (x != BB_END (bb) 3442 if (x != BB_END (bb)
3305 && (can_throw_internal (x) 3443 && (can_throw_internal (x)
3315 flags |= EDGE_ABNORMAL_CALL; 3453 flags |= EDGE_ABNORMAL_CALL;
3316 nehe = make_edge (nfte->src, eh_edge->dest, 3454 nehe = make_edge (nfte->src, eh_edge->dest,
3317 flags); 3455 flags);
3318 3456
3319 nehe->probability = eh_edge->probability; 3457 nehe->probability = eh_edge->probability;
3320 nfte->probability 3458 nfte->probability = nehe->probability.invert ();
3321 = REG_BR_PROB_BASE - nehe->probability;
3322 3459
3323 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest); 3460 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3324 bb = nfte->src; 3461 bb = nfte->src;
3325 eh_edge = nehe; 3462 eh_edge = nehe;
3326 } 3463 }
3327 3464
3328 /* Converting possibly trapping insn to non-trapping is 3465 /* Converting possibly trapping insn to non-trapping is
3329 possible. Zap dummy outgoing edges. */ 3466 possible. Zap dummy outgoing edges. */
3330 peep2_do_cleanup_cfg |= purge_dead_edges (bb); 3467 peep2_do_cleanup_cfg |= purge_dead_edges (bb);
3331 } 3468 }
3469
3470 /* Re-insert the ARGS_SIZE notes. */
3471 if (as_note)
3472 fixup_args_size_notes (before_try, last, INTVAL (XEXP (as_note, 0)));
3332 3473
3333 /* If we generated a jump instruction, it won't have 3474 /* If we generated a jump instruction, it won't have
3334 JUMP_LABEL set. Recompute after we're done. */ 3475 JUMP_LABEL set. Recompute after we're done. */
3335 for (x = last; x != before_try; x = PREV_INSN (x)) 3476 for (x = last; x != before_try; x = PREV_INSN (x))
3336 if (JUMP_P (x)) 3477 if (JUMP_P (x))
3347 emitted as a replacement. PREV is the insn before the start of 3488 emitted as a replacement. PREV is the insn before the start of
3348 the replacement. MATCH_LEN is the number of instructions that were 3489 the replacement. MATCH_LEN is the number of instructions that were
3349 matched, and which now need to be replaced in the buffer. */ 3490 matched, and which now need to be replaced in the buffer. */
3350 3491
3351 static void 3492 static void
3352 peep2_update_life (basic_block bb, int match_len, rtx last, rtx prev) 3493 peep2_update_life (basic_block bb, int match_len, rtx_insn *last,
3494 rtx_insn *prev)
3353 { 3495 {
3354 int i = peep2_buf_position (peep2_current + match_len + 1); 3496 int i = peep2_buf_position (peep2_current + match_len + 1);
3355 rtx x; 3497 rtx_insn *x;
3356 regset_head live; 3498 regset_head live;
3357 3499
3358 INIT_REG_SET (&live); 3500 INIT_REG_SET (&live);
3359 COPY_REG_SET (&live, peep2_insn_data[i].live_before); 3501 COPY_REG_SET (&live, peep2_insn_data[i].live_before);
3360 3502
3389 Return true if we added it, false otherwise. The caller will try to match 3531 Return true if we added it, false otherwise. The caller will try to match
3390 peepholes against the buffer if we return false; otherwise it will try to 3532 peepholes against the buffer if we return false; otherwise it will try to
3391 add more instructions to the buffer. */ 3533 add more instructions to the buffer. */
3392 3534
3393 static bool 3535 static bool
3394 peep2_fill_buffer (basic_block bb, rtx insn, regset live) 3536 peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live)
3395 { 3537 {
3396 int pos; 3538 int pos;
3397 3539
3398 /* Once we have filled the maximum number of insns the buffer can hold, 3540 /* Once we have filled the maximum number of insns the buffer can hold,
3399 allow the caller to match the insns against peepholes. We wait until 3541 allow the caller to match the insns against peepholes. We wait until
3424 /* Perform the peephole2 optimization pass. */ 3566 /* Perform the peephole2 optimization pass. */
3425 3567
3426 static void 3568 static void
3427 peephole2_optimize (void) 3569 peephole2_optimize (void)
3428 { 3570 {
3429 rtx insn; 3571 rtx_insn *insn;
3430 bitmap live; 3572 bitmap live;
3431 int i; 3573 int i;
3432 basic_block bb; 3574 basic_block bb;
3433 3575
3434 peep2_do_cleanup_cfg = false; 3576 peep2_do_cleanup_cfg = false;
3439 df_analyze (); 3581 df_analyze ();
3440 3582
3441 /* Initialize the regsets we're going to use. */ 3583 /* Initialize the regsets we're going to use. */
3442 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 3584 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3443 peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack); 3585 peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);
3586 search_ofs = 0;
3444 live = BITMAP_ALLOC (&reg_obstack); 3587 live = BITMAP_ALLOC (&reg_obstack);
3445 3588
3446 FOR_EACH_BB_REVERSE (bb) 3589 FOR_EACH_BB_REVERSE_FN (bb, cfun)
3447 { 3590 {
3448 bool past_end = false; 3591 bool past_end = false;
3449 int pos; 3592 int pos;
3450 3593
3451 rtl_profile_for_bb (bb); 3594 rtl_profile_for_bb (bb);
3456 peep2_reinit_state (live); 3599 peep2_reinit_state (live);
3457 3600
3458 insn = BB_HEAD (bb); 3601 insn = BB_HEAD (bb);
3459 for (;;) 3602 for (;;)
3460 { 3603 {
3461 rtx attempt, head; 3604 rtx_insn *attempt, *head;
3462 int match_len; 3605 int match_len;
3463 3606
3464 if (!past_end && !NONDEBUG_INSN_P (insn)) 3607 if (!past_end && !NONDEBUG_INSN_P (insn))
3465 { 3608 {
3466 next_insn: 3609 next_insn:
3486 /* Match the peephole. */ 3629 /* Match the peephole. */
3487 head = peep2_insn_data[peep2_current].insn; 3630 head = peep2_insn_data[peep2_current].insn;
3488 attempt = peephole2_insns (PATTERN (head), head, &match_len); 3631 attempt = peephole2_insns (PATTERN (head), head, &match_len);
3489 if (attempt != NULL) 3632 if (attempt != NULL)
3490 { 3633 {
3491 rtx last = peep2_attempt (bb, head, match_len, attempt); 3634 rtx_insn *last = peep2_attempt (bb, head, match_len, attempt);
3492 if (last) 3635 if (last)
3493 { 3636 {
3494 peep2_update_life (bb, match_len, last, PREV_INSN (attempt)); 3637 peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
3495 continue; 3638 continue;
3496 } 3639 }
3506 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 3649 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3507 BITMAP_FREE (peep2_insn_data[i].live_before); 3650 BITMAP_FREE (peep2_insn_data[i].live_before);
3508 BITMAP_FREE (live); 3651 BITMAP_FREE (live);
3509 if (peep2_do_rebuild_jump_labels) 3652 if (peep2_do_rebuild_jump_labels)
3510 rebuild_jump_labels (get_insns ()); 3653 rebuild_jump_labels (get_insns ());
3511 } 3654 if (peep2_do_cleanup_cfg)
3512 #endif /* HAVE_peephole2 */ 3655 cleanup_cfg (CLEANUP_CFG_CHANGED);
3656 }
3513 3657
3514 /* Common predicates for use with define_bypass. */ 3658 /* Common predicates for use with define_bypass. */
3515 3659
3516 /* True if the dependency between OUT_INSN and IN_INSN is on the store 3660 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3517 data not the address operand(s) of the store. IN_INSN and OUT_INSN 3661 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3518 must be either a single_set or a PARALLEL with SETs inside. */ 3662 must be either a single_set or a PARALLEL with SETs inside. */
3519 3663
3520 int 3664 int
3521 store_data_bypass_p (rtx out_insn, rtx in_insn) 3665 store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3522 { 3666 {
3523 rtx out_set, in_set; 3667 rtx out_set, in_set;
3524 rtx out_pat, in_pat; 3668 rtx out_pat, in_pat;
3525 rtx out_exp, in_exp; 3669 rtx out_exp, in_exp;
3526 int i, j; 3670 int i, j;
3609 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single 3753 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3610 or multiple set; IN_INSN should be single_set for truth, but for convenience 3754 or multiple set; IN_INSN should be single_set for truth, but for convenience
3611 of insn categorization may be any JUMP or CALL insn. */ 3755 of insn categorization may be any JUMP or CALL insn. */
3612 3756
3613 int 3757 int
3614 if_test_bypass_p (rtx out_insn, rtx in_insn) 3758 if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3615 { 3759 {
3616 rtx out_set, in_set; 3760 rtx out_set, in_set;
3617 3761
3618 in_set = single_set (in_insn); 3762 in_set = single_set (in_insn);
3619 if (! in_set) 3763 if (! in_set)
3657 } 3801 }
3658 3802
3659 return true; 3803 return true;
3660 } 3804 }
3661 3805
3662 static bool
3663 gate_handle_peephole2 (void)
3664 {
3665 return (optimize > 0 && flag_peephole2);
3666 }
3667
3668 static unsigned int 3806 static unsigned int
3669 rest_of_handle_peephole2 (void) 3807 rest_of_handle_peephole2 (void)
3670 { 3808 {
3671 #ifdef HAVE_peephole2 3809 if (HAVE_peephole2)
3672 peephole2_optimize (); 3810 peephole2_optimize ();
3811
3812 return 0;
3813 }
3814
3815 namespace {
3816
3817 const pass_data pass_data_peephole2 =
3818 {
3819 RTL_PASS, /* type */
3820 "peephole2", /* name */
3821 OPTGROUP_NONE, /* optinfo_flags */
3822 TV_PEEPHOLE2, /* tv_id */
3823 0, /* properties_required */
3824 0, /* properties_provided */
3825 0, /* properties_destroyed */
3826 0, /* todo_flags_start */
3827 TODO_df_finish, /* todo_flags_finish */
3828 };
3829
3830 class pass_peephole2 : public rtl_opt_pass
3831 {
3832 public:
3833 pass_peephole2 (gcc::context *ctxt)
3834 : rtl_opt_pass (pass_data_peephole2, ctxt)
3835 {}
3836
3837 /* opt_pass methods: */
3838 /* The epiphany backend creates a second instance of this pass, so we need
3839 a clone method. */
3840 opt_pass * clone () { return new pass_peephole2 (m_ctxt); }
3841 virtual bool gate (function *) { return (optimize > 0 && flag_peephole2); }
3842 virtual unsigned int execute (function *)
3843 {
3844 return rest_of_handle_peephole2 ();
3845 }
3846
3847 }; // class pass_peephole2
3848
3849 } // anon namespace
3850
3851 rtl_opt_pass *
3852 make_pass_peephole2 (gcc::context *ctxt)
3853 {
3854 return new pass_peephole2 (ctxt);
3855 }
3856
3857 namespace {
3858
3859 const pass_data pass_data_split_all_insns =
3860 {
3861 RTL_PASS, /* type */
3862 "split1", /* name */
3863 OPTGROUP_NONE, /* optinfo_flags */
3864 TV_NONE, /* tv_id */
3865 0, /* properties_required */
3866 PROP_rtl_split_insns, /* properties_provided */
3867 0, /* properties_destroyed */
3868 0, /* todo_flags_start */
3869 0, /* todo_flags_finish */
3870 };
3871
3872 class pass_split_all_insns : public rtl_opt_pass
3873 {
3874 public:
3875 pass_split_all_insns (gcc::context *ctxt)
3876 : rtl_opt_pass (pass_data_split_all_insns, ctxt)
3877 {}
3878
3879 /* opt_pass methods: */
3880 /* The epiphany backend creates a second instance of this pass, so
3881 we need a clone method. */
3882 opt_pass * clone () { return new pass_split_all_insns (m_ctxt); }
3883 virtual unsigned int execute (function *)
3884 {
3885 split_all_insns ();
3886 return 0;
3887 }
3888
3889 }; // class pass_split_all_insns
3890
3891 } // anon namespace
3892
3893 rtl_opt_pass *
3894 make_pass_split_all_insns (gcc::context *ctxt)
3895 {
3896 return new pass_split_all_insns (ctxt);
3897 }
3898
3899 namespace {
3900
3901 const pass_data pass_data_split_after_reload =
3902 {
3903 RTL_PASS, /* type */
3904 "split2", /* name */
3905 OPTGROUP_NONE, /* optinfo_flags */
3906 TV_NONE, /* tv_id */
3907 0, /* properties_required */
3908 0, /* properties_provided */
3909 0, /* properties_destroyed */
3910 0, /* todo_flags_start */
3911 0, /* todo_flags_finish */
3912 };
3913
3914 class pass_split_after_reload : public rtl_opt_pass
3915 {
3916 public:
3917 pass_split_after_reload (gcc::context *ctxt)
3918 : rtl_opt_pass (pass_data_split_after_reload, ctxt)
3919 {}
3920
3921 /* opt_pass methods: */
3922 virtual bool gate (function *)
3923 {
3924 /* If optimizing, then go ahead and split insns now. */
3925 if (optimize > 0)
3926 return true;
3927
3928 #ifdef STACK_REGS
3929 return true;
3930 #else
3931 return false;
3673 #endif 3932 #endif
3674 return 0; 3933 }
3675 } 3934
3676 3935 virtual unsigned int execute (function *)
3677 struct rtl_opt_pass pass_peephole2 = 3936 {
3678 { 3937 split_all_insns ();
3679 { 3938 return 0;
3680 RTL_PASS, 3939 }
3681 "peephole2", /* name */ 3940
3682 gate_handle_peephole2, /* gate */ 3941 }; // class pass_split_after_reload
3683 rest_of_handle_peephole2, /* execute */ 3942
3684 NULL, /* sub */ 3943 } // anon namespace
3685 NULL, /* next */ 3944
3686 0, /* static_pass_number */ 3945 rtl_opt_pass *
3687 TV_PEEPHOLE2, /* tv_id */ 3946 make_pass_split_after_reload (gcc::context *ctxt)
3688 0, /* properties_required */ 3947 {
3689 0, /* properties_provided */ 3948 return new pass_split_after_reload (ctxt);
3690 0, /* properties_destroyed */ 3949 }
3691 0, /* todo_flags_start */ 3950
3692 TODO_df_finish | TODO_verify_rtl_sharing | 3951 namespace {
3693 TODO_dump_func /* todo_flags_finish */ 3952
3694 } 3953 const pass_data pass_data_split_before_regstack =
3954 {
3955 RTL_PASS, /* type */
3956 "split3", /* name */
3957 OPTGROUP_NONE, /* optinfo_flags */
3958 TV_NONE, /* tv_id */
3959 0, /* properties_required */
3960 0, /* properties_provided */
3961 0, /* properties_destroyed */
3962 0, /* todo_flags_start */
3963 0, /* todo_flags_finish */
3695 }; 3964 };
3696 3965
3697 static unsigned int 3966 class pass_split_before_regstack : public rtl_opt_pass
3698 rest_of_handle_split_all_insns (void) 3967 {
3699 { 3968 public:
3700 split_all_insns (); 3969 pass_split_before_regstack (gcc::context *ctxt)
3701 return 0; 3970 : rtl_opt_pass (pass_data_split_before_regstack, ctxt)
3702 } 3971 {}
3703 3972
3704 struct rtl_opt_pass pass_split_all_insns = 3973 /* opt_pass methods: */
3705 { 3974 virtual bool gate (function *);
3706 { 3975 virtual unsigned int execute (function *)
3707 RTL_PASS, 3976 {
3708 "split1", /* name */ 3977 split_all_insns ();
3709 NULL, /* gate */ 3978 return 0;
3710 rest_of_handle_split_all_insns, /* execute */ 3979 }
3711 NULL, /* sub */ 3980
3712 NULL, /* next */ 3981 }; // class pass_split_before_regstack
3713 0, /* static_pass_number */ 3982
3714 TV_NONE, /* tv_id */ 3983 bool
3715 0, /* properties_required */ 3984 pass_split_before_regstack::gate (function *)
3716 0, /* properties_provided */ 3985 {
3717 0, /* properties_destroyed */ 3986 #if HAVE_ATTR_length && defined (STACK_REGS)
3718 0, /* todo_flags_start */
3719 TODO_dump_func /* todo_flags_finish */
3720 }
3721 };
3722
3723 static unsigned int
3724 rest_of_handle_split_after_reload (void)
3725 {
3726 /* If optimizing, then go ahead and split insns now. */
3727 #ifndef STACK_REGS
3728 if (optimize > 0)
3729 #endif
3730 split_all_insns ();
3731 return 0;
3732 }
3733
3734 struct rtl_opt_pass pass_split_after_reload =
3735 {
3736 {
3737 RTL_PASS,
3738 "split2", /* name */
3739 NULL, /* gate */
3740 rest_of_handle_split_after_reload, /* execute */
3741 NULL, /* sub */
3742 NULL, /* next */
3743 0, /* static_pass_number */
3744 TV_NONE, /* tv_id */
3745 0, /* properties_required */
3746 0, /* properties_provided */
3747 0, /* properties_destroyed */
3748 0, /* todo_flags_start */
3749 TODO_dump_func /* todo_flags_finish */
3750 }
3751 };
3752
3753 static bool
3754 gate_handle_split_before_regstack (void)
3755 {
3756 #if defined (HAVE_ATTR_length) && defined (STACK_REGS)
3757 /* If flow2 creates new instructions which need splitting 3987 /* If flow2 creates new instructions which need splitting
3758 and scheduling after reload is not done, they might not be 3988 and scheduling after reload is not done, they might not be
3759 split until final which doesn't allow splitting 3989 split until final which doesn't allow splitting
3760 if HAVE_ATTR_length. */ 3990 if HAVE_ATTR_length. */
3761 # ifdef INSN_SCHEDULING 3991 # ifdef INSN_SCHEDULING
3766 #else 3996 #else
3767 return 0; 3997 return 0;
3768 #endif 3998 #endif
3769 } 3999 }
3770 4000
3771 static unsigned int 4001 } // anon namespace
3772 rest_of_handle_split_before_regstack (void) 4002
3773 { 4003 rtl_opt_pass *
3774 split_all_insns (); 4004 make_pass_split_before_regstack (gcc::context *ctxt)
3775 return 0; 4005 {
3776 } 4006 return new pass_split_before_regstack (ctxt);
3777
3778 struct rtl_opt_pass pass_split_before_regstack =
3779 {
3780 {
3781 RTL_PASS,
3782 "split3", /* name */
3783 gate_handle_split_before_regstack, /* gate */
3784 rest_of_handle_split_before_regstack, /* execute */
3785 NULL, /* sub */
3786 NULL, /* next */
3787 0, /* static_pass_number */
3788 TV_NONE, /* tv_id */
3789 0, /* properties_required */
3790 0, /* properties_provided */
3791 0, /* properties_destroyed */
3792 0, /* todo_flags_start */
3793 TODO_dump_func /* todo_flags_finish */
3794 }
3795 };
3796
3797 static bool
3798 gate_handle_split_before_sched2 (void)
3799 {
3800 #ifdef INSN_SCHEDULING
3801 return optimize > 0 && flag_schedule_insns_after_reload;
3802 #else
3803 return 0;
3804 #endif
3805 } 4007 }
3806 4008
3807 static unsigned int 4009 static unsigned int
3808 rest_of_handle_split_before_sched2 (void) 4010 rest_of_handle_split_before_sched2 (void)
3809 { 4011 {
3811 split_all_insns (); 4013 split_all_insns ();
3812 #endif 4014 #endif
3813 return 0; 4015 return 0;
3814 } 4016 }
3815 4017
3816 struct rtl_opt_pass pass_split_before_sched2 = 4018 namespace {
3817 { 4019
3818 { 4020 const pass_data pass_data_split_before_sched2 =
3819 RTL_PASS, 4021 {
3820 "split4", /* name */ 4022 RTL_PASS, /* type */
3821 gate_handle_split_before_sched2, /* gate */ 4023 "split4", /* name */
3822 rest_of_handle_split_before_sched2, /* execute */ 4024 OPTGROUP_NONE, /* optinfo_flags */
3823 NULL, /* sub */ 4025 TV_NONE, /* tv_id */
3824 NULL, /* next */ 4026 0, /* properties_required */
3825 0, /* static_pass_number */ 4027 0, /* properties_provided */
3826 TV_NONE, /* tv_id */ 4028 0, /* properties_destroyed */
3827 0, /* properties_required */ 4029 0, /* todo_flags_start */
3828 0, /* properties_provided */ 4030 0, /* todo_flags_finish */
3829 0, /* properties_destroyed */
3830 0, /* todo_flags_start */
3831 TODO_verify_flow |
3832 TODO_dump_func /* todo_flags_finish */
3833 }
3834 }; 4031 };
3835 4032
3836 /* The placement of the splitting that we do for shorten_branches 4033 class pass_split_before_sched2 : public rtl_opt_pass
3837 depends on whether regstack is used by the target or not. */ 4034 {
3838 static bool 4035 public:
3839 gate_do_final_split (void) 4036 pass_split_before_sched2 (gcc::context *ctxt)
3840 { 4037 : rtl_opt_pass (pass_data_split_before_sched2, ctxt)
3841 #if defined (HAVE_ATTR_length) && !defined (STACK_REGS) 4038 {}
3842 return 1; 4039
4040 /* opt_pass methods: */
4041 virtual bool gate (function *)
4042 {
4043 #ifdef INSN_SCHEDULING
4044 return optimize > 0 && flag_schedule_insns_after_reload;
3843 #else 4045 #else
3844 return 0; 4046 return false;
3845 #endif 4047 #endif
3846 } 4048 }
3847 4049
3848 struct rtl_opt_pass pass_split_for_shorten_branches = 4050 virtual unsigned int execute (function *)
3849 { 4051 {
3850 { 4052 return rest_of_handle_split_before_sched2 ();
3851 RTL_PASS, 4053 }
3852 "split5", /* name */ 4054
3853 gate_do_final_split, /* gate */ 4055 }; // class pass_split_before_sched2
3854 split_all_insns_noflow, /* execute */ 4056
3855 NULL, /* sub */ 4057 } // anon namespace
3856 NULL, /* next */ 4058
3857 0, /* static_pass_number */ 4059 rtl_opt_pass *
3858 TV_NONE, /* tv_id */ 4060 make_pass_split_before_sched2 (gcc::context *ctxt)
3859 0, /* properties_required */ 4061 {
3860 0, /* properties_provided */ 4062 return new pass_split_before_sched2 (ctxt);
3861 0, /* properties_destroyed */ 4063 }
3862 0, /* todo_flags_start */ 4064
3863 TODO_dump_func | TODO_verify_rtl_sharing /* todo_flags_finish */ 4065 namespace {
3864 } 4066
4067 const pass_data pass_data_split_for_shorten_branches =
4068 {
4069 RTL_PASS, /* type */
4070 "split5", /* name */
4071 OPTGROUP_NONE, /* optinfo_flags */
4072 TV_NONE, /* tv_id */
4073 0, /* properties_required */
4074 0, /* properties_provided */
4075 0, /* properties_destroyed */
4076 0, /* todo_flags_start */
4077 0, /* todo_flags_finish */
3865 }; 4078 };
4079
4080 class pass_split_for_shorten_branches : public rtl_opt_pass
4081 {
4082 public:
4083 pass_split_for_shorten_branches (gcc::context *ctxt)
4084 : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt)
4085 {}
4086
4087 /* opt_pass methods: */
4088 virtual bool gate (function *)
4089 {
4090 /* The placement of the splitting that we do for shorten_branches
4091 depends on whether regstack is used by the target or not. */
4092 #if HAVE_ATTR_length && !defined (STACK_REGS)
4093 return true;
4094 #else
4095 return false;
4096 #endif
4097 }
4098
4099 virtual unsigned int execute (function *)
4100 {
4101 return split_all_insns_noflow ();
4102 }
4103
4104 }; // class pass_split_for_shorten_branches
4105
4106 } // anon namespace
4107
4108 rtl_opt_pass *
4109 make_pass_split_for_shorten_branches (gcc::context *ctxt)
4110 {
4111 return new pass_split_for_shorten_branches (ctxt);
4112 }
4113
4114 /* (Re)initialize the target information after a change in target. */
4115
4116 void
4117 recog_init ()
4118 {
4119 /* The information is zero-initialized, so we don't need to do anything
4120 first time round. */
4121 if (!this_target_recog->x_initialized)
4122 {
4123 this_target_recog->x_initialized = true;
4124 return;
4125 }
4126 memset (this_target_recog->x_bool_attr_masks, 0,
4127 sizeof (this_target_recog->x_bool_attr_masks));
4128 for (unsigned int i = 0; i < NUM_INSN_CODES; ++i)
4129 if (this_target_recog->x_op_alt[i])
4130 {
4131 free (this_target_recog->x_op_alt[i]);
4132 this_target_recog->x_op_alt[i] = 0;
4133 }
4134 }