diff gcc/ChangeLog-2016 @ 16:04ced10e8804

gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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+2016-12-30  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* doc/cppopts.texi: Reorder table entries to put the most
+	commonly-used options first and debug options last.
+
+2016-12-30  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*testqi_ext_3): Merge insn pattern and
+	corresponding splitter to define_insn_and_split.  Use wi::shifted_mask
+	helper function to calculate mask.
+
+2016-12-30  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/predicates.md (ext_register_operand): Do not reject
+	registers without upper parts here.
+	* config/i386/i386.md (extv<mode>): Copy registers without
+	upper parts in operand 1 to a pseudo.
+	(extzv<mode>): Ditto.
+	(insv<mode>): Ditto.
+
+2016-12-30  Gerald Pfeifer  <gerald@pfeifer.com>
+
+	* doc/standards.texi (Standards): Remove broken reference to
+	objc.toodarkpark.net and avoid list with now just one item.
+
+2016-12-29  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* config/i386/i386.md (*extvqi): Remove insn pattern.
+	(divmodqi4): Update expander to generate QImode zero-extract from AH.
+
+2016-12-29  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000.c (altivec_expand_builtin): Fix typos in
+	error messages.
+
+2016-12-29  Gerald Pfeifer  <gerald@pfeifer.com>
+
+	* doc/extend.texi (Cilk Plus Builtins): cilkplus.org now uses
+	https by default.
+	* doc/passes.texi (Cilk Plus Transformation): Ditto.
+	* doc/generic.texi (Statements for C++): Ditto, and use @uref.
+
+2016-12-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* config/i386/constraints.md (Bn): New special memory constraint.
+	* config/i386/predicates.md (norex_memory_operand): New predicate.
+	* config/i386/i386.md (*extzvqi_mem_rex64): New insn pattern and
+	corresponding peephole2 pattern.
+
+2016-12-27  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* doc/cppdiropts.texi, doc/cppwarnopts.texi:  New files, split from...
+	* doc/cppopts.texi: .... here.
+	* doc/cpp.texi (Invocation): Adjust includes.
+	* doc/invoke.texi (Option Summary): Add missing preprocesor-related
+	options.  Adjust sorting and formatting.
+	(Warning Options): Include cppwarnopts.texi.
+	(Preprocessor Options): Add pointers and list the specific
+	preprocessor options from cppopts.texi first instead of last.
+	(Directory Options): Move/merge documentation of -I, -iquote, and
+	-I- to cppdiropts.texi.  Include that file here.
+
+2016-12-27  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/predicates.md (const_0_to_12_operand): Rename
+	predicate and change test from 0..11 to 0..12 to match the
+	semantics of the word extract/insert instructions.  Change all
+	callers.
+	(const_0_to_11_operand): Likewise.
+	* config/rs6000/rs6000.c (altivec_expand_builtin): Likewise.
+	* config/rs6000/vsx.md (vextract4b): Likewise.
+	(vextract4b_internal): Likewise.
+	(vinsert4b): Likewise.
+	(vinsert4b_internal): Likewise.
+	(vinsert4b_di): Likewise.
+	(vinsert4b_di_internal): Likewise.
+	* config/rs6000/rs6000.md (zero_extendsi<mode>2): Fix offset used
+	in xxextractuw to zero extend the word in the vector registers.
+	(lfiwzx): Likewise.
+
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.c (ix86_secondary_reload): Require QImode
+	intermediate for QImode mask register spill only for !TARGET_AVX512DQ.
+	Always use true_regnum to determine operand regno.
+
+2016-12-27  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* doc/cppopts.texi: Delete redundant documentation for -x.  Move
+	-fno-show-column documentation to...
+	* doc/invoke.texi (Diagnostic Message Formatting Options):  ...here.
+	Update the option summary.
+
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (VI_512): Remove.
+	(vcond<V_512:mode><VI_AVX512BW:mode>): Use VI_AVX512BW
+	mode iterator instead of VI_512.
+	(vcondu<V_512:mode><VI_AVX512BW:mode>): Ditto.
+
+2016-12-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR translation/78922
+	* config/i386/stringop.opt: Remove.
+
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* config/i386/constraints.md (Bc): New special memory constraint.
+	* config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use Bc
+	constraint with nonimmediate_operand to allow constant memory operands.
+	(*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1)
+	(*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use Bc constraint
+	with general_operand to allow constant memory operands.
+
+2016-12-27  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+
+	* c-family/c.opt (flag_chkp_flexible_struct_trailing_arrays):
+	Add new option.
+	(fchkp-narrow-to-innermost-array): Fix typo.
+	* doc/cpp.texi (flag_chkp_flexible_struct_trailing_arrays): Ditto.
+	* tree-chkp.c (chkp_may_narrow_to_field ): Forbid
+	narrowing when flag_chkp_flexible_struct_trailing_arrays is used
+	and the field is the last array field in the structure.
+
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (andqi_ext_1): Use general_operand
+	predicate for operand 2.
+
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use
+	nonimmediate_operand instead of nonimmediate_x64nomem_operand.
+	(*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1)
+	(*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use general_operand
+	instead of general_x64nomem_operand.
+	* config/i386/predicates.md (nonimmediate_x64nomem_operand): Remove.
+	(general_x64nomem_operand): Ditto.
+
+2016-12-26  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78904
+	* config/i386/i386.md (addqi_ext_1): Canonicalize insn pattern w.r.t.
+	zero_extract RTXes.
+	(*addqi_ext_2): Ditto.
+	(testqi_ext_ccno_0): Canonicalize expander w.r.t. zero_extract RTXes.
+	(testqi_ext_1_ccno): Rename from testqi_ext_ccno_0.
+	(*testqi_ext_0): Merge with *testqi_ext_1.
+	(*testqi_ext_1): Canonicalize insn pattern w.r.t. zero_extract RTXes.
+	Update corresponding splitter.
+	(*testqi_ext_2): Canonicalize insn pattern w.r.t. zero_extract RTXes.
+	(*andqi_ext_0): Merge with *andqi_ext_1.
+	(andqi_ext_1): Canonicalize insn pattern w.r.t. zero_extract RTXes.
+	Rename from *andqi_ext_1.  Update corresponding splitter and
+	peephole2 patterns.
+	(*andqi_ext_1_cc): Rename from *andqi_ext_0_cc.
+	(*andqi_ext_2): Canonicalize insn pattern w.r.t. zero_extract RTXes.
+	(*<any_or:code>qi_ext_0): Merge with *andqi_ext_1.
+	(*<any_or:code>qi_ext_1): Canonicalize insn pattern w.r.t.
+	zero_extract RTXes.  Update corresponding splitter.
+	(*<any_or:code>qi_ext_2): Canonicalize insn pattern w.r.t.
+	zero_extract RTXes.
+	(xorqi_cc_ext_1): Canonicalize expander w.r.t. zero_extract RTXes.
+	(xorqi_ext_1_cc): Rename from xorqi_cc_ext_1.
+	(*xorqi_cc_ext_1): Canonicalize insn pattern w.r.t. zero_extract RTXes.
+	Update corresponding splitter.
+	(*xorqi_ext_1_cc): Rename from *xorqi_cc_ext_1.
+	(isinfxf2): Update calls to renamed expanders.
+	(isinf<mode>2): Ditto.
+	* config/i386/i386.c (ix86_expand_fp_compare): Ditto.
+	(ix86_emit_fp_unordered_jump): Ditto.
+	(ix86_emit_i387_round): Ditto.
+
+2016-12-26  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* doc/invoke.texi (SPARC options): Add missing documentation for -mlra.
+
+	* doc/cpp.texi (Invocation): Remove space in command.
+
+2016-12-25  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* doc/cpp.texi (Invocation): Revise to indicate that GCC driver
+	options are only documented in the GCC manual.
+	* doc/cppopts.texi: Delete documentation of GCC driver options
+	-o, -Wall, -Wtraditional, -Werror, -Wsystem-headers, -w,
+	-pedantic, -pedantic-errors, -std=, -ansi, --help, --target-help,
+	-v, -version.  Update -Wcomment, -Wtrigraphs, -Wundef,
+	-Wexpansion-to-defined, -Wno-endif-labels, -traditional,
+	-traditional-cpp, -trigraphs to merge text previously in GCC manual.
+	* doc/invoke.texi (Option Summary): Move -trigraphs, -traditional,
+	and -traditional-cpp from C dialect options to preprocessor options.
+	(C Dialect Options): Likewise.
+	(Warning Options): Delete documentation of -Wcomment, -Wtrigraphs,
+	-Wexpansion-to-defined, -Wundef, and -Wno-endif-labels.
+
+2016-12-24  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-core.h (tree_base): Document the meaning of public_flag
+	for SSA names.
+	* tree.h (SSA_NAME_IS_VIRTUAL_OPERAND): New macro.
+	(SET_SSA_NAME_VAR_OR_IDENTIFIER): Record whether the variable
+	is a virtual operand.
+	* gimple-expr.h (virtual_operand_p): Use SSA_NAME_IS_VIRTUAL_OPERAND.
+
+2016-12-22  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	* tree-pretty-print.c (dump_generic_node): Change dump format for
+	REALPART_EXPR and IMAGPART_EXPR with TDF_GIMPLE.
+
+2016-12-22  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* varasm.c (build_constant_desc): Use the alignment of the var
+	decl instead of the original expression.
+
+2016-12-22  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	* config/s390/s390-c.c (s390_cpu_cpp_builtins_internal): Define
+	__S390_ARCH_LEVEL__.
+
+2016-12-22  Martin Liska  <mliska@suse.cz>
+
+	PR tree-optimization/78886
+	* tree-ssa-strlen.c (handle_builtin_malloc): Return when LHS
+	is equal to NULL.
+
+2016-12-22  Jakub Jelinek  <jakub@redhat.com>
+
+	PR bootstrap/78817
+	* vec.h (vec<T, va_heap, vl_ptr>::safe_grow_cleared): Revert
+	2016-12-15 change.
+
+2016-12-21  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/78580
+	* ira-costs.c (find_costs_and_classes): Make regno_aclass
+	translated into an allocno class.
+
+2016-12-21  Jakub Jelinek  <jakub@redhat.com>
+
+	PR bootstrap/78817
+	* tree-pass.h (make_pass_post_ipa_warn): Declare.
+	* builtins.c (validate_arglist): Adjust get_nonnull_args call.
+	Check for NULL pointer argument to nonnull arg here.
+	(validate_arg): Revert 2016-12-14 changes.
+	* calls.h (get_nonnull_args): Remove declaration.
+	* tree-ssa-ccp.c: Include diagnostic-core.h.
+	(pass_data_post_ipa_warn): New variable.
+	(pass_post_ipa_warn): New class.
+	(pass_post_ipa_warn::execute): New method.
+	(make_pass_post_ipa_warn): New function.
+	* tree.h (get_nonnull_args): Declare.
+	* tree.c (get_nonnull_args): New function.
+	* calls.c (maybe_warn_null_arg): Removed.
+	(maybe_warn_null_arg): Removed.
+	(initialize_argument_information): Revert 2016-12-14 changes.
+	* passes.def: Add pass_post_ipa_warn after first ccp after IPA.
+
+2016-12-21  Pat Haugen  <pthaugen@us.ibm.com>
+
+	PR rtl-optimization/11488
+	* common/config/rs6000/rs6000-common.c
+	(rs6000_option_optimization_table): Enable -fsched-pressure.
+	* config/rs6000/rs6000.c (TARGET_COMPUTE_PRESSURE_CLASSES): Define
+	target hook.
+	(rs6000_option_override_internal): Set default -fsched-pressure
+	algorithm.
+	(rs6000_compute_pressure_classes): Implement target hook.
+
+2016-12-21  Bill Seurer  <seurer@linux.vnet.ibm.com>
+
+	PR sanitizer/65479
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+	-fasynchronous-unwind-tables option when -fsanitize=address is
+	specified.
+
+2016-12-21  Bernd Schmidt  <bschmidt@redhat.com>
+
+	PR target/71321
+	* config/i386/i386.md (lea<mode>_general_2b, lea<mode>_general_3b): New
+	patterns.
+	* config/i386/predicates.md (const123_operand): New.
+
+2016-12-21  Jakub Jelinek  <jakub@redhat.com>
+	    Martin Liska  <mliska@suse.cz>
+
+	PR driver/78863
+	* gcc.c (driver::build_option_suggestions): Do not add
+	-fsanitize=all as a suggestion candidate.
+
+2016-12-21  Alexander Monakov  <amonakov@ispras.ru>
+
+	PR target/78831
+	* config/nvptx/nvptx.c (init_softstack_frame): Remove assert.  Compute
+	crtl->is_leaf only if unset.  Adjust comment.
+
+2016-12-21  Andrew Pinski  <apinski@cavium.com>
+
+	* match.pd (max:c @0 (plus@2 @0 INTEGER_CST@1)): New Pattern.
+	(min:c @0 (plus@2 @0 INTEGER_CST@1)) : New Pattern.
+
+2016-12-20  James Greenhalgh  <james.greenhalghj@arm.com>
+
+	* common.opt (excess_precision): Tag as SetByCombined.
+	* opts.c (set_fast_math_flags): Also set
+	flag_excess_precision_cmdline.
+	(fast_math_flags_set_p): Also check flag_excess_precision_cmdline.
+	* doc/invoke.texi (-fexcess-precision): Drop text saying the
+	option has no effect under -ffast-math, make it clear that
+	-ffast-math will cause -fexcess-precision=fast by default even for
+	standards compliant modes.
+	(-ffast-math): Document that this sets -fexcess-precision=fast.
+
+2016-12-20  Richard Biener  <rguenther@suse.de>
+
+	* passes.c (execute_one_pass): Handle going out of SSA w/o
+	hitting pass_startwith.  Handle skipping property providers.
+
+2016-12-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/78694
+	* config/arm/arm.c (dump_minipool): Copy mp->value before emitting it
+	in the minipool to avoid invalid RTL sharing.
+
+2016-12-19  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000-protos.h (expand_strn_compare): Declare.
+	* config/rs6000/rs6000.md (UNSPEC_CMPB): New unspec.
+	(cmpb<mode>3): pattern for generating cmpb.
+	(cmpstrnsi): pattern to expand strncmp ().
+	* config/rs6000/rs6000.opt (mstring-compare-inline-limit): Add a new
+	target option for controlling how much code inline expansion of
+	strncmp() will be allowed to generate.
+	* config/rs6000/rs6000.c (expand_strncmp_align_check): generate code
+	for runtime page crossing check of strncmp () args.
+	(expand_strn_compare): Function to do builtin expansion of strncmp ().
+
+2016-12-19  David Malcolm  <dmalcolm@redhat.com>
+
+	* print-rtl-function.c (print_rtx_function): Update
+	example in comment to reflect current format.
+
+2016-12-19  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*popcounthi2_1): New insn_and_split pattern.
+
+2016-12-19  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* doc/cpp.texi: Clean up anachronistic C99 references and remove
+	discussion of very old GCC versions.
+	(Differences from previous versions): Delete entire section.
+
+2016-12-19  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for
+	early expansion of vector multiply and subtract builtins.
+
+2016-12-19  David Malcolm  <dmalcolm@redhat.com>
+
+	* print-rtl.c (rtx_writer::print_rtx_operand_code_r): For
+	non-virtual pseudos in compact mode, wrap the regno in '<' and '>'
+	rather than using a '%' prefix.
+	* rtl-tests.c (selftest::test_dumping_regs): Update for above change.
+
+2016-12-19  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	PR target/78748
+	* config/s390/s390.md ("*andc_split_<mode>"): Allow memory destination
+	only if it coincides with operand 2.
+
+2016-12-19  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	* combine.c (change_zero_ext): Skip generation of redundant AND.
+
+2016-12-19  Krister Walfridsson  <krister.walfridsson@gmail.com>
+
+	* config/netbsd.h (LINK_EH_SPEC): Define.
+
+2016-12-18  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* lra-constraints.c (process_address): Add forward declaration.
+	(simplify_operand_subreg): In the MEM case, if the adjusted memory
+	reference is not sufficient aligned and the address was invalid,
+	reload the address before reloading the original memory reference.
+	Fix long lines and add a final return for the sake of clarity.
+
+2016-12-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR sanitizer/78832
+	* sanopt.c (sanitize_asan_mark_unpoison): Remove next variable, use
+	continue if gsi_next should be skipped.
+	(sanitize_asan_mark_poison): Remove prev variable, use continue if
+	gsi_prev should be skipped.  When removing ASAN_MARK, do gsi_prev
+	first and gsi_remove on a previously made copy of the iterator.
+
+2016-12-17  Andrew Senkevich  <andrew.senkevich@intel.com>
+
+	* config/i386/avx512bwintrin.h: Add new k-mask intrinsics.
+	* config/i386/avx512dqintrin.h: Ditto.
+	* config/i386/avx512fintrin.h: Ditto.
+	* config/i386/i386-builtin.def (__builtin_ia32_kaddqi,
+	__builtin_ia32_kaddhi, __builtin_ia32_kaddsi,
+	__builtin_ia32_kadddi): New.
+	* config/i386/sse.md (kadd<mode>): New.
+
+2016-12-17  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*tzcnt<mode>_1): Merge *tzcnt<mode>_1_falsedep_1
+	and *tzcnt<mode>_1 to define_insn_and_split pattern.  Adjust split
+	condition to split after epilogue_completed.
+	(ctz<mode>2): Remove expander.
+	(ctz<mode>2): Merge *ctz<mode>2_falsedep_1 and *ctz<mode>2 to
+	define_insn_and_split pattern.  Adjust split condition to split
+	after epilogue_completed.
+	(clz<mode>2_lznct): Remove expander.
+	(clz<mode>2_lzcnt): Merge *clz<mode>2_lzcnt_falsedep_1 and
+	*clz<mode>2 to define_insn_and_split pattern.  Adjust split
+	condition to split after epilogue_completed.
+	(<lt_zcnt>_<mode>): Remove expander.
+	(<lt_zcnt>_<mode>): Merge *<lt_zcnt>_<mode>_falsedep_1 and
+	*<lt_zcnt>_<mode> to define_insn_and_split pattern.  Adjust split
+	condition to split after epilogue_completed.
+	(<lt_zcnt>_hi): New insn pattern.
+	(popcount<mode>2): Remove expander.
+	(popcount<mode>2): Merge *popcount<mode>2_falsedep_1 and
+	*popcount<mode>2 to define_insn_and_split pattern.  Adjust split
+	condition to split after epilogue_completed.
+	(popcounthi2): New insn pattern.
+
+2016-12-16  Kelvin Nilsen  <kelvin@gcc.gnu.org>
+
+	* config/rs6000/altivec.md (UNSPEC_CMPRB): New unspec value.
+	(UNSPEC_CMPRB2): New unspec value.
+	(UNSPEC_CMPEQB): New unspec value.
+	(cmprb): New expansion.
+	(*cmprb_internal): New insn.
+	(*setb_internal): New insn.
+	(cmprb2): New expansion.
+	(*cmprb2_internal): New insn.
+	(cmpeqb): New expansion.
+	(*cmpeqb_internal): New insn.
+	* config/rs6000/rs6000-builtin.def (BU_P9_2): New macro.
+	(BU_P9_64BIT_2): Likewise.
+	(BU_P9_OVERLOAD_2): Likewise.
+	(CMPRB): Add byte-in-range built-in function.
+	(CMBRB2): Add byte-in-either-range built-in function.
+	(CMPEQB): Add byte-in-set built-in function.
+	(CMPRB): Add overload support for byte-in-range function.
+	(CMPRB2): Add overload support for byte-in-either-range function.
+	(CMPEQB): Add overload support for byte-in-set built-in function.
+	* config/rs6000/rs6000-c.c (P9_BUILTIN_CMPRB): Macro expansion to
+	define argument types for new builtin.
+	(P9_BUILTIN_CMPRB2): Likewise.
+	(P9_BUILTIN_CMPEQB): Likewise.
+	* doc/extend.texi (PowerPC AltiVec Built-in Functions): Rearrange
+	the order of presentation for certain built-in functions
+	(scalar_extract_exp, scalar_extract_sig, scalar_insert_exp)
+	(scalar_cmp_exp_gt, scalar_cmp_exp_lt, scalar_cmp_exp_eq)
+	(scalar_cmp_exp_unordered, scalar_test_data_class)
+	(scalar_test_neg) to improve locality and flow.  Document
+	the new __builtin_scalar_byte_in_set,
+	__builtin_scalar_byte_in_range, and
+	__builtin_scalar_byte_in_either_range functions.
+
+2016-12-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.md: New define_split above bswap<mode>2.
+
+2016-12-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.md: New define_split above insv<mode>.
+
+2016-12-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/78408
+	* tree-ssa-ccp.c: Include tree-dfa.h.
+	(optimize_memcpy): New function.
+	(pass_fold_builtins::execute): Use it.  Remove useless conditional
+	break after BUILT_IN_VA_*.
+
+2016-12-16  Marek Polacek  <polacek@redhat.com>
+
+	PR tree-optimization/78819
+	* tree-vrp.c (find_switch_asserts): Return if the insertion limit is 0.
+	Don't register an assertion if the default case shares a label with
+	another case.
+
+2016-12-16  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/arm/arm.md (subsi3_carryin): Add Thumb-2 RSC #0.
+	(arm_negdi2) Rename to negdi2_insn, allow on Thumb-2.
+	* config/arm/thumb2.md (thumb2_negdi2): Remove pattern.
+
+2016-12-16  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14.
+
+2016-12-16  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.md (call_prof): Remove.
+	(call_value_prof): Likewise.
+	(sibcall_prof): Likewise.
+	(sibcall_value_prof): Likewise.
+
+2016-12-16  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.h (LINK_SPEC): Tidy up.
+	(ENDFILE_SPEC): Likewise.
+	(LIB_SPEC): Likewise.
+	(STARTFILE_SPEC): Include gcrt0 when profiling.
+	(FUNCTION_PROFILER): Use __mcount.
+	* config/arc/arc.opt (mucb-mcount): Remove.
+	* doc/invoke.texi (ARC): Remove mucb-mcount doc.
+	* arc/arc-protos.h (arc_profile_call): Remove.
+	* config/arc/arc.c (write_profile_sections): Likewise.
+	(arc_profile_call): Likewise.
+	(unspec_prof_hash): Likewise.
+	(unspec_prof_htab_eq): Likewise.
+	(arc_legitimate_constant_p): Remove UNSPEC_PROF.
+	(arc_reorg): Remove call to write_profile_sections.
+	* config/arc/arc.md (call): Remove call to arc_profile_call.
+	(call_value): Likewise.
+	(sibcall): Likewise.
+	(sibcall_value): Likewise.
+	(define_constants): Remove UNSPEC_PROF.
+
+2016-12-16  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.md (mulsidi_600): Change to insn_and_split,
+	generate new mul64 insn for core multiplication work.
+	(umulsidi_600): Likewise, but use mulu64 insn.
+	(mul64): New pattern, content taken from old mulsidi_600 insn pattern.
+	(mulu64): Likewise, but using umulsidi_600.
+	(mulsidi3): Remove move to destination, this is now handled by
+	mulsidi_600 insn_and_split.
+	(umulsidi3): Likewise, but using umulsidi_600.
+
+2016-12-16  Richard Biener  <rguenther@suse.de>
+
+	PR c++/71694
+	* langhooks-def.h (lhd_unit_size_without_reusable_padding): Declare.
+	(LANG_HOOKS_UNIT_SIZE_WITHOUT_REUSABLE_PADDING): Define.
+	(LANG_HOOKS_FOR_TYPES_INITIALIZER): Adjust.
+	* langhooks.h (struct lang_hooks_for_types): Add
+	unit_size_without_reusable_padding.
+	* langhooks.c (lhd_unit_size_without_reusable_padding): New.
+	* stor-layout.c (finish_bitfield_representative): Use
+	unit_size_without_reusable_padding langhook to decide on the
+	last representatives size.
+
+2016-12-16  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/71632
+	* expr.c (expand_cond_expr_using_cmove): Bail out early if
+	we end up recursing via TER.
+
+2016-12-15  Martin Sebor  <msebor@redhat.com>
+
+	PR bootstrap/78817
+	* vec.h (vec<T, va_heap, vl_ptr>::safe_grow_cleared): Assert
+	a pointer is non-null.
+
+2016-12-15  Andrew Senkevich  <andrew.senkevich@intel.com>
+
+	* config/i386/avx512bwintrin.h: Add new k-mask intrinsics.
+	* config/i386/avx512dqintrin.h: Ditto.
+	* config/i386/avx512fintrin.h: Ditto.
+	* config/i386/i386-builtin.def (__builtin_ia32_kmovb,
+	__builtin_ia32_kmovd, __builtin_ia32_kmovq): New.
+	(__builtin_ia32_kmov16): Rename to __builtin_ia32_kmovw.
+	* config/i386/sse.md (kmov<mskmodesuffix>): New.
+
+2016-12-15  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (ffs<mode>2): Generate CCCmode flags register
+	for TARGET_BMI.
+	(ffssi2_no_cmove): Ditto.
+	(*tzcnt<mode>_1_falsedep_1): New insn_and_split pattern.
+	(*tzcnt<mode>_1_falsedep): New insn pattern.
+
+	(LT_ZCNT): New mode iterator.
+	(lt_zcnt): New mode attribute.
+	(lt_zcnt_type): New mode attribute.
+	(<lt_zcnt>_<mode>): Macroize expander from bmi_tzcnt_<mode> and
+	lzcnt_<mode> using LT_ZCNT mode iterator.
+	(*<lt_zcnt>_<mode>_falsedep_1): Macroize insn from
+	*bmi_tzcnt_<mode>_falsedep_1 and *lzcnt_<mode>_falsedep_1
+	using LT_ZCNT mode iterator.
+	(*<lt_zcnt>_<mode>_falsedep): Macroize insn from
+	*bmi_tzcnt_<mode>_falsedep and *lzcnt_<mode>_falsedep
+	using LT_ZCNT mode iterator.
+	(*<lt_zcnt>_<mode>): Macroize insn from *bmi_tzcnt_<mode>
+	and *lzcnt_<mode> using LT_ZCNT mode iterator.
+	* config/i386/i386-builtin.def (__builtin_ia32_tzcnt_u16)
+	(__builtin_ia32_tzcnt_u32, __builtin_ia32_tzcnt_u64, __builtin_ctzs):
+	Update for rename.
+
+2016-12-15  Jakub Jelinek  <jakub@redhat.com>
+
+	* ipa-cp.c (class ipcp_bits_lattice): Formatting fixes.
+	(print_ipcp_constant_value): Likewise.
+	(ipcp_cloning_candidate_p): Likewise.
+	(ipcp_bits_lattice::get_value_and_mask): Likewise.
+	(ipcp_bits_lattice::meet_with_1): Likewise.
+	(ipcp_bits_lattice::meet_with): Likewise.
+	(initialize_node_lattices): Likewise.
+	(ipcp_lattice::add_value): Likewise.
+	(propagate_vals_accross_pass_through): Renamed to ...
+	(propagate_vals_across_pass_through): ... this function.
+	(propagate_vals_accross_ancestor): Renamed to ...
+	(propagate_vals_across_ancestor): ... this.
+	(propagate_scalar_accross_jump_function): Renamed to ...
+	(propagate_scalar_across_jump_function): ... this.
+	Adjust calls to above functions.
+	(propagate_context_accross_jump_function): Renamed to ...
+	(propagate_context_across_jump_function): ... this.
+	(propagate_bits_accross_jump_function): Renamed to ...
+	(propagate_bits_accross_jump_function): ... this.  Formatting fixes.
+	(propagate_vr_accross_jump_function): Renamed to ...
+	(propagate_vr_across_jump_function): ... this.
+	(merge_agg_lats_step): Formatting fixes.
+	(propagate_constants_accross_call): Renamed to ...
+	(propagate_constants_across_call): ... this.  Adjust calls to above
+	functions.
+	(ipa_get_indirect_edge_target_1): Formatting fixes.
+	(gather_context_independent_values): Likewise.
+	(estimate_local_effects): Likewise.
+	(add_all_node_vals_to_toposort): Likewise.
+	(propagate_constants_topo): Adjust calls to above functions.
+	(get_replacement_map): Formatting fixes.
+	(dump_profile_updates): Likewise.
+	(update_profiling_info): Likewise.
+	(update_specialized_profile): Likewise.
+	(create_specialized_node): Likewise.
+	(find_more_contexts_for_caller_subset): Likewise.
+	(decide_whether_version_node): Likewise.
+	(identify_dead_nodes): Likewise.
+	(ipcp_decision_stage): Likewise.
+	(ipcp_store_bits_results): Likewise.
+	(ipcp_store_vr_results): Likewise.
+	(ipcp_driver): Likewise.
+
+2016-12-15  David Malcolm  <dmalcolm@redhat.com>
+
+	PR preprocessor/78680
+	PR preprocessor/78811
+	* input.c (struct selftest::lexer_test): Add field
+	m_implicitly_expect_EOF.
+	(selftest::lexer_error_sink): New class.
+	(selftest::lexer_error_sink::s_singleton): New global.
+	(selftest::lexer_test::lexer_test): Initialize new field
+	"m_implicitly_expect_EOF".
+	(selftest::lexer_test::~lexer_test): Conditionalize the
+	check for the EOF token on the new field.
+	(selftest::test_lexer_string_locations_raw_string_unterminated):
+	New function.
+	(selftest::input_c_tests): Call the new test.
+
+2016-12-15  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/arm/arm.h (TARGET_BACKTRACE): Use crtl->is_leaf.
+	* config/arm/arm.c (arm_option_check_internal): Improve comment.
+	(thumb_force_lr_save): Use crtl->is_leaf.
+	(arm_get_frame_offsets): Remove comment.  Use crtl->is_leaf.
+	(thumb_far_jump_used_p): Remove comment.
+	(arm_frame_pointer_required): Use crtl->is_leaf.
+
+2016-12-15  Jakub Jelinek  <jakub@redhat.com>
+
+	* doc/extend.texi: Clean up @xref{...} uses.
+	* doc/invoke.texi: Likewise.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-fpus.def: Add CNAME field to all FPU definitions.
+	* genopt.sh: Use explicit enumeration tags for FPU entries.
+	* arm-tables.opt: Regenerated.
+	* arm.opt (mfpu): Provide initial value.
+	* arm-opts.h (enum fpu_type): Build the enumeration from the list of
+	available FPUs.  Add 'auto' entry on the end.
+	* arm.c (arm_configure_build_target): Only do explicit configuration
+	of the FPU features if the selected FPU is not 'auto'.
+	(arm_option_override): Adjust initialization of arm_fpu_index.
+	Emit an error if we have a hard float ABI request, but the processor
+	does not support floating-point.
+	(arm_option_print): Handle -mfpu=auto.
+	(arm_valid_target_attribute_rec): Don't permit fpu=auto in pragmas
+	or function attributes.
+	(arm_identify_fpu_from_isa): Handle effective soft-float when
+	the FPU is automatically detected.
+	* arm-cores.def (arm1136jf-s): Add feature ISA_FP_DBL.
+	(arm1176jzf-s): Likewise.
+	(mpcore): Likewise.
+	(arm1156t2f-s): Likewise.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-fpus.def (ARM_FPU): Remove features field from all definitions.
+	* arm.h (arm_fpu_feature_set): Delete typedef.
+	(FPU_FL_NONE): Delete.
+	(FPU_FL_NEON): Delete.
+	(FPU_FL_FP16): Delete.
+	(FPU_FL_CRYPTO): Delete.
+	(FPU_FL_DBL): Delete.
+	(FPU_FL_D32): Delete.
+	(FPU_FL_VFPv2): Delete.
+	(FPU_FL_VFPv3): Delete.
+	(FPU_FL_VFPv4): Delete.
+	(FPU_FL_VFPv5): Delete.
+	(FPU_FL_AMRv8): Delete.
+	(FPU_VFPv2): Delete.
+	(FPU_VFPv3): Delete.
+	(FPU_VFPv4): Delete.
+	(FPU_VFPv5): Delete.
+	(FPU_ARMv8): Delete.
+	(FPU_DBL): Delete.
+	(FPU_D32): Delete.
+	(FPU_NEON): Delete.
+	(FPU_CRYPTO): Delete.
+	(FPU_FP16): Delete.
+	(arm_fpu_desc): Delete features field.
+	* arm.c (all_fpus): Don't initialize feature field.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.c (arm_can_inline_p): Use ISA features for determining
+	inlinability.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-protos.h (arm_configure_build_target): Change second argument
+	to cl_target_options.
+	* arm.c (arm_configure_build_target): Likewise.
+	(arm_option_restore): Update accordingly.
+	(arm_option_override): Create the target_option_default_node before
+	calling arm_configure_build_target.  Use it in call of latter.
+	Resynchronize after all other overrides have been calculated.
+	(arm_valid_target_attribute_tree): Use the target options for
+	reconfiguration.  Resynchronize after performing override checks.
+	* arm-c.c (arm_pragma_target_parse): Use target optiosn from cur_tree
+	to reconfigure the build target.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h (TARGET_VFPD32): Use arm_active_target.
+	(TARGET_VFP3): Likewise.
+	(TARGET_VFP5): Likewise.
+	(TARGET_VFP_SINGLE): Likewise.
+	(TARGET_VFP_DOUBLE): Likewise.
+	(TARGET_NEON_FP16): Likewise.
+	(TARGET_FP16): Likewise.
+	(TARGET_FMA): Likewise.
+	(TARGET_FPU_ARMV8): Likewise.
+	(TARGET_CRYPTO): Likewise.
+	(TARGET_NEON): Likewise.
+	(TARGET_FPU_FEATURES): Delete.
+	* arm.c (arm_option_check_internal): Check for iwmmxt conflict with
+	Neon using arm_active_target.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h (TARGET_FPU_NAME): Delete.
+	* arm.c (arm_identify_fpu_from_isa): New function.
+	(arm_declare_function_name): Use it to get the name for the FPU.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-protos.h: Include sbitmap.h
+	(arm_configure_build_target): Make public.
+	* arm.c (arm_configure_build_target): Now not static.
+	(arm_valid_target_attribute_rec): Move internal option check to...
+	(arm_valid_target_attribute_tree0: ... here.  Also reconfingure the
+	active target.
+	(arm_override_options_after_change): Call arm_configure_build_target.
+	(isa_all_fpubits): Renamed from isa_fpubits.
+	(arm_option_restore): New function.
+	(TARGET_OPTION_RESTORE): Register it.
+	(arm_configure_build_target): Initialize the FPU capability bits in
+	the isa.
+	(arm_option_override): Move the code that forces the setting of the
+	FPU option before the call to arm_configure_build_target.
+	* arm.opt (march): Mark as Save.
+	(mcpu, mtune): Likewise.
+	* arm-c.c (arm_pragma_target_parse): Reconfigure the build target
+	after pragmas change the target options.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-isa.h (isa_feature): Add bits for VFPv4, FPv5, fp16conv,
+	fP_dbl, fp_d32 and fp_crypto.
+	(ISA_ALL_FPU): Add all the new bits.
+	(ISA_VFPv2, ISA_VFPv3, ISA_VFPv4, ISA_FPv5): New macros.
+	(ISA_FP_ARMv8, ISA_FP_DBL, ISA_FP_D32, ISA_NEON, ISA_CRYPTO): Likewise.
+	* arm-fpus.def: Add ISA features to all FPUs.
+	* arm.h: (arm_fpu_desc): Add new field for ISA bits.
+	* arm.c (all_fpus): Initialize it.
+	* arm-tables.opt: Regenerated.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h (FPU_FL_VFPv2) New feature bit.
+	(FPU_FL_VFPv3, FPU_FL_VFPv4, FPU_FL_VFPv5, FPU_FL_ARMv8): Likewise.
+	(FPU_VFPv2, FPU_VFPv3, FPU_VFPv4, FPU_VFPv5, FPU_ARMv8): New helper
+	macros.
+	(FPU_DBL, FPU_D32, FPU_NEON, FPU_CRYPTO, FPU_FP16): Likewise.
+	(TARGET_FPU_REV): Delete.
+	(TARGET_VFP3): Use feature bits.
+	(TARGET_VFP5): Likewise.
+	(TARGET_FMA): Likewise.
+	(TARGET_FPU_ARMV8): Likewise.
+	(struct arm_fpu_desc): Delete rev field.
+	* arm-fpus.def: Delete REV entry, use new feature bits and macros.
+	* arm.c (all_fpus): Delete rev field.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h (vfp_reg_type): Delete.
+	(TARGET_FPU_REGS): Delete.
+	(arm_fpu_desc): Delete regs field.
+	(FPU_FL_NONE, FPU_FL_NEON, FPU_FL_FP16, FPU_FL_CRYPTO): Use unsigned
+	values.
+	(FPU_FL_DBL, FPU_FL_D32): Define.
+	(TARGET_VFPD32): Use feature test.
+	(TARGET_VFP_SINGLE): Likewise.
+	(TARGET_VFP_DOUBLE): Likewise.
+	* arm-fpus.def: Update all entries for new feature bits.
+	* arm.c (all_fpus): Update initializer macro.
+	(arm_can_inline_p): Remove test on fpu regs.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h (arm_fp_model): Delete.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-cores.def: Remove FLAGS field from all core definitions.
+	* arm-arches.def: Likewise.
+	* arm-opts.h (enum processor_type): Remove FLAGS parameter from
+	ARM_CORES macro.
+	(arm_arch_core_flags): Likewise, plus ARM_ARCH macro.
+	* arm-protos.h (FL_*): Delete.
+	(arm_feature_set): Delete.
+	(ARM_FSET_*): Delete.
+	* arm.c (struct processors): Delete flags field.
+	(all_cores): Delete FLAGS parameter from macro, don't initialize flags.
+	(all architectures): Likewise.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-opts.h (struct arm_arch_core_flag): Add new field ISA.
+	Initialize it.
+	(arm_arch_core_flag): Delete flags field.
+	(arm_arch_core_flags): Don't initialize flags field.
+	* common/config/arm/arm-common.c (check_isa_bits_for): New function.
+	(arm_target_thumb_only): Use new isa bits arrays.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-protos.h (insn_flags): Delete declaration.
+	(arm_arch7ve): Declare.
+	* arm.c (insn_flags): Delete.
+	(arm_arch7ve): New variable.
+	(arm_selected_cpu): Delete.
+	(arm_option_check_internal): Use new ISA bitmap.
+	(arm_option_override_internal): Likewise.
+	(arm_configure_build_target): Declare arm_selected_cpu locally.
+	(arm_option_override): Use new ISA bitmap.  Initialize arm_arch7ve.
+	Rearrange variable intialization by general function.
+	* arm.h (TARGET_HAVE_LPAE): Use arm_arch7ve.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-builtins.c: Include sbitmap.h.
+	(def_mbuiltin): Change first parameter to a flag bit.  Use it to test
+	available features in the current target.
+	(struct builtin_description): Change type of feature field.
+	(IWMMXT_BUILTIN): Use the isa_features types.
+	(IWMMXT2_BUILTIN): Likewise.
+	(IWMMXT_BUILTIN2): Likewise.
+	(IWMMXT2_BUILTIN2): Likewise.
+	(CRC32_BUILTIN): Likewise.
+	(CRYPTO_BUILTIN): Likewise.
+	(iwmmx_builtin): Likewise.
+	(iwmmx2_builtin): Likewise.
+	(arm_iwmmxt_builtin): Check for specific feature bits.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd.
+	(ISA_ALL_QUIRKS): New macro.
+	* arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list.
+	* arm.c (isa_quirkbits): New feature-list bitmap.
+	(arm_configure_build_target): Ignore quirk bits when comparing an
+	architecture feature list with a CPU feature list.
+	(arm_option_override): Initialize_isa_quirkbits.  If the user has
+	not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the
+	feature if isa_quirk_cm3_ldrd appears in the isa feature list.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.c (arm_option_override): Use arm_active_target as source of
+	information for arm_base_arch and arm_arch_name.
+	* (arm_file_start): Use arm_active_target for core name.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.c (arm_selected_tune): Delete static variable.
+	(arm_selected_arch): Likewise.
+	(arm_configure_build_target): Declare local versions of arm_selected
+	target and arm_selected_arch.  Initialize more fields in target
+	data structure.
+	(arm_option_override): Use arm_active_target instead of
+	arm_selected_tune and arm_selected_arch.
+	(asm_file_start): Use arm_active_target.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-protos.h (arm_build_target): New structure.
+	(arm_active_target): Declare it.
+	* arm.c (arm_active_target): New variable.
+	(bitmap_popcount): New function.
+	(feature_count): Delete.
+	(arm_initialize_isa): New function.
+	isa_fpubits): New variable.
+	(arm_configure_build_target): New function.
+	(arm_option_override): Initialize isa_fpubits and arm_active_target.isa.
+	Use arm_configure_build_target.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-isa.h: New file.
+	* arm-protos.h: Include it.
+	* arm-arches.def: Add new ISA field to all entries.  Drop bogus
+	armv8.1-a+crc architecture.
+	* arm-cores.def: Similarly.  Group ARMv8 cores by profile.
+	* arm-opts.h (enum processor_type): Adjust for new field.
+	* arm.c (struct processors): New field 'isa_bits'.
+	(all_cores, all_architectures): Initialize new field.
+	* arm-tables.opt: Regenerated.
+	* arm-tune.md: Regenerated.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-arches.def (ARM_ARCH): Add extra field TUNE_FLAGS, move
+	tuning properties from architectural FLAGS field.
+	* arm-cores.def (ARM_CORE): Likewise.
+	* arm-protos.h (TF_LDSCHED, TF_WBUF, TF_CO_PROC): New macros.
+	(TF_SMALLMUL, TF_STRONG, TF_SCALE, TF_NOMODE32): New macros.
+	(FL_LDSCHED, FL_STRONG, FL_WBUF, FL_SMALLMUL): Delete.
+	(FL_TUNE): Remove deleted elements.
+	(tune_flags): Convert type to unsigned int.
+	* arm.c (struct processors): Add new field tune_flags.
+	(all_cores, all_arches): Initialize it.
+	(arm_option_override): Adapt uses of tune_flags.  Use tune_flags
+	for deciding when we should have slow multiply operations.
+
+2016-12-14  Martin Sebor  <msebor@redhat.com>
+
+	PR middle-end/78519
+	* gimple-ssa-sprintf.c (format_string): Handle null pointers.
+	(format_directive): Diagnose null pointer arguments.
+	(pass_sprintf_length::handle_gimple_call): Diagnose null destination
+	pointers.  Correct location of null format string in diagnostics.
+
+2016-12-14  David Malcolm  <dmalcolm@redhat.com>
+
+	* Makefile.in (SELFTEST_FLAGS): Add path argument to -fself-test.
+	(s-selftest): Add dependency on the selftests data directory.
+	* common.opt (fself-test): Rename to...
+	(fself-test=): ...this, documenting the meaning of the argument.
+	* selftest-run-tests.c (along): Likewise.
+	* selftest-run-tests.c: Include "options.h".
+	(selftest::run_tests): Initialize selftest::path_to_selftest_files
+	from flag_self_test.
+	* selftest.c (selftest::path_to_selftest_files): New global.
+	(selftest::locate_file): New function.
+	(selftest::test_locate_file): New function.
+	(selftest_c_tests): Likewise.
+	(selftest::selftest_c_tests): Call test_locate_file.
+	* selftest.h (selftest::locate_file): New decl.
+	(selftest::path_to_selftest_files): New decl.
+
+2016-12-14  Andrew Pinski  <apinski@cavium.com>
+
+	* config/aarch64/aarch64-cores.def: Add -1 as the variant to all
+	of the cores.
+	(thunderx): Update to include LSE by default.
+	(thunderxt88p1): New core.
+	(thunderxt88): New core.
+	(thunderxt81): New core.
+	(thunderxt83): New core.
+	* config/aarch64/driver-aarch64.c (struct aarch64_core_data):
+	Add variant field.
+	(ALL_VARIANTS): New define.
+	(AARCH64_CORE): Support VARIANT operand.
+	(cpu_data): Likewise.
+	(host_detect_local_cpu): Parse variant field of /proc/cpuinfo.
+	Combine the arch and single core case and support variant searching.
+	* common/config/aarch64/aarch64-common.c (AARCH64_CORE):
+	Add VARIANT operand.
+	* config/aarch64/aarch64-opts.h (AARCH64_CORE): Likewise.
+	* config/aarch64/aarch64.c (AARCH64_CORE): Likewise.
+	* config/aarch64/aarch64.h (AARCH64_CORE): Likewise.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi (AARCH64/mtune): Document thunderxt88,
+	thunderxt88p1, thunderxt81, thunderxt83 as available options.
+
+2016-12-14  Martin Jambor  <mjambor@suse.cz>
+
+	* omp-offload.c: Fix coding style.
+	* omp-expand.c: Likewise.
+	* omp-general.c: Likewise.
+	* omp-grid.c: Likewise.
+	* omp-low.c: Fix coding style of parts touched by the
+	previous splitting patch.
+
+2016-12-14  Martin Jambor  <mjambor@suse.cz>
+
+	* omp-general.h: New file.
+	* omp-general.c: New file.
+	* omp-expand.h: Likewise.
+	* omp-expand.c: Likewise.
+	* omp-offload.h: Likewise.
+	* omp-offload.c: Likewise.
+	* omp-grid.c: Likewise.
+	* omp-grid.c: Likewise.
+	* omp-low.h: Include omp-general.h and omp-grid.h.  Removed includes
+	of params.h, symbol-summary.h, lto-section-names.h, cilk.h, tree-eh.h,
+	ipa-prop.h, tree-cfgcleanup.h, cfgloop.h, except.h, expr.h, stmt.h,
+	varasm.h, calls.h, explow.h, dojump.h, flags.h, tree-into-ssa.h,
+	tree-cfg.h, cfganal.h, alias.h, emit-rtl.h, optabs.h, expmed.h,
+	alloc-pool.h, cfghooks.h, rtl.h and memmodel.h.
+	(omp_find_combined_for): Declare.
+	(find_omp_clause): Renamed to omp_find_clause and moved to
+	omp-general.h.
+	(free_omp_regions): Renamed to omp_free_regions and moved to
+	omp-expand.h.
+	(replace_oacc_fn_attrib): Renamed to oacc_replace_fn_attrib and moved
+	to omp-general.h.
+	(set_oacc_fn_attrib): Renamed to oacc_set_fn_attrib and moved to
+	omp-general.h.
+	(build_oacc_routine_dims): Renamed to oacc_build_routine_dims and
+	moved to omp-general.h.
+	(get_oacc_fn_attrib): Renamed to oacc_get_fn_attrib and moved to
+	omp-general.h.
+	(oacc_fn_attrib_kernels_p): Moved to omp-general.h.
+	(get_oacc_fn_dim_size): Renamed to oacc_get_fn_dim_size and moved to
+	omp-general.c.
+	(omp_expand_local): Moved to omp-expand.h.
+	(make_gimple_omp_edges): Renamed to omp_make_gimple_edges and moved to
+	omp-expand.h.
+	(omp_finish_file): Moved to omp-offload.h.
+	(default_goacc_validate_dims): Renamed to
+	oacc_default_goacc_validate_dims and moved to omp-offload.h.
+	(offload_funcs, offload_vars): Moved to omp-offload.h.
+	* omp-low.c: Include omp-general.h, omp-offload.h and omp-grid.h.
+	(omp_region): Moved to omp-expand.c.
+	(omp_for_data_loop): Moved to omp-general.h.
+	(omp_for_data): Likewise.
+	(oacc_loop): Moved to omp-offload.c.
+	(oacc_loop_flags): Moved to omp-general.h.
+	(offload_funcs, offload_vars): Moved to omp-offload.c.
+	(root_omp_region): Moved to omp-expand.c.
+	(omp_any_child_fn_dumped): Likewise.
+	(find_omp_clause): Renamed to omp_find_clause and moved to
+	omp-general.c.
+	(is_combined_parallel): Moved to omp-expand.c.
+	(is_reference): Renamed to omp_is_reference and and moved to
+	omp-general.c.
+	(adjust_for_condition): Renamed to omp_adjust_for_condition and moved
+	to omp-general.c.
+	(get_omp_for_step_from_incr): Renamed to omp_get_for_step_from_incr
+	and moved to omp-general.c.
+	(extract_omp_for_data): Renamed to omp_extract_for_data and moved to
+	omp-general.c.
+	(workshare_safe_to_combine_p): Moved to omp-expand.c.
+	(omp_adjust_chunk_size): Likewise.
+	(get_ws_args_for): Likewise.
+	(get_base_type): Removed.
+	(dump_omp_region): Moved to omp-expand.c.
+	(debug_omp_region): Likewise.
+	(debug_all_omp_regions): Likewise.
+	(new_omp_region): Likewise.
+	(free_omp_region_1): Likewise.
+	(free_omp_regions): Renamed to omp_free_regions and moved to
+	omp-expand.c.
+	(find_combined_for): Renamed to omp_find_combined_for, made global.
+	(build_omp_barrier): Renamed to omp_build_barrier and moved to
+	omp-general.c.
+	(omp_max_vf): Moved to omp-general.c.
+	(omp_max_simt_vf): Likewise.
+	(gimple_build_cond_empty): Moved to omp-expand.c.
+	(parallel_needs_hsa_kernel_p): Likewise.
+	(expand_omp_build_assign): Moved declaration to omp-expand.c.
+	(expand_parallel_call): Moved to omp-expand.c.
+	(expand_cilk_for_call): Likewise.
+	(expand_task_call): Likewise.
+	(vec2chain): Likewise.
+	(remove_exit_barrier): Likewise.
+	(remove_exit_barriers): Likewise.
+	(optimize_omp_library_calls): Likewise.
+	(expand_omp_regimplify_p): Likewise.
+	(expand_omp_build_assign): Likewise.
+	(expand_omp_taskreg): Likewise.
+	(oacc_collapse): Likewise.
+	(expand_oacc_collapse_init): Likewise.
+	(expand_oacc_collapse_vars): Likewise.
+	(expand_omp_for_init_counts): Likewise.
+	(expand_omp_for_init_vars): Likewise.
+	(extract_omp_for_update_vars): Likewise.
+	(expand_omp_ordered_source): Likewise.
+	(expand_omp_ordered_sink): Likewise.
+	(expand_omp_ordered_source_sink): Likewise.
+	(expand_omp_for_ordered_loops): Likewise.
+	(expand_omp_for_generic): Likewise.
+	(expand_omp_for_static_nochunk): Likewise.
+	(find_phi_with_arg_on_edge): Likewise.
+	(expand_omp_for_static_chunk): Likewise.
+	(expand_cilk_for): Likewise.
+	(expand_omp_simd): Likewise.
+	(expand_omp_taskloop_for_outer): Likewise.
+	(expand_omp_taskloop_for_inner): Likewise.
+	(expand_oacc_for): Likewise.
+	(expand_omp_for): Likewise.
+	(expand_omp_sections): Likewise.
+	(expand_omp_single): Likewise.
+	(expand_omp_synch): Likewise.
+	(expand_omp_atomic_load): Likewise.
+	(expand_omp_atomic_store): Likewise.
+	(expand_omp_atomic_fetch_op): Likewise.
+	(expand_omp_atomic_pipeline): Likewise.
+	(expand_omp_atomic_mutex): Likewise.
+	(expand_omp_atomic): Likewise.
+	(oacc_launch_pack): and moved to omp-general.c, made public.
+	(OACC_FN_ATTRIB): Likewise.
+	(replace_oacc_fn_attrib): Renamed to oacc_replace_fn_attrib and moved
+	to omp-general.c.
+	(set_oacc_fn_attrib): Renamed to oacc_set_fn_attrib and moved to
+	omp-general.c.
+	(build_oacc_routine_dims): Renamed to oacc_build_routine_dims and
+	moved to omp-general.c.
+	(get_oacc_fn_attrib): Renamed to oacc_get_fn_attrib and moved to
+	omp-general.c.
+	(oacc_fn_attrib_kernels_p): Moved to omp-general.c.
+	(oacc_fn_attrib_level): Moved to omp-offload.c.
+	(get_oacc_fn_dim_size): Renamed to oacc_get_fn_dim_size and moved to
+	omp-general.c.
+	(get_oacc_ifn_dim_arg): Renamed to oacc_get_ifn_dim_arg and moved to
+	omp-general.c.
+	(mark_loops_in_oacc_kernels_region): Moved to omp-expand.c.
+	(grid_launch_attributes_trees): Likewise.
+	(grid_attr_trees): Likewise.
+	(grid_create_kernel_launch_attr_types): Likewise.
+	(grid_insert_store_range_dim): Likewise.
+	(grid_get_kernel_launch_attributes): Likewise.
+	(get_target_argument_identifier_1): Likewise.
+	(get_target_argument_identifier): Likewise.
+	(get_target_argument_value): Likewise.
+	(push_target_argument_according_to_value): Likewise.
+	(get_target_arguments): Likewise.
+	(expand_omp_target): Likewise.
+	(grid_expand_omp_for_loop): Moved to omp-grid.c.
+	(grid_arg_decl_map): Likewise.
+	(grid_remap_kernel_arg_accesses): Likewise.
+	(grid_expand_target_grid_body): Likewise.
+	(expand_omp): Renamed to omp_expand and moved to omp-expand.c.
+	(build_omp_regions_1): Moved to omp-expand.c.
+	(build_omp_regions_root): Likewise.
+	(omp_expand_local): Likewise.
+	(build_omp_regions): Likewise.
+	(execute_expand_omp): Likewise.
+	(pass_data_expand_omp): Likewise.
+	(pass_expand_omp): Likewise.
+	(make_pass_expand_omp): Likewise.
+	(pass_data_expand_omp_ssa): Likewise.
+	(pass_expand_omp_ssa): Likewise.
+	(make_pass_expand_omp_ssa): Likewise.
+	(grid_lastprivate_predicate): Renamed to
+	omp_grid_lastprivate_predicate and moved to omp-grid.c, made public.
+	(grid_prop): Moved to omp-grid.c.
+	(GRID_MISSED_MSG_PREFIX): Likewise.
+	(grid_safe_assignment_p): Likewise.
+	(grid_seq_only_contains_local_assignments): Likewise.
+	(grid_find_single_omp_among_assignments_1): Likewise.
+	(grid_find_single_omp_among_assignments): Likewise.
+	(grid_find_ungridifiable_statement): Likewise.
+	(grid_parallel_clauses_gridifiable): Likewise.
+	(grid_inner_loop_gridifiable_p): Likewise.
+	(grid_dist_follows_simple_pattern): Likewise.
+	(grid_gfor_follows_tiling_pattern): Likewise.
+	(grid_call_permissible_in_distribute_p): Likewise.
+	(grid_handle_call_in_distribute): Likewise.
+	(grid_dist_follows_tiling_pattern): Likewise.
+	(grid_target_follows_gridifiable_pattern): Likewise.
+	(grid_remap_prebody_decls): Likewise.
+	(grid_var_segment): Likewise.
+	(grid_mark_variable_segment): Likewise.
+	(grid_copy_leading_local_assignments): Likewise.
+	(grid_process_grid_body): Likewise.
+	(grid_eliminate_combined_simd_part): Likewise.
+	(grid_mark_tiling_loops): Likewise.
+	(grid_mark_tiling_parallels_and_loops): Likewise.
+	(grid_process_kernel_body_copy): Likewise.
+	(grid_attempt_target_gridification): Likewise.
+	(grid_gridify_all_targets_stmt): Likewise.
+	(grid_gridify_all_targets): Renamed to omp_grid_gridify_all_targets
+	and moved to omp-grid.c, made public.
+	(make_gimple_omp_edges): Renamed to omp_make_gimple_edges and moved to
+	omp-expand.c.
+	(add_decls_addresses_to_decl_constructor): Moved to omp-offload.c.
+	(omp_finish_file): Likewise.
+	(oacc_thread_numbers): Likewise.
+	(oacc_xform_loop): Likewise.
+	(oacc_default_dims, oacc_min_dims): Likewise.
+	(oacc_parse_default_dims): Likewise.
+	(oacc_validate_dims): Likewise.
+	(new_oacc_loop_raw): Likewise.
+	(new_oacc_loop_outer): Likewise.
+	(new_oacc_loop): Likewise.
+	(new_oacc_loop_routine): Likewise.
+	(finish_oacc_loop): Likewise.
+	(free_oacc_loop): Likewise.
+	(dump_oacc_loop_part): Likewise.
+	(dump_oacc_loop): Likewise.
+	(debug_oacc_loop): Likewise.
+	(oacc_loop_discover_walk): Likewise.
+	(oacc_loop_sibling_nreverse): Likewise.
+	(oacc_loop_discovery): Likewise.
+	(oacc_loop_xform_head_tail): Likewise.
+	(oacc_loop_xform_loop): Likewise.
+	(oacc_loop_process): Likewise.
+	(oacc_loop_fixed_partitions): Likewise.
+	(oacc_loop_auto_partitions): Likewise.
+	(oacc_loop_partition): Likewise.
+	(default_goacc_fork_join): Likewise.
+	(default_goacc_reduction): Likewise.
+	(execute_oacc_device_lower): Likewise.
+	(default_goacc_validate_dims): Likewise.
+	(default_goacc_dim_limit): Likewise.
+	(pass_data_oacc_device_lower): Likewise.
+	(pass_oacc_device_lower): Likewise.
+	(make_pass_oacc_device_lower): Likewise.
+	(execute_omp_device_lower): Likewise.
+	(pass_data_omp_device_lower): Likewise.
+	(pass_omp_device_lower): Likewise.
+	(make_pass_omp_device_lower): Likewise.
+	(pass_data_omp_target_link): Likewise.
+	(pass_omp_target_link): Likewise.
+	(find_link_var_op): Likewise.
+	(pass_omp_target_link::execute): Likewise.
+	(make_pass_omp_target_link): Likewise.
+	* Makefile.in (OBJS): Added omp-offload.o, omp-expand.o, omp-general.o
+	and omp-grid.o.
+	(GTFILES): Added omp-offload.h, omp-offload.c and omp-expand.c, removed
+	omp-low.h.
+	* gimple-fold.c: Include omp-general.h instead of omp-low.h.
+	(fold_internal_goacc_dim): Adjusted calls to
+	get_oacc_ifn_dim_arg and get_oacc_fn_dim_size to use their new names.
+	* gimplify.c: Include omp-low.h.
+	(omp_notice_variable): Adjust the call to get_oacc_fn_attrib to use
+	its new name.
+	(gimplify_omp_task): Adjusted calls to find_omp_clause to use its new
+	name.
+	(gimplify_omp_for): Likewise.
+	* lto-cgraph.c: Include omp-offload.h instead of omp-low.h.
+	* toplev.c: Include omp-offload.h instead of omp-low.h.
+	* tree-cfg.c: Include omp-general.h instead of omp-low.h.  Also
+	include omp-expand.h.
+	(make_edges_bb): Adjusted the call to make_gimple_omp_edges to use its
+	new name.
+	(make_edges): Adjust the call to free_omp_regions to use its new name.
+	* tree-parloops.c: Include omp-general.h.
+	(create_parallel_loop): Adjusted the call to set_oacc_fn_attrib to use
+	its new name.
+	(parallelize_loops): Adjusted the call to get_oacc_fn_attrib to use
+	its new name.
+	* tree-ssa-loop.c: Include omp-general.h instead of omp-low.h.
+	(gate_oacc_kernels): Adjusted the call to get_oacc_fn_attrib to use
+	its new name.
+	* tree-vrp.c: Include omp-general.h instead of omp-low.h.
+	(extract_range_basic): Adjusted calls to get_oacc_ifn_dim_arg and
+	get_oacc_fn_dim_size to use their new names.
+	* varpool.c: Include omp-offload.h instead of omp-low.h.
+	* gengtype.c (open_base_files): Replace omp-low.h with omp-offload.h in
+	ifiles.
+	* config/nvptx/nvptx.c: Include omp-general.c.
+	(nvptx_expand_call): Adjusted the call to get_oacc_fn_attrib to use
+	its new name.
+	(nvptx_reorg): Likewise.
+	(nvptx_record_offload_symbol): Likewise.
+
+2016-12-14  Martin Sebor  <msebor@redhat.com>
+
+	PR middle-end/78786
+	* gimple-ssa-sprintf.c (target_dir_max): New macro.
+	(get_mpfr_format_length): New function.
+	(format_integer): Use HOST_WIDE_INT instead of int.
+	(format_floating_max): Same.
+	(format_floating): Call get_mpfr_format_length.
+	(format_directive): Use target_dir_max.
+
+2016-12-14  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/78791
+	* config/i386/i386.h (enum ix86_stack_slot): Add SLOT_STV_TEMP.
+	* config/i386/i386.c (dimode_scalar_chain::make_vector_copies,
+	dimode_scalar_chain::convert_reg): Use SLOT_STV_TEMP instead of
+	SLOT_TEMP.
+
+2016-12-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/59874
+	* config/i386/i386-builtin.def: Add __builtin_clzs and __builtin_ctzs.
+	(ix86_fold_builtin): Handle IX86_BUILTIN_CTZS and IX86_BUILTIN_CLZS.
+	* config/i386/i386.md (*ctzhi2): New insn_and_split pattern.
+	(*clzhi2): Ditto.
+
+2016-12-14  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/77844
+	* valtrack.c: Include rtl-iter.h.
+	(struct rtx_subst_pair): Add insn field.
+	(propagate_for_debug_subst): If pair->to contains at least 2
+	regs, create a DEBUG_INSN with a debug temp before pair->insn
+	and replace from with the debug temp instead of pair->to.
+	(propagate_for_debug): Initialize p.insn.
+	* combine.c (insn_uid_check): New inline function.
+	(INSN_COST, LOG_LINKS): Use it instead of INSN_UID.
+	(find_single_use, combine_instructions,
+	cant_combine_insn_p, try_combine): Use NONDEBUG_INSN_P instead of
+	INSN_P.
+
+2016-12-14  Martin Sebor  <msebor@redhat.com>
+
+	PR c/17308
+	* builtin-attrs.def (ATTR_NONNULL_1_1, ATTR_NONNULL_1_2): Defined.
+	(ATTR_NONNULL_1_3, ATTR_NONNULL_1_4, ATTR_NONNULL_1_5): Same.
+	(ATTR_NOTHROW_NONNULL_1_1, ATTR_NOTHROW_NONNULL_1_2): Same.
+	(ATTR_NOTHROW_NONNULL_1_3, ATTR_NOTHROW_NONNULL_1_4): Same.
+	(ATTR_NOTHROW_NONNULL_1_5): Same.
+	(ATTR_NONNULL_1_FORMAT_PRINTF_1_2): Same.
+	(ATTR_NONNULL_1_FORMAT_PRINTF_2_0): Same.
+	(ATTR_NONNULL_1_FORMAT_PRINTF_2_3): Same.
+	(ATTR_NONNULL_1_FORMAT_PRINTF_3_0): Same.
+	(ATTR_NONNULL_1_FORMAT_PRINTF_3_4): Same.
+	(ATTR_NONNULL_1_FORMAT_PRINTF_4_0): Same.
+	(ATTR_NONNULL_1_FORMAT_PRINTF_4_5): Same.
+	* builtins.c (validate_arg): Add argument.  Treat null pointers
+	passed to nonnull arguments as invalid.
+	(validate_arglist): Same.
+	* builtins.def (fprintf, fprintf_unlocked): Add nonnull attribute.
+	(printf, printf_unlocked, sprintf. vfprintf, vsprintf): Same.
+	(__sprintf_chk, __vsprintf_chk, __fprintf_chk, __vfprintf_chk): Same.
+	* calls.c (get_nonnull_ags, maybe_warn_null_arg): New functions.
+	(initialize_argument_information): Diagnose null pointers passed to
+	arguments declared nonnull.
+	* calls.h (get_nonnull_args): Declared.
+
+2016-12-14  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000.c (rs6000_split_vec_extract_var): On ISA
+	3.0/power9, add support to use the VEXTU{B,H,W}{L,R}X extract
+	instructions.
+	* config/rs6000/vsx.md (VSr2): Add IEEE 128-bit floating point
+	type constraint registers.
+	(VSr3): Likewise.
+	(FL_CONV): New mode iterator for binary floating types that have a
+	direct conversion from 64-bit integer to floating point.
+	(vsx_extract_<mode>_p9): Add support for the ISA 3.0/power9
+	VEXTU{B,H,W}{L,R}X extract instructions.
+	(vsx_extract_<mode>_p9 splitter): Add splitter to load up the
+	extract byte position into the GPR if we are using the
+	VEXTU{B,H,W}{L,R}X extract instructions.
+	(vsx_extract_<mode>_di_p9): Support extracts to GPRs.
+	(vsx_extract_<mode>_store_p9): Support extracting to GPRs so that
+	we can use reg+offset address instructions.
+	(vsx_extract_<mode>_var): Support extracts to GPRs.
+	(vsx_extract_<VSX_EXTRACT_I:mode>_<SDI:mode>_var): New combiner
+	insn to combine vector extracts with zero_extend.
+	(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Optimize
+	extracting a small integer vector element and converting it to a
+	floating point type.
+	(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise.
+	(UNSPEC_XXEXTRACTUW): New unspec.
+	(UNSPEC_XXINSERTW): Likewise.
+	(vextract4b): Add support for the vec_vextract4b built-in
+	function.
+	(vextract4b_internal): Likewise.
+	(vinsert4b): Add support for the vec_insert4b built-in function.
+	Include both a version that inserts element 1 from a V4SI object
+	and one that inserts a DI object.
+	(vinsert4b_internal): Likewise.
+	(vinsert4b_di): Likewise.
+	(vinsert4b_di_internal): Likewise.
+	* config/rs6000/predicates.md (const_0_to_11_operand): New
+	predicate, match 0..11.
+	* config/rs6000/rs6000-builtin.def (BU_P9V_VSX_3): Set built-in
+	type to ternary, not binary.
+	(BU_P9V_64BIT_VSX_3): Likewise.
+	(P9V_BUILTIN_VEXTRACT4B): Add support for vec_vinsert4b and
+	vec_extract4b non-overloaded built-in functions.
+	(P9V_BUILTIN_VINSERT4B): Likewise.
+	(P9V_BUILTIN_VINSERT4B_DI): Likewise.
+	(P9V_BUILTIN_VEC_VEXTULX): Move to section that adds 2 operand ISA
+	3.0 built-in functions.
+	(P9V_BUILTIN_VEC_VEXTURX): Likewise.
+	(P9V_BUILTIN_VEC_VEXTRACT4B): Add support for overloaded
+	vec_insert4b and vec_extract4 built-in functions.
+	(P9V_BUILTIN_VEC_VINSERT4B): Likewise.
+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+	overloaded support for vec_vinsert4b and vec_extract4b.
+	* config/rs6000/rs6000.c (altivec_expand_builtin): Add checks for
+	the vec_insert4b and vec_extract4b byte number being a constant in
+	the range 0..11.
+	* config/rs6000/altivec.h (vec_vinsert4b): Support vec_vinsert4b
+	and vec_extract4b built-in functions.
+	* doc/extend.doc (PowerPC VSX built-in functions): Document
+	vec_insert4b and vec_extract4b.
+
+2016-12-14  Martin Liska  <mliska@suse.cz>
+
+	* gimple-pretty-print.c (dump_probability): New function.
+	(dump_edge_probability): Use the function.
+	(dump_gimple_label): Likewise.
+	(dump_gimple_bb_header): Likewise.
+
+2016-12-14  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	* tree-ssa-strlen.c (fold_strstr_to_memcmp): New function.
+	(strlen_optimize_stmt): Call fold_strstr_to_memcmp.
+
+2016-12-14  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* lra-constraints.c (process_address_1): Do not attempt to decompose
+	addresses for MEMs that satisfy fixed-form constraints.
+
+2016-12-14  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78788
+	* tree-vrp.c (set_value_range): Allow [-INF(OVF), +INF(OVF)].
+	(set_and_canonicalize_value_range): Do not drop the above to
+	VARYING.
+
+2016-12-13  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* config/rs6000/rs600.c (rs6000_builtin_vectorization_cost):
+	Adjust unaligned load cost.
+
+2016-12-13  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78794
+	* config/i386/i386.c (dimode_scalar_chain::compute_convert_gain):
+	Calculate additional gain for andnot for targets without BMI.
+
+2016-12-13  Carl Love  <cel@us.ibm.com>
+
+	* config/rs6000/rs6000-c.c: Add built-in support for
+	vector float vec_pack (vector double, vector double)
+	vector double vec_sld (vector double, vector double)
+	* config/rs6000/rs6000.c: Add icode check for vsldoi_v2df to allow
+	4-bit unsigned literal.
+	* config/rs6000/rs6000-builtin.def: Add definition for VSLDOI_2DF
+	* doc/extend.texi: Update the built-in documentation file for the
+	new powerpc vec_pack and vec_sld built-ins.
+
+2016-12-13  Martin Liska  <mliska@suse.cz>
+
+	* sanopt.c (sanopt_optimize_walker): Set contains_asan_mark.
+	(sanopt_optimize): Add new argument.
+	(sanitize_asan_mark_unpoison): New function.
+	(maybe_contains_asan_check): Likewise.
+	(sanitize_asan_mark_poison): Likewise.
+	(pass_sanopt::execute): Call the new functions.
+
+2016-12-13  Martin Liska  <mliska@suse.cz>
+
+	PR tree-optimization/78428
+	* expr.c (store_constructor_field): Add new arguments to the function.
+	(store_constructor): Set up bitregion_end and add gcc_unreachable to
+	fields that have either non-constant size or (and) offset.
+
+2016-12-13  Marek Polacek  <polacek@redhat.com>
+
+	* tree-data-ref.c (compute_overlap_steps_for_affine_univar): Change
+	parameters' type from int to HOST_WIDE_INT.
+	(compute_overlap_steps_for_affine_1_2): Change parameters' type from
+	int to HOST_WIDE_INT.
+	(build_classic_dist_vector_1): Likewise.
+	(add_multivariate_self_dist): Likewise.
+
+2016-12-13  Michael Matz  <matz@suse.de>
+
+	PR tree-optimization/78725
+	* tree-ssa-loop-split.c (split_at_bb_p): Check for overflow and
+	at correct use point.
+
+2016-12-13  Martin Liska  <mliska@suse.cz>
+
+	* asan.c (asan_expand_mark_ifn): Use renamed
+	BUILT_IN_ASAN_{UN}CLOBBER_N to BUILT_IN_ASAN_{UN}POISON_STACK_MEMORY.
+	* sanitizer.def: Likewise.
+
+2016-12-13  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* doc/extend.texi (Half-Precision): Update to document current
+	compiler behaviour.
+
+2016-12-13  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* doc/extend.texi (Floating Types): Document availability of
+	_Float16 on ARM/AArch64.
+
+2016-12-13  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78699
+	* tree-vect-data-refs.c (vect_analyze_group_access_1): Limit
+	group size.
+
+2016-12-13  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/78742
+	* tree.c (cst_and_fits_in_hwi): Look if the actual value fits.
+	* tree-object-size.c (compute_builtin_object_size): Use
+	tree_fits_shwi_p.
+	* tree-data-ref.c (initialize_matrix_A): Remove excess assert.
+
+2016-12-13  Martin Liska  <mliska@suse.cz>
+
+	* asan.c (asan_mark_poison_p): Remove.
+	(asan_mark_p): New function.
+	(transform_statements): Use the function.
+	(asan_expand_mark_ifn): Do not use masked enum.
+	* asan.h (enum asan_mark_flags): Declare it via a macro.
+	* gimple-pretty-print.c (dump_gimple_call_args): Dump first
+	argument of ASAN_MARK.
+	* gimplify.c (build_asan_poison_call_expr): Use new enum values.
+	(asan_poison_variable): Likewise.
+
+2016-12-13  Jakub Jelinek  <jakub@redhat.com>
+
+	PR ipa/77905
+	* ipa-pure-const.c (cdtor_p): Return true for
+	DECL_STATIC_{CON,DE}STRUCTOR even when it is
+	DECL_LOOPING_CONST_OR_PURE_P.
+
+2016-12-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/78777
+	* gimple-ssa-strength-reduction.c (create_add_on_incoming_edge,
+	insert_initializers): Use stmt_ends_bb_p instead of is_ctrl_stmt.
+
+	PR other/78766
+	* opt-functions.awk (opt_args): Use [{] instead of { in regexps.
+	Formatting fix.
+
+2016-12-12  Martin Sebor  <msebor@redhat.com>
+
+	PR middle-end/78622
+	PR middle-end78606
+	* gimple-ssa-sprintf.c (min_bytes_remaining): Use res.knownrange
+	rather than res.bounded.
+	(get_width_and_precision): Set precision to -1 when negative.
+	(adjust_range_for_overflow): New function.
+	(format_integer): Correct the handling of the space, plus, and pound
+	flags, and the special case of zero precision.
+	Always set res.bounded to true unless either precision or width
+	is specified and unknown.
+	Call adjust_range_for_overflow.
+	Avoid use zero as the shortest value when precision is specified
+	but unknown.
+	(format_directive): Remove vestigial quoting.  Always inform of
+	argument value or range when it's available.
+	(add_bytes): Correct the computation of boundrange used to
+	decide whether a warning is of a "maybe" or "defnitely" kind.
+
+2016-12-12  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	* combine.c (change_zero_ext): Handle mode expanding zero_extracts.
+
+2016-12-12  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78738
+	* config/i386/i386.h (X87_ENABLE_ARITH): Also enable for
+	flag_unsafe_math_optimizations.
+	(X87_ENABLE_FLOAT): Ditto.
+
+2016-12-12  Marek Polacek  <polacek@redhat.com>
+
+	PR middle-end/78716
+	* gimplify.c (gimplify_va_arg_expr): Don't require ADDR_EXPR for
+	Case 1; check POINTER_TYPE_P instead.
+
+2016-12-12  Bernd Schmidt  <bschmidt@redhat.com>
+
+	PR rtl-optimization/78669
+	* ira.c (combine_and_move_insns): When deleting an insn, clear the
+	replace flag for all used regs in that insn.
+
+2016-12-12  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm-opts.h: Move struct arm_arch_core_flag and
+	arm_arch_core_flags to ...
+	* common/config/arm/arm-common.c: There.
+
+2016-12-12  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/constraints.md (T): Use special memory constraint.
+	(U): Minor tweak.
+	(W): Add TARGET_ARCH64 test.
+	* config/sparc/sparc.md (*movdi_insn_sp32): Replace 'W' with 'T'.
+	(*movdf_insn_sp32): Likewise.
+	(*mov<VM64:mode>_insn_sp32): Likewise.  Replace 'e' with 'f' in
+	conjunction with offsettable memory references.
+
+2016-12-11  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* config/nios2/nios2.c (nios2_emit_move_sequence): Call copy_rtx
+	to avoid shared structure error.
+
+2016-12-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	PR target/78695
+	* config/rs6000/rs6000.c (find_alignment_op): Discard from
+	consideration any artificial definition.
+
+2016-12-11  Iain Sandoe  <iain@codesourcery.com>
+
+	* configure.ac (CROSS directory tests): Remove the assumption that
+	Darwin hosts contain suitable target sysroots in "/".
+	* configure: Regenerate.
+
+2016-12-11  Iain Sandoe  <iain@codesourcery.com>
+
+	PR rtl-optimization/71496
+	* config/rs6000/darwin.md (load_macho_picbase_si): Mark as non-
+	copyable.  (load_macho_picbase_di, reload_macho_picbase_si,
+	reload_macho_picbase_di): Likewise.
+
+2012-12-11  John David Anglin  <danglin@gcc.gnu.org>
+
+	* config/pa/pa.c (pa_callee_copies): New function.
+	* config/pa/pa.opt (mcaller-copies): New option.
+	* doc/invoke.texi (mcaller-copies): Document option.
+
+2016-12-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/70799
+	* config/i386/i386.c (dimode_scalar_to_vector_candidate_p)
+	<case ASHIFT, case LSHIFTRT>: Consider all constant shifts.
+	Add FIXME comment.
+	(dimode_scalar_chain::compute_convert_gain): Reduce gain for
+	constant shifts larger or equal than 32.
+
+2016-12-11  Roger Pau Monné  <roger.pau@citrix.com>
+
+	* config/i386/x86-64.h: Append --32 to the assembler options when
+	-m16 is used on non-glibc systems as well.
+
+2016-12-10  Allan Sandfeld Jensen  <allan.jensen@qt.io>
+
+	PR target/70118
+	* config/i386/mmintrin.h (__m64_u): New type
+	* config/i386/emmintrin.h (_mm_loadl_epi64, _mm_storel_epi64):
+	Make the allowed unaligned memory access explicit.
+
+2016-12-10  Krister Walfridsson  <krister.walfridsson@gmail.com>
+
+	* config.gcc (i386-*-netbsd*): Make i486 the default arch on NetBSD.
+	Generally use cpu generic.
+
+2016-12-10  Jakub Jelinek  <jakub@redhat.com>
+	    Marc Glisse  <marc.glisse@inria.fr>
+
+	PR tree-optimization/78720
+	* match.pd (A < 0 ? C : 0): Only optimize for signed A.  If shift
+	is negative, sign extend to @1's type and than AND with C.
+
+2016-12-10  Jakub Jelinek  <jakub@redhat.com>
+
+	PR fortran/78758
+	* tree-object-size.c (compute_object_offset) <case ARRAY_REF>: Handle
+	non-zero low bound or non-standard element sizes.
+
+	PR sanitizer/78708
+	* lto-streamer-in.c (input_function): In addition to debug stmts
+	without -g, remove IFN_*SAN_* calls if corresponding flag_sanitize
+	bit is not enabled.
+
+2016-12-09  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000-passes.def: New file.
+	* config/rs6000/rs6000-protos.h: Declare make_pass_analyze_swaps.
+	* config/rs6000/rs6000.c (rs6000_option_override): Remove
+	registration of machine-specific passes.
+	(pass_analyze_swaps::clone): New function.
+	* config/rs6000/t-rs6000: Define PASSES_EXTRA.
+
+2016-12-09  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	PR ipa/78721
+	* ipa-cp.c (propagate_vr_accross_jump_function): Call
+	drop_tree_overflow after fold_convert.
+
+2016-12-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/72742
+	* config/rs6000/rs6000.md (*and<mode>3_imm_mask_dot,
+	*and<mode>3_imm_mask_dot2): Add rs6000_is_valid_and_mask to insn
+	condition.
+
+2016-12-09  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/78683
+	* config/rs6000/rs6000.h (CLZ_DEFINED_VALUE_AT_ZERO): Use
+	GET_MODE_BITSIZE.  Return 2.
+	(CTZ_DEFINED_VALUE_AT_ZERO): Use GET_MODE_BITSIZE.  Return 2.  Handle
+	TARGET_POPCNTD the same as TARGET_CTZ.
+	* config/rs6000/rs6000.md (ctz<mode>2): Reimplement.
+	(ffs<mode>2): Reimplement.
+
+2016-12-09  Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+	PR rtl-optimization/78255
+	* gcc/postreload.c (reload_cse_simplify): Do not CSE a function if
+	NO_FUNCTION_CSE is true.
+
+2016-12-09  Cesar Philippidis  <cesar@codesourcery.com>
+
+	PR ipa/78027
+	* ipa-icf.c (sem_function::parse): Don't process functions with
+	oacc decl attributes, as they may be OpenACC routines.
+
+2016-12-09  David Malcolm  <dmalcolm@redhat.com>
+
+	* rtl.h (get_mem_attrs): Add "const" qualifier to returned
+	pointer.
+
+2016-12-09  Nathan Sidwell  <nathan@acm.org>
+
+	PR C++/78550
+	* convert.c (convert_to_integer_1): Maybe fold conversions to
+	integral types with fewer bits than its mode.
+
+2016-12-09  Martin Liska  <mliska@suse.cz>
+
+	* tree-pretty-print.c (pretty_print_string): Escape non-printable
+	chars in strings.
+
+2016-12-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/78726
+	* tree-ssa-reassoc.c (make_new_ssa_for_def): Add OPCODE and OP
+	argument.  For lhs uses in debug stmts, don't replace lhs with
+	new_lhs, but with a debug temp set to new_lhs opcode op.
+	(make_new_ssa_for_all_defs): Add OPCODE argument, pass OPCODE and
+	OP down to make_new_ssa_for_def.
+	(zero_one_operation): Call make_new_ssa_for_all_defs even when
+	stmts_to_fix is empty, if *def has not changed yet.  Pass
+	OPCODE to make_new_ssa_for_all_defs.
+
+2016-12-08  Martin Sebor  <msebor@redhat.com>
+
+	PR c/78284
+	* builtin-attrs.def (ATTR_ALLOC_SIZE, ATTR_RETURNS_NONNULL): New
+	identifier tree nodes.
+	(ATTR_ALLOCA_SIZE_1_NOTHROW_LEAF_LIST): New attribute list.
+	(ATTR_MALLOC_SIZE_1_NOTHROW_LIST): Same.
+	(ATTR_MALLOC_SIZE_1_NOTHROW_LEAF_LIST): Same.
+	(ATTR_MALLOC_SIZE_1_2_NOTHROW_LEAF_LIST): Same.
+	(ATTR_ALLOC_SIZE_2_NOTHROW_LEAF_LIST): Same.
+	* builtins.c (expand_builtin_alloca): Call
+	maybe_warn_alloc_args_overflow.
+	* builtins.def (aligned_alloc, calloc, malloc, realloc):
+	Add attribute alloc_size.
+	(alloca): Add attribute alloc_size and returns_nonnull.
+	* calls.h (maybe_warn_alloc_args_overflow): Declare.
+	* calls.c (alloc_max_size, operand_signed_p): New functions.
+	(maybe_warn_alloc_args_overflow): Define.
+	(initialize_argument_information): Diagnose overflow in functions
+	declared with attaribute alloc_size.
+	* doc/invoke.texi (Warning Options): Document -Walloc-zero and
+	-Walloc-size-larger-than.
+
+2016-12-08  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/78671
+	* lra-assign.c (find_hard_regno_for_1): Check prohibited regs for an
+	allocno class.
+
+2016-12-08  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.h (HARD_REGNO_NREGS): Use GENERAL_REGNO_P.
+	(HARD_REGNO_NREGS_HAS_PADDING): Ditto.  Simplify macro.
+
+2015-12-08  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	PR target/78733
+	* config/aarch64/aarch64.c (aarch64_classify_address):
+	Set load_store_pair_p for TImode and TFmode.
+
+2016-12-08  David Malcolm  <dmalcolm@redhat.com>
+
+	* emit-rtl.c (gen_reg_rtx): Move regno_pointer_align and
+	regno_reg_rtx resizing logic to...
+	(emit_status::ensure_regno_capacity): ...this new method,
+	and ensure that the buffers are large enough.
+	(init_emit): Allocate regno_reg_rtx using ggc_cleared_vec_alloc
+	rather than ggc_vec_alloc.
+	* function.h (emit_status::ensure_regno_capacity): New method.
+
+2016-12-08  Dmitry Vyukov  <dvyukov@google.com>
+
+	* opts.c (finish_options): Enable -fsanitize-address-use-after-scope
+	only if -fsanitize=address is enabled (not -fsanitize=kernel-address).
+	* doc/invoke.texi (-fsanitize=kernel-address):
+	Don't say that it enables -fsanitize-address-use-after-scope.
+
+2016-12-08  Bin Cheng  <bin.cheng@arm.com>
+
+	PR middle-end/78684
+	* tree-vect-loop-manip.c (create_intersect_range_checks_index): Check
+	sign bit for index step of data reference.
+
+2016-12-08  Naveen H.S  <Naveen.Hurugalawadi@cavium.com>
+
+	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
+	Handle SYMBOL_SMALL_TLSGD for ILP32.
+	* config/aarch64/aarch64.md : tlsgd_small modified into
+	tlsgd_small_<mode> to support SImode and DImode.
+	*tlsgd_small modified into *tlsgd_small_<mode> to support SImode and
+	DImode.
+
+2016-12-08  Andrew Pinski  <apinski@cavium.com>
+
+	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
+	Access the lower part of RTX appropriately.
+
+2016-12-07  David Malcolm  <dmalcolm@redhat.com>
+
+	* genpreds.c (write_tm_constrs_h): Update for renaming of
+	rtx_reader_ptr to md_reader_ptr.
+	(write_tm_preds_h): Likewise.
+	(write_insn_preds_c): Likewise.
+	* read-md.c (rtx_reader_ptr): Rename to...
+	(md_reader_ptr): ...this, and convert from an
+	rtx_reader * to a md_reader *.
+	(rtx_reader::set_md_ptr_loc): Rename to...
+	(md_reader::set_md_ptr_loc): ...this.
+	(rtx_reader::get_md_ptr_loc): Rename to...
+	(md_reader::get_md_ptr_loc): ...this.
+	(rtx_reader::copy_md_ptr_loc): Rename to...
+	(md_reader::copy_md_ptr_loc): ...this.
+	(rtx_reader::fprint_md_ptr_loc): Rename to...
+	(md_reader::fprint_md_ptr_loc): ...this.
+	(rtx_reader::print_md_ptr_loc): Rename to...
+	(md_reader::print_md_ptr_loc): ...this.
+	(rtx_reader::join_c_conditions): Rename to...
+	(md_reader::join_c_conditions): ...this.
+	(rtx_reader::fprint_c_condition): ...this.
+	(rtx_reader::print_c_condition): Rename to...
+	(md_reader::print_c_condition): ...this.
+	(fatal_with_file_and_line):  Update for renaming of
+	rtx_reader_ptr to md_reader_ptr.
+	(rtx_reader::require_char): Rename to...
+	(md_reader::require_char): ...this.
+	(rtx_reader::require_char_ws): Rename to...
+	(md_reader::require_char_ws): ...this.
+	(rtx_reader::require_word_ws): Rename to...
+	(md_reader::require_word_ws): ...this.
+	(rtx_reader::read_char): Rename to...
+	(md_reader::read_char): ...this.
+	(rtx_reader::unread_char): Rename to...
+	(md_reader::unread_char): ...this.
+	(rtx_reader::peek_char): Rename to...
+	(md_reader::peek_char): ...this.
+	(rtx_reader::read_name): Rename to...
+	(md_reader::read_name): ...this.
+	(rtx_reader::read_escape): Rename to...
+	(md_reader::read_escape): ...this.
+	(rtx_reader::read_quoted_string): Rename to...
+	(md_reader::read_quoted_string): ...this.
+	(rtx_reader::read_braced_string): Rename to...
+	(md_reader::read_braced_string): ...this.
+	(rtx_reader::read_string): Rename to...
+	(md_reader::read_string): ...this.
+	(rtx_reader::read_skip_construct): Rename to...
+	(md_reader::read_skip_construct): ...this.
+	(rtx_reader::handle_constants): Rename to...
+	(md_reader::handle_constants): ...this.
+	(rtx_reader::traverse_md_constants): Rename to...
+	(md_reader::traverse_md_constants): ...this.
+	(rtx_reader::handle_enum): Rename to...
+	(md_reader::handle_enum): ...this.
+	(rtx_reader::lookup_enum_type): Rename to...
+	(md_reader::lookup_enum_type): ...this.
+	(rtx_reader::traverse_enum_types): Rename to...
+	(md_reader::traverse_enum_types): ...this.
+	(rtx_reader::rtx_reader): Rename to...
+	(md_reader::md_reader): ...this, and update for renaming of
+	rtx_reader_ptr to md_reader_ptr.
+	(rtx_reader::~rtx_reader): Rename to...
+	(md_reader::~md_reader): ...this, and update for renaming of
+	rtx_reader_ptr to md_reader_ptr.
+	(rtx_reader::handle_include): Rename to...
+	(md_reader::handle_include): ...this.
+	(rtx_reader::handle_file): Rename to...
+	(md_reader::handle_file): ...this.
+	(rtx_reader::handle_toplevel_file): Rename to...
+	(md_reader::handle_toplevel_file): ...this.
+	(rtx_reader::get_current_location): Rename to...
+	(md_reader::get_current_location): ...this.
+	(rtx_reader::add_include_path): Rename to...
+	(md_reader::add_include_path): ...this.
+	(rtx_reader::read_md_files): Rename to...
+	(md_reader::read_md_files): ...this.
+	* read-md.h (class rtx_reader): Split into...
+	(class md_reader): ...new class.
+	(rtx_reader_ptr): Rename to...
+	(md_reader_ptr): ...this, and convert to a md_reader *.
+	(class noop_reader): Update base class to be md_reader.
+	(class rtx_reader): Reintroduce as a subclass of md_reader.
+	(rtx_reader_ptr): Reintroduce as a rtx_reader *.
+	(read_char): Update for renaming of rtx_reader_ptr to
+	md_reader_ptr.
+	(unread_char): Likewise.
+	* read-rtl.c (rtx_reader_ptr): New global.
+	(rtx_reader::apply_iterator_to_string): Rename to...
+	(md_reader::apply_iterator_to_string): ...this.
+	(rtx_reader::copy_rtx_for_iterators): Rename to...
+	(md_reader::copy_rtx_for_iterators): ...this.
+	(rtx_reader::read_conditions): Rename to...
+	(md_reader::read_conditions): ...this.
+	(rtx_reader::record_potential_iterator_use): Rename to...
+	(md_reader::record_potential_iterator_use): ...this.
+	(rtx_reader::read_mapping): Rename to...
+	(md_reader::read_mapping): ...this.
+	(rtx_reader::read_rtx): Use rtx_reader_ptr when calling
+	read_rtx_code.
+	(rtx_reader::read_rtx_operand): Use get_string_obstack rather
+	than directly accessing m_string_obstack.
+	(rtx_reader::rtx_reader): New ctor.
+	(rtx_reader::~rtx_reader): New dtor.
+
+2016-12-07  Martin Sebor  <msebor@redhat.com>
+
+	PR middle-end/77784
+	PR middle-end/78149
+	PR middle-end/78138
+
+	* builtins.c (expand_builtin_strcat, expand_builtin_strncat): New
+	functions.
+	(compute_dest_size, get_size_range, check_sizes, check_strncat_sizes)
+	(check_memop_sizes): Same.
+	(expand_builtin_memcpy): Call check memop_sizes.
+	(expand_builtin_mempcpy): Same.
+	(expand_builtin_memset): Same,
+	(expand_builtin_bzero): Same.
+	(expand_builtin_memory_chk): Call check_sizes.
+	(expand_builtin_strcpy): Same.
+	(expand_builtin_strncpy): Same.
+	(maybe_emit_sprintf_chk_warning): Same.
+	(expand_builtin): Handle strcat and strncat.
+	(fini_object_sizes): Reset pointers.
+	(compute_object_size): New function.
+	* gimple-ssa-sprintf.c (pass_sprintf_length::handle_gimple_call):
+	Avoid issuing warnings also issued during built-in expansion.
+	* doc/invoke.texi (Warning Options): Document -Wstringop-overflow.
+
+2016-12-07  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/72717
+	* config/rs6000/rs6000.c (rs6000_expand_vector_init): If the
+	V2DImode elements are SUBREG's convert the result into DImode
+	rather than failing in emit_move_insn.
+
+2016-12-07  Jakub Jelinek  <jakub@redhat.com>
+
+	* builtins.c (fold_builtin_strstr): Removed.
+	(fold_builtin_2): Don't call fold_builtin_strstr.
+	* gimple-fold.c (gimple_fold_builtin_strchr): Check is_strrchr
+	earlier in the strrchr (x, 0) -> strchr (x, 0) optimization.
+	(gimple_fold_builtin_strstr): New function.
+	(gimple_fold_builtin): Call it.
+	* fold-const-call.c (fold_const_call): Handle CFN_BUILT_IN_STRSTR.
+
+	PR c++/78692
+	* cgraph.c (cgraph_edge::redirect_call_stmt_to_callee): Set lhs
+	var to lhs of new_stmt right before noreturn handling rather than to
+	lhs of e->call_stmt early.
+
+2016-12-07  David Malcolm  <dmalcolm@redhat.com>
+
+	* read-md.c (rtx_reader::require_char): New method.
+	(require_char_ws): Convert from function to...
+	(rtx_reader::require_char_ws): ...method.
+	(rtx_reader::require_word_ws): New method.
+	* read-md.h (rtx_reader::require_char): New method decl.
+	(require_char_ws): Remove global decl in favor of...
+	(rtx_reader::require_char_ws): ...new method decl.
+	(rtx_reader::require_word_ws): New method decl.
+	(rtx_reader::peek_char): New method decl.
+
+2016-12-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	PR rtl-optimization/78617
+	* lra-remat.c (do_remat): Initialize live_hard_regs from live in
+	registers, also setting hard registers mapped to pseudo registers.
+
+2016-12-07  David Malcolm  <dmalcolm@redhat.com>
+
+	* cfgexpand.c (pass_expand::execute): Move stack initializations
+	to rtl_data::init_stack_alignment and call it.
+	* emit-rtl.c (rtl_data::init_stack_alignment): New method.
+	* emit-rtl.h (rtl_data::init_stack_alignment): New method.
+
+2016-12-07  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* gcc/ira.c (ira_setup_eliminable_regset): Initialize crtl->is_leaf.
+	(ira): Move initialization of crtl->is_leaf earlier.
+
+2016-12-07  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64.md (movti_aarch64): Change Ump to m.
+	(movtf_aarch64): Likewise.
+	* config/aarch64/aarch64.c (aarch64_classify_address):
+	Use correct intersection of offsets.
+	(aarch64_legitimize_address_displacement): Use 9-bit signed offsets.
+	(aarch64_legitimize_address): Use 9-bit signed offsets for TI/TF mode.
+	Use 7-bit signed scaled mode for modes > 16 bytes.
+
+2016-12-07  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	PR rtl-optimization/78561
+	* config/rs6000/rs6000.c (rs6000_reg_live_or_pic_offset_p) Use
+	constant_pool_empty_p in place of get_pool_size_upper_bound.
+	(rs6000_stack_info): Likewise.
+	(rs6000_emit_prologue): Likewise.
+	(rs6000_elf_declare_function_name): Likewise.
+	(rs6000_set_up_by_prologue): Likewise.
+	(rs6000_can_eliminate): Likewise.
+	* output.h (get_pool_size_upper_bound): Delete.
+	(constant_pool_empty_p): New.
+	* varasm.c (get_pool_size_upper_bound): Delete
+	(constant_pool_empty_p): New.
+
+2016-12-07  Bin Cheng  <bin.cheng@arm.com>
+
+	PR tree-optimization/78691
+	* match.pd ((convert1 (minmax ((convert2 (x) c)))) -> minmax (x c)):
+	Require integral type for the outer expression.
+
+2016-12-07  Naveen H.S  <Naveen.Hurugalawadi@cavium.com>
+
+	* config/aarch64/aarch64.c
+	(aarch64_builtin_support_vector_misalignment): New.
+	(TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Define.
+
+2016-12-06  David Malcolm  <dmalcolm@redhat.com>
+
+	PR bootstrap/78705
+	* config/i386/i386.c (ix86_test_dumping_memory_blockage):
+	Conditionalize the string comparison on Pmode == DImode.
+
+2016-12-06  Tom de Vries  <tom@codesourcery.com>
+
+	PR tree-optimization/67955
+	* tree-ssa-alias.c (same_addr_size_stores_p): New function.
+	(stmt_kills_ref_p): Use it.
+
+2016-12-06  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR middle-end/78700
+	* calls.c (expand_call): Move back call to prepare_call_address.
+
+2016-12-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/78658
+	* config/rs6000/rs6000.md (zero_extendqi<mode>2): Use ^ instead of
+	?* constraints for the ISA 3.0 patterns, so the register allocator
+	is more likely to allocate QImode/HImode to vector registers for
+	conversion to floating point unless a reload is needed.
+	(zero_extendhi<mode>2): Likewise.
+	(float<QHI:mode><FP_ISA3:mode>2_internal): Properly deal with the
+	first alternative which is converting QImode/HImode to floating
+	point and the QImode/HImode value is in a vector register, and
+	does not allocate the second pseudo register.  Remove zero
+	extending into traditional floating point registers, since the
+	instruction used only works on traditional altivec registers.
+	(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
+
+2016-12-06  David Malcolm  <dmalcolm@redhat.com>
+
+	* config/i386/i386.c: Include print-rtl.h.
+	(selftest::ix86_test_dumping_memory_blockage): New function.
+	(selftest::ix86_run_selftests): Call it.
+	* print-rtl-function.c (print_rtx_function): Create an
+	rtx_reuse_manager and use it.
+	* print-rtl.c: Include "rtl-iter.h".
+	(rtx_writer::rtx_writer): Add reuse_manager param.
+	(rtx_reuse_manager::rtx_reuse_manager): New ctor.
+	(uses_rtx_reuse_p): New function.
+	(rtx_reuse_manager::preprocess): New function.
+	(rtx_reuse_manager::has_reuse_id): New function.
+	(rtx_reuse_manager::seen_def_p): New function.
+	(rtx_reuse_manager::set_seen_def): New function.
+	(rtx_writer::print_rtx): If "in_rtx" has a reuse ID, print it as a
+	prefix the first time in_rtx is seen, and print reuse_rtx
+	subsequently.
+	(print_inline_rtx): Supply NULL for new reuse_manager param.
+	(debug_rtx): Likewise.
+	(print_rtl): Likewise.
+	(print_rtl_single): Likewise.
+	(rtx_writer::print_rtl_single_with_indent): Likewise.
+	* print-rtl.h: Include bitmap.h when building for host.
+	(rtx_writer::rtx_writer): Add reuse_manager param.
+	(rtx_writer::m_rtx_reuse_manager): New field.
+	(class rtx_reuse_manager): New class.
+	* rtl-tests.c (selftest::assert_rtl_dump_eq): Add reuse_manager
+	param and use it when constructing rtx_writer.
+	(selftest::test_dumping_rtx_reuse): New function.
+	(selftest::rtl_tests_c_tests): Call it.
+	* selftest-rtl.h (class rtx_reuse_manager): New forward decl.
+	(selftest::assert_rtl_dump_eq): Add reuse_manager param.
+	(ASSERT_RTL_DUMP_EQ): Supply NULL for reuse_manager param.
+	(ASSERT_RTL_DUMP_EQ_WITH_REUSE): New macro.
+
+2016-12-06  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR target/77761
+	* lra-lives.c (process_bb_lives): Update biggest mode for
+	implicitly used hard reg.
+
+2016-12-06  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/predicates.md (general_gr_operand): New predicate.
+	* config/i386/i386.md (TImode and DImode push_operand splitter):
+	Use general_gr_operand.  Macroize using DWI mode macro.
+	(TImode and DImode nonimmediate_operand splitter): Use
+	nonimmediate_gr_operand and general_gr_operand.  Macroize using
+	DWI mode macro.
+	(TF/XF/DFmode push_operand splitter): Use general_gr_operand.
+	(TFmode nonimmediate_operand splitter): Use nonimmediate_gr_operand
+	and general_gr_operand.
+	(XFmode nonimmediate_operand splitter): Ditto.
+	(DFmode nonimmediate_operand splitter): Ditto.
+	* config/i386/mmx.md (MMXMODE nonimmediate_operand splitter): Ditto.
+
+2016-12-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/arm/arm-cores.def (cortex-m23, cortex-m33): Move into
+	alphabetical order with respect to other ARMv8 processors.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Likewise.
+
+2016-12-06  Robert Suchanek  <robert.suchanek@imgtec.com>
+
+	* config/mips/mips.c (mips_expand_builtin_insn): Check input
+	ranges of literal integer arguments.
+
+2016-12-06  Aldy Hernandez  <aldyh@redhat.com>
+
+	PR middle-end/78548
+	* tree-ssa-uninit.c (simplify_preds_4): Call release() instead of
+	destroy_predicate_vecs.
+	(uninit_uses_cannot_happen): Make uninit_preds a scalar.
+
+2016-12-06  Aldy Hernandez  <aldyh@redhat.com>
+
+	PR middle-end/78566
+	* tree-ssa-uninit.c (can_one_predicate_be_invalidated_p): Change
+	argument type to a pred_chain.
+	(can_chain_union_be_invalidated_p): Use pred_chain instead of a
+	worklist.
+	(flatten_out_predicate_chains): Remove.
+	(uninit_uses_cannot_happen): Rename from
+	uninit_ops_invalidate_phi_use.
+	Change logic so that we are checking that the PHI use will
+	invalidate _ALL_ possibly uninitialized operands.
+	(is_use_properly_guarded): Rename call to
+	uninit_ops_invalidate_phi_use into uninit_uses_cannot_happen.
+
+2016-12-06  Tamar Christina  <tamar.christina@arm.com>
+
+	* gcc/config/aarch64/arm_neon.h
+	(vreinterpretq_p8_p128, vreinterpretq_p16_p128): Added.
+	(vreinterpret_p64_p16, vreinterpretq_p64_p128): Likewise.
+	(vreinterpretq_p64_p16, vreinterpretq_p128_p8): Likewise.
+	(vreinterpretq_p128_p16, vreinterpretq_p128_f16): Likewise.
+	(vreinterpretq_p128_f32, vreinterpretq_p128_p64): Likewise.
+	(vreinterpretq_p128_s64, vreinterpretq_p128_u64): Likewise.
+	(vreinterpretq_p128_s8, vreinterpretq_p128_s16): Likewise.
+	(vreinterpretq_p128_s32, vreinterpretq_p128_u8): Likewise.
+	(vreinterpretq_p128_u16, vreinterpretq_p128_u32): Likewise.
+	(vreinterpretq_f16_p128, vreinterpretq_f32_p128): Likewise.
+	(vreinterpretq_s64_p128, vreinterpretq_u64_p128): Likewise.
+	(vreinterpretq_s8_p128, vreinterpretq_s16_p128): Likewise.
+	(vreinterpretq_s32_p128, vreinterpretq_u8_p128): Likewise.
+	(vreinterpretq_u16_p128, vreinterpretq_u32_p128): Likewise.
+
+2016-12-06  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/71537
+	* fold-const.c (fold_comparison): Assume CONSTANT_CLASS_P (base0)
+	plus offset is non-zero.  For maybe_nonzero_address decl base0,
+	require indirect_base0.
+
+	PR c++/71537
+	* fold-const-call.c (fold_const_call_1): Remove memchr handling here.
+	(fold_const_call) <case CFN_BUILT_IN_STRNCMP,
+	case CFN_BUILT_IN_STRNCASECMP>: Formatting improvements.
+	(fold_const_call) <case CFN_BUILT_IN_MEMCMP>: Likewise.  If s2 is 0
+	and arguments have no side-effects, return 0.
+	(fold_const_call): Handle CFN_BUILT_IN_MEMCHR.
+
+	PR c++/71537
+	* fold-const-call.c (fold_const_call): Handle
+	CFN_BUILT_IN_{INDEX,STRCHR,RINDEX,STRRCHR}.
+
+	PR tree-optimization/78675
+	* tree-vect-loop.c (vectorizable_live_operation): For
+	VECTOR_BOOLEAN_TYPE_P vectype use integral type with bitsize precision
+	instead of TREE_TYPE (vectype) for the BIT_FIELD_REF.
+
+2016-12-06  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR middle-end/78642
+	* emit-rtl.c (verify_rtx_sharing) <CLOBBER>: Relax condition.
+	(copy_rtx_if_shared_1) <CLOBBER>: Likewise.
+	(copy_insn_1) <CLOBBER>: Likewise.
+
+2016-12-05  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/78688
+	* config/rs6000/rs6000.h (FUNCTION_VALUE_REGNO_P): Use IN_RANGE
+	instead of ((N) >= (X) && (N) <= (Y-X)) to silence warnings about
+	comparing signed to unsigned values.
+	(FUNCTION_ARG_REGNO_P): Likewise.
+
+2016-12-05  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+	    Stefan Freudenberger  <stefan@reservoir.com>
+
+	PR tree-optimization/78646
+	* gimple-ssa-strength-reduction.c (replace_ref): The pointer
+	addition used for the memory base expression should have the type
+	of the candidate.
+
+2016-12-05  Waldemar Brodkorb  <wbx@openadk.org>
+
+	PR target/71721
+	* config.gcc (*-*-uclinux*): Enable posix threads.
+
+2016-12-05  Andrew Senkevich  <andrew.senkevich@intel.com>
+
+	* config/i386/avx512bwintrin.h: Add new k-mask intrinsics.
+	* config/i386/avx512dqintrin.h: Ditto.
+	* config/i386/avx512fintrin.h: Ditto.
+	* config/i386/i386-builtin-types.def (UCHAR_FTYPE_UQI_UQI_PUCHAR,
+	UCHAR_FTYPE_UHI_UHI_PUCHAR, UCHAR_FTYPE_USI_USI_PUCHAR,
+	UCHAR_FTYPE_UDI_UDI_PUCHAR, UCHAR_FTYPE_UQI_UQI, UCHAR_FTYPE_UHI_UHI,
+	UCHAR_FTYPE_USI_USI, UCHAR_FTYPE_UDI_UDI, UQI_FTYPE_UQI_INT,
+	UHI_FTYPE_UHI_INT, USI_FTYPE_USI_INT, UDI_FTYPE_UDI_INT,
+	UQI_FTYPE_UQI, USI_FTYPE_USI, UDI_FTYPE_UDI, UQI_FTYPE_UQI_UQI): New
+	function types.
+	* config/i386/i386-builtin.def (__builtin_ia32_knotqi,
+	__builtin_ia32_knotsi, __builtin_ia32_knotdi,
+	__builtin_ia32_korqi, __builtin_ia32_korsi, __builtin_ia32_kordi,
+	__builtin_ia32_kxnorqi, __builtin_ia32_kxnorsi,
+	__builtin_ia32_kxnordi, __builtin_ia32_kxorqi, __builtin_ia32_kxorsi,
+	__builtin_ia32_kxordi, __builtin_ia32_kandqi,
+	__builtin_ia32_kandsi, __builtin_ia32_kanddi, __builtin_ia32_kandnqi,
+	__builtin_ia32_kandnsi, __builtin_ia32_kandndi): New.
+	* config/i386/i386.c (ix86_expand_args_builtin): Handle new types.
+
+2016-12-05  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* combine.c: Revert r243162.
+
+2016-12-05  Paolo Bonzini  <bonzini@gnu.org>
+
+	* match.pd: Simplify X ? C : 0 where C is a power of 2 and
+	X tests a single bit.
+
+2016-12-05  Nathan Sidwell  <nathan@acm.org>
+
+	* diagnostic.c (diagnostic_check_max_errors): New, broken out of ...
+	(diagnostic_action_after_output): ... here.
+	(diagnostic_report_diagnostic): Call it for non-notes.
+	* diagnostic.h (struct diagnostic_context): Make max_errors signed int.
+	(diagnostic_check_max_errors): Declare.
+
+2016-12-05  Cupertino Miranda  <cmiranda@synopsys.com>
+
+	* config/arc/arc.h (STARTFILE_SPEC): Use default linux specs.
+	(ENDFILE_SPEC): Likewise.
+
+2016-12-05  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc-protos.h (insn_is_tls_gd_dispatch): Remove.
+	* config/arc/arc.c (arc_unspec_offset): New function.
+	(arc_finalize_pic): Change.
+	(arc_emit_call_tls_get_addr): Likewise.
+	(arc_legitimize_tls_address): Likewise.
+	(arc_legitimize_pic_address): Likewise.
+	(insn_is_tls_gd_dispatch): Remove.
+	* config/arc/arc.h (INSN_REFERENCES_ARE_DELAYED): Change.
+	* config/arc/arc.md (ls_gd_load): Remove unused pattern.
+	(tls_gd_dispatch): Likewise.
+
+2016-12-05  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	* config/arm/arm.c (TARGET_ASM_INIT_SECTIONS): Fix wrong undef
+	location.
+
+2016-12-05  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc-protos.h (sparc_splitdi_legitimate): Rename to...
+	(sparc_split_reg_mem_legitimate): ...this.
+	(sparc_split_reg_mem): Declare.
+	(sparc_split_mem_reg): Likewise.
+	(sparc_split_regreg_legitimate): Rename to...
+	(sparc_split_reg_reg_legitimate): ...this.
+	* config/sparc/sparc.c (sparc_splitdi_legitimate): Rename to...
+	(sparc_split_reg_mem_legitimate): ...this.
+	(sparc_split_reg_mem): New function.
+	(sparc_split_mem_reg): Likewise.
+	(sparc_split_regreg_legitimate): Rename to...
+	(sparc_split_reg_reg_legitimate): ...this.
+	(sparc_split_reg_reg): New function.
+	* config/sparc/sparc.md (lra): Remove "none" value.
+	(enabled): Adjust to above change.
+	(*movdi_insn_sp32): Remove new (r,T) alternative and reorder others.
+	(DImode splitters): Adjust to above renamings and use new functions.
+	(*movdf_insn_sp32): Remove new (r,T) alternative and reorder others.
+	(DFmode splitters): Adjust to above renamings and use new functions.
+	(*mov<VM64:mode>_insn_sp64): Replace C with Z constraint and use W
+	constraint in conjunction with e.
+	(*mov<VM64:mode>_insn_sp32): Remove new (r,T) alternative, add (o,Y)
+	alternative and reorder others.
+	(VM64:mode splitters): Adjust to above renamings and use new functions.
+
+2016-12-04  Martin Sebor  <msebor@redhat.com>
+
+	PR c/78668
+	* builtin-attrs.def (ATTR_ALLOC_SIZE, ATTR_RETURNS_NONNULL): New
+	identifier tree nodes.
+	(ATTR_ALLOCA_SIZE_1_NOTHROW_LEAF_LIST): New attribute list.
+	(ATTR_MALLOC_SIZE_1_NOTHROW_LIST): Same.
+	(ATTR_MALLOC_SIZE_1_NOTHROW_LEAF_LIST): Same.
+	(ATTR_MALLOC_SIZE_1_2_NOTHROW_LEAF_LIST): Same.
+	(ATTR_ALLOC_SIZE_2_NOTHROW_LEAF_LIST): Same.
+	* builtins.def (aligned_alloc, calloc, malloc, realloc):
+	Add attribute alloc_size.
+	(alloca): Add attribute alloc_size and returns_nonnull.
+
+2016-12-04  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/70322
+	* config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Handle NEG.
+	(dimode_scalar_chain::compute_convert_gain): Ditto.
+	(dimode_scalar_chain::convert_insn): Ditto.
+
+2016-12-03  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* lra-constraints.c (emit_spill_move): Use gen_lowpart_SUBREG in all
+	cases to build a lowpart SUBREG.
+
+2016-12-03  Eric Botcazou  <ebotcazou@adacore.com>
+	    David S. Miller  <davem@davemloft.net>
+
+	* config/sparc/constraints.md (U): Adjust comment.
+	* config/sparc/sparc.md (lra): New attribute.
+	(enabled): For base instructions, if the lra attribute is set,
+	return 1 if it is in keeping with TARGET_LRA.
+	(*movdi_insn_sp32): Add lra attribute for alternatives mentioning U
+	constraint and duplicate them with U replaced by r.
+	(*movdf_insn_sp32): Likewise.
+	(*mov<VM64:mode>_insn_sp32): Likewise.
+	(*movtf_insn_sp32): Remove alternatives mentioning U constraint.
+
+2016-12-02  Jeff Law  <law@redhat.com>
+
+	* config/arm/arm.c (arm_handle_cmse_nonsecure_call): Remove unused
+	variable main_variant.
+
+2016-12-02  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config.gcc (powerpc*-*-linux*): Set gnu-indirect-function by
+	default on PowerPC linux systems.
+
+2016-12-02  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78638
+	* simplify-rtx.c (simplify_truncation): M2 is not mode, it is
+	GET_MODE (op).  Fix this.
+
+2016-12-02  David Malcolm  <dmalcolm@redhat.com>
+
+	PR bootstrap/78616
+	* selftest.c (selftest::assert_strndup_eq): Rename to...
+	(selftest::assert_xstrndup_eq): ...this, and remove call to
+	strndup.
+	(selftest::test_strndup): Rename to...
+	(selftest::test_xstrndup): ...this, updating for above renaming.
+	(selftest::test_libiberty): Update for renaming.
+
+2016-12-02  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/78639
+	* config/rs6000/rs6000.md (movdi_internal64): Fix typo in
+	subversion id 242679 that causes the wrong store instruction to be
+	generated if a DImode is in an Altivec register using REG+REG
+	addressing.
+
+2016-12-02  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/70322
+	* config/i386/i386.md (*andndi3_doubleword): Add non-BMI alternative
+	and corresponding post-reload splitter.
+
+2016-12-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.h (machine_function): Add
+	reg_is_wrapped_separately field.
+	* config/aarch64/aarch64.md (LAST_SAVED_REGNUM): Define new constant.
+	* config/aarch64/aarch64.c (emit_set_insn): Change return type to
+	rtx_insn *.
+	(aarch64_save_callee_saves): Don't save registers that are wrapped
+	separately.
+	(aarch64_restore_callee_saves): Don't restore registers that are
+	wrapped separately.
+	(offset_9bit_signed_unscaled_p, offset_12bit_unsigned_scaled_p,
+	aarch64_offset_7bit_signed_scaled_p): Move earlier in the file.
+	(aarch64_get_separate_components): New function.
+	(aarch64_get_next_set_bit): Likewise.
+	(aarch64_components_for_bb): Likewise.
+	(aarch64_disqualify_components): Likewise.
+	(aarch64_emit_prologue_components): Likewise.
+	(aarch64_emit_epilogue_components): Likewise.
+	(aarch64_set_handled_components): Likewise.
+	(aarch64_process_components): Likewise.
+	(TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS,
+	TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB,
+	TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS,
+	TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS,
+	TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS,
+	TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Define.
+
+2016-12-02  Martin Jambor  <mjambor@suse.cz>
+
+	* passes.def: Move pass_rebuild_cgraph_edges to the end of
+	pass_build_ssa_passes.
+
+2016-12-02  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/alpha/alpha.md (exception_receiver): Copy
+	alpha_gp_ave_rtx return value.
+
+2016-12-02  Tadek Kijkowski  <tkijkowski@gmail.com>
+
+	* Makefile.in (PREPROCESSOR_DEFINES): Add a level of indirection
+	for several include directories that may be relative to sysroot.
+	* config/i386/x-mingw32 (gplus_includedir): Define.
+	(gplus_tool_includedir, gplus_backward_include_dir): Likewise.
+	(native_system_includedir): Likewise.
+	* config/i386/mingw32.h (STANDARD_STARTFILE_PREFIX_1): Do not
+	override if TARGET_SYSTEM_ROOT is defined.
+	(NATIVE_SYSTEM_HEADER_DIR): Likewise.
+
+2016-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/70322
+	* config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Handle NOT.
+	(dimode_scalar_chain::compute_convert_gain): Likewise.
+	(dimode_scalar_chain::convert_insn): Likewise.
+	* config/i386/i386.md (*one_cmpldi2_doubleword): New
+	define_insn_and_split.
+	(one_cmpl<mode>2): Use SWIM1248x iterator instead of SWIM.
+
+	PR target/78614
+	* rtl.c (copy_rtx): Don't clear used flag here.
+	(shallow_copy_rtx_stat): Clear used flag here unless code the rtx
+	is shareable.
+	* simplify-rtx.c (simplify_replace_fn_rtx): When copying rtx with
+	'E' in format, copy all vectors.
+	* emit-rtl.c (copy_insn_1): Don't clear used flag here.
+	* valtrack.c (cleanup_auto_inc_dec): Likewise.
+	* config/rs6000/rs6000.c (rs6000_frame_related): Likewise.
+
+2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+	    Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm-builtins.c (arm_builtins): Define
+	ARM_BUILTIN_CMSE_NONSECURE_CALLER.
+	(bdesc_2arg): Add line for cmse_nonsecure_caller.
+	(arm_init_builtins): Handle cmse_nonsecure_caller.
+	(arm_expand_builtin): Likewise.
+	* config/arm/arm_cmse.h (cmse_nonsecure_caller): New.
+
+2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+	    Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.c (detect_cmse_nonsecure_call): New.
+	(cmse_nonsecure_call_clear_caller_saved): New.
+	(arm_reorg): Use cmse_nonsecure_call_clear_caller_saved.
+	(arm_function_ok_for_sibcall): Disable sibcalls for
+	cmse_nonsecure_call.
+	* config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
+	* config/arm/arm.md (call): Handle cmse_nonsecure_entry.
+	(call_value): Likewise.
+	(nonsecure_call_internal): New.
+	(nonsecure_call_value_internal): New.
+	* config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
+	(*nonsecure_call_value_reg_thumb1_v5): New.
+	* config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
+	(*nonsecure_call_value_reg_thumb2): New.
+	* config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.
+
+2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+	    Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.c (gimplify.h): New include.
+	(arm_handle_cmse_nonsecure_call): New.
+	(arm_attribute_table): Added cmse_nonsecure_call.
+	(arm_comp_type_attributes): Deny compatibility of function types
+	with without the cmse_nonsecure_call attribute.
+	* doc/extend.texi (ARM ARMv8-M Security Extensions): New attribute.
+
+2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+	    Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.c (output_return_instruction): Clear
+	registers.
+	(thumb2_expand_return): Likewise.
+	(thumb1_expand_epilogue): Likewise.
+	(thumb_exit): Likewise.
+	(arm_expand_epilogue): Likewise.
+	(cmse_nonsecure_entry_clear_before_return): New.
+	(comp_not_to_clear_mask_str_un): New.
+	(compute_not_to_clear_mask): New.
+	* config/arm/thumb1.md (*epilogue_insns): Change length attribute.
+	* config/arm/thumb2.md (*thumb2_return): Disable for
+	cmse_nonsecure_entry functions.
+	(*thumb2_cmse_entry_return): Duplicate thumb2_return pattern for
+	cmse_nonsecure_entry functions.
+
+2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+	    Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.c (use_return_insn): Change to return with  bxns
+	when cmse_nonsecure_entry.
+	(output_return_instruction): Likewise.
+	(arm_output_function_prologue): Likewise.
+	(thumb_pop): Likewise.
+	(thumb_exit): Likewise.
+	(thumb2_expand_return): Assert that entry functions always have simple
+	returns.
+	(arm_expand_epilogue): Handle entry functions.
+	(arm_function_ok_for_sibcall): Disable sibcall for entry functions.
+	(arm_asm_declare_function_name): New.
+	* config/arm/arm-protos.h (arm_asm_declare_function_name): New.
+	* config/arm/elf.h (ASM_DECLARE_FUNCTION_NAME): Redefine to
+	use arm_asm_declare_function_name.
+
+2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+	    Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New.
+	(arm_attribute_table): Added cmse_nonsecure_entry
+	(arm_compute_func_type): Handle cmse_nonsecure_entry.
+	(cmse_func_args_or_return_in_stack): New.
+	(arm_handle_cmse_nonsecure_entry): New.
+	* config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define.
+	(IS_CMSE_ENTRY): Likewise.
+	* doc/extend.texi (ARM ARMv8-M Security Extensions): New attribute.
+
+2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+	    Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config.gcc (extra_headers): Added arm_cmse.h.
+	* config/arm/arm-arches.def (ARM_ARCH):
+	(armv8-m): Add FL2_CMSE.
+	(armv8-m.main): Likewise.
+	(armv8-m.main+dsp): Likewise.
+	* config/arm/arm-c.c
+	(arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
+	* config/arm/arm-flags.h: Define FL2_CMSE.
+	* config/arm.c (arm_arch_cmse): New.
+	(arm_option_override): New error for unsupported cmse target.
+	* config/arm/arm.h (arm_arch_cmse): New.
+	* config/arm/arm.opt (mcmse): New.
+	* config/arm/arm_cmse.h: New file.
+	* doc/invoke.texi (ARM Options): Add -mcmse.
+	* doc/sourcebuild.texi (arm_cmse_ok): Add new effective target.
+	* doc/extend.texi: Add ARMv8-M Security Extensions entry.
+
+2016-12-02  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.c: Fix coding rule glitches.
+
+2016-12-02  Martin Jambor  <mjambor@suse.cz>
+
+	* hsa.c (hsa_callable_function_p): Return false for artificial
+	functions.
+
+2016-12-02  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	PR rtl-optimization/78561
+	* varasm.c (recompute_pool_offsets): New.
+	(output_constant_pool): Call it.
+
+2016-12-02  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	PR rtl-optimization/78561
+	* config/rs6000/rs6000.c (rs6000_reg_live_or_pic_offset_p) Rename
+	get_pool_size to get_pool_size_upper_bound.
+	(rs6000_stack_info): Likewise.
+	(rs6000_emit_prologue): Likewise.
+	(rs6000_elf_declare_function_name): Likewise.
+	(rs6000_set_up_by_prologue): Likewise.
+	(rs6000_can_eliminate): Likewise, reformat spaces to tabs.
+	* output.h (get_pool_size): Rename to...
+	(get_pool_size_upper_bound): ...This.
+	* varasm.c (get_pool_size): Rename to...
+	(get_pool_size_upper_bound): ...This.
+
+2016-12-02  Bin Cheng  <bin.cheng@arm.com>
+
+	* match.pd: Add new pattern:
+	(cond (cmp (convert? x) c1) (op x c2) c3) -> (op (minmax x c1) c2).
+
+2016-12-02  Nathan Sidwell  <nathan@acm.org>
+
+	* diagnostic.c (diagnostic_report_diagnostic): Remove extraneous
+	braces.
+
+2016-12-02  Aldy Hernandez  <aldyh@redhat.com>
+
+	PR middle-end/78328
+	* gimple-ssa-warn-alloca.c (alloca_call_type): Handle
+	VR_ANTI_RANGE.
+
+2016-12-02  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* config/s390/s390.c (s390_save_gprs_to_fprs): Fix RTL sharing
+	problem.
+
+2016-12-02  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr-arch.h (avr_mcu_t) [n_flash]: Remove field.
+	* config/avr/avr-devices.c (AVR_MCU): Remove N_FLASH macro argument.
+	* config/avr/avr-mcus.def (AVR_MCU): Remove initializer for n_flash.
+	* config/avr/avr.c (avr_set_core_architecture) [avr_n_flash]: Use
+	avr_mcu_types.flash_size to compute default value.
+	* config/avr/gen-avr-mmcu-specs.c (print_mcu) [cc1_n_flash]: Use
+	mcu->flash_size to compute value for spec.
+
+2016-12-02  Georg-Johann Lay  <avr@gjlay.de>
+
+	* doc/invoke.texi (AVR Options) [-mabsdata]: Point to absdata.
+	* doc/extend.texi (AVR Variable Attributes) [progmem]: Hint
+	about linker description to avoid progmem altogether.
+	[absdata]: Point to -mabsdata option.
+
+2016-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/78547
+	* emit-rtl.c (unshare_all_rtl): Make sure DECL_RTL and
+	DECL_INCOMING_RTL is not shared.
+	* config/i386/i386.c (convert_scalars_to_vectors): If any
+	insns have been converted, adjust all parameter's DEC_RTL and
+	DECL_INCOMING_RTL back from V1TImode to TImode if the parameters have
+	TImode.
+
+	PR rtl-optimization/78575
+	* config/i386/i386.c (timode_scalar_chain::fix_debug_reg_uses): Use
+	DF infrastructure to wrap all V1TImode reg uses into TImode subreg
+	if not already wrapped in a subreg.  Make sure df_insn_rescan does not
+	affect further iterations.
+
+2016-12-02  Martin Liska  <mliska@suse.cz>
+
+	PR ipa/78555
+	* sreal.c (sreal::to_int): Make absolute value before shifting.
+	(sreal::operator/): Likewise.
+	(sreal_verify_negative_division): New test.
+	(void sreal_c_tests): Call the new test.
+	* sreal.h (sreal::normalize_up): Use new SREAL_ABS and
+	SREAL_SIGN macros.
+	(sreal::normalize_down): Likewise.
+
+2016-12-02  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	* combine.c (combine_simplify_rtx):  Suppress replacement of
+	"(and (reg) (const_int bit))" with "if_then_else".
+
+2016-12-02  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	PR target/77822
+	* config/s390/s390.md ("extzv")
+	("*extzv<mode><clobbercc_or_nocc>")
+	("*extzvdi<clobbercc_or_nocc>_lshiftrt")
+	("*<risbg_n>_ior_and_sr_ze")
+	("*extract1bitdi<clobbercc_or_nocc>")
+	("*insv<mode><clobbercc_or_nocc>", "*insv_rnsbg_noshift")
+	("*insv_rnsbg_srl", "*insv<mode>_mem_reg")
+	("*insvdi_mem_reghigh", "*insvdi_reg_imm"): Use EXTRACT_ARGS_IN_RANGE
+	to validate the arguments of zero_extract and sign_extract.
+
+2016-12-02  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	PR target/77822
+	* rtl.h (EXTRACT_ARGS_IN_RANGE): New.
+
+2016-12-02  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* gcc/config/s390/s390.c (s390_builtin_vectorization_cost): New
+	function.
+	(TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): Define target
+	macro.
+
+2016-12-02  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* config/s390/vector.md (vec_halfhalf): New mode iterator.
+	("vec_pack_trunc_<mode>", "vec_pack_ssat_<mode>")
+	("vec_pack_usat_<mode>", "vec_unpacks_hi_v16qi")
+	("vec_unpacks_low_v16qi", "vec_unpacku_hi_v16qi")
+	("vec_unpacku_low_v16qi", "vec_unpacks_hi_v8hi")
+	("vec_unpacks_lo_v8hi", "vec_unpacku_hi_v8hi")
+	("vec_unpacku_lo_v8hi", "vec_unpacks_hi_v4si")
+	("vec_unpacks_lo_v4si", "vec_unpacku_hi_v4si")
+	("vec_unpacku_lo_v4si"): New pattern definitions.
+	* config/s390/vx-builtins.md: Move VI_HW_HSD mode iterator to
+	vector.md.
+
+2016-12-02  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* config/s390/s390-protos.h (s390_reverse_condition): New
+	prototype.
+	* config/s390/s390.c (s390_canonicalize_comparison): Fold compares
+	of CC mode values.
+	(s390_reverse_condition): New function.
+	* config/s390/s390.h (REVERSE_CC_MODE, REVERSE_CONDITION): Define
+	target macros.
+
+2016-12-02  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* config/s390/s390-modes.def (CCVEQANY, CCVH, CCVHANY, CCVHU)
+	(CCVHUANY): Remove modes.
+	(CCVIH, CCVIHU, CCVIALL, CCVIANY, CCVFALL, CCVFANY): Add modes and
+	documentation.
+	* config/s390/s390.c (s390_match_ccmode_set): Rename cc modes.
+	(s390_expand_vec_compare_scalar): Pick one of the cc consumer
+	modes.
+	(s390_branch_condition_mask): Adjust to use the new cc consumer
+	modes.  The new modes allow for proper reversal in the middle-end.
+	(s390_expand_vec_compare_cc): Determine the proper cc producer and
+	consumer modes for a comparison.
+	* config/s390/s390.md: Rename CCVH to CCVIH and CCVHU to CCVIHU
+	throughout the file.
+	* config/s390/vx-builtins.md: Likewise.
+
+2016-12-02  Maxim Ostapenko  <m.ostapenko@samsung.com>
+
+	* asan.c (asan_global_struct): Refactor.
+	(create_odr_indicator): New function.
+	(asan_needs_odr_indicator_p): Likewise.
+	(is_odr_indicator): Likewise.
+	(asan_add_global): Introduce odr_indicator_ptr. Pass it into global's
+	constructor.
+	(asan_protect_global): Do not protect odr indicators.
+
+2016-12-01  Jeff Law  <law@redhat.com>
+
+	* tree-ssa-threadedge.c
+	(record_temporary_equivalences_from_stmts_at_dest): Avoid temporary
+	propagation of operands if there are no operands.
+
+2016-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/78586
+	* gimple-ssa-sprintf.c (format_integer): Don't handle NOP_EXPR,
+	CONVERT_EXPR or COMPONENT_REF here.  Formatting fix.  For
+	SSA_NAME_DEF_STMT with NOP_EXPR only change argtype if the rhs1's
+	type is INTEGER_TYPE or POINTER_TYPE.
+
+2016-12-01  Kelvin Nilsen  <kelvin@gcc.gnu.org>
+
+	PR target/78577
+	* config/rs6000/vsx.md (vextuhlx): Revise mode of operand 2.
+	(vextuhrx): Likewise.
+	(vextuwlx): Likewise.
+	(vextuwrx): Likewise.
+
+2016-12-01  David Malcolm  <dmalcolm@redhat.com>
+
+	* dwarf2out.c (dwarf2out_c_finalize): Reset early_dwarf and
+	early_dwarf_finished.
+
+2016-12-01  Eric Botcazou  <ebotcazou@adacore.com>
+	    David S. Miller  <davem@davemloft.net>
+
+	* config/sparc/sparc.opt (mlra): New target option.
+	* config/sparc/sparc.c (TARGET_LRA_P): Define to...
+	(sparc_lra_p): ...this.  New function.
+	(D_MODES, DF_MODES): Add missing cast.
+	* config/sparc/sparc.md (*movsi_lo_sum, *movsi_high): Do not
+	provide these insns when flag_pic.
+	(sethi_di_medlow, losum_di_medlow, seth44, setm44, setl44, sethh,
+	setlm, sethm, setlo, embmedany_sethi, embmedany_losum,
+	embmedany_brsum, embmedany_textuhi, embmedany_texthi,
+	embmedany_textulo, embmedany_textlo): Likewise.
+	(sethi_di_medlow_embmedany_pic): Provide it only with flag_pic.
+
+2016-12-01  David Edelsohn  <dje.gcc@gmail.com>
+
+	PR debug/66419
+	PR c++/78235
+	* dbxout.c (dbxout_type_fields): Skip TEMPLATE_DECLs.
+
+2016-12-01  Richard Biener  <rguenther@suse.de>
+	    Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	* vec.h (vec<T, A, vl_embed>::quick_grow_cleared): Guard call to
+	memset if len-oldlen != 0.
+	(vec<T, va_heap, vl_ptr>::safe_grow_cleared): Likewise.
+
+2016-12-01  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*andndi3_doubleword): Depend on TARGET_SSE2.
+
+2016-12-01  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.c: Fix coding rule glitches.
+
+2016-12-01  Markus Trippelsdorf  <markus@trippelsdorf.de>
+
+	PR tree-optimization/78598
+	* tree-ssa-loop-prefetch.c (ddown): Cast to signed to avoid
+	overflows.
+
+2016-12-01  Markus Trippelsdorf  <markus@trippelsdorf.de>
+
+	PR rtl-optimization/78596
+	* combine.c (simplify_comparison): Cast to unsigned to avoid
+	left shifting of negative value.
+
+2016-12-01  Matthias Klose  <doko@ubuntu.com>
+
+	* doc/install.texi: Don't use pkg-config to check for bdw-gc.
+
+2016-12-01  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-alias.c (indirect_refs_may_alias_p): Do not
+	treat arrays with same type as objects that cannot overlap.
+
+2016-12-01  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.c (avr_print_operand): Use SYMBOL_REF_P if possible.
+	(avr_handle_addr_attribute, avr_asm_output_aligned_decl_common)
+	(avr_asm_asm_output_aligned_bss, avr_addr_space_convert): Dito.
+
+2016-12-01  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/78587
+	* dwarf2out.c (loc_descr_plus_const): For negative offset use
+	uint_loc_descriptor instead of int_loc_descriptor and perform negation
+	in unsigned HOST_WIDE_INT type.
+	(scompare_loc_descriptor): Shift UINTVAL left instead of INTVAL.
+
+	PR target/78614
+	* config/rs6000/rs6000.c (rs6000_frame_related): Call
+	set_used_flags (pat) before any simplifications.  Clear used flag on
+	PARALLEL copy.  Don't guard add_reg_note call.  Call
+	copy_rtx_if_shared on pat before storing it into
+	REG_FRAME_RELATED_EXPR.
+
+2016-12-01  Alan Modra  <amodra@gmail.com>
+
+	* gcc/config/rs6000/rs6000.c (insn_is_swappable_p): Properly
+	look inside UNSPEC_VSX_XXSPLTW vec.
+
+2016-12-01  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78607
+	* combine.c (try_combine): Emit a barrier after a unconditional trap.
+
+2016-11-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/78602
+	* config/rs6000/rs6000.c (rs6000_expand_vector_extract): If the
+	element is not a constant or in a register, force it to a
+	register.
+
+	PR target/78560
+	* config/rs6000/rs6000.c (rs6000_expand_vector_set): Force value
+	that will be set to a vector element to be in a register.
+	* config/rs6000/vsx.md (vsx_set_<mode>_p9): Fix thinko that used
+	the wrong multiplier to convert the element number to a byte
+	offset.
+
+2016-11-30  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR tree-optimization/77856
+	* lra-constraints.c (inherit_in_ebb): Check original regno for
+	invalid invariant regs too.  Set only clobbered hard regs for the
+	invalid invariant regs.
+
+2016-11-30  Pitchumani Sivanupandi  <pitchumani.sivanupandi@microchip.com>
+
+	Commit files forgotten in r242966.
+
+	* config/avr/avr-arch.h (avr_mcu_t) [flash_size]: New member.
+	* config/avr/avr-devices.c (avr_mcu_types): Add flash size info.
+	* config/avr/gen-avr-mmcu-specs.c (print_mcu): Remove hard-coded
+	prefix check to find wrap-around value, instead use MCU flash size.
+	For 8k flash devices, update link_pmem_wrap spec string to
+	add --pmem-wrap-around=8k.
+	* config/avr/specs.h (LINK_RELAX_SPEC): Move link_pmem_wrap from
+	here...
+	(LINK_SPEC): ...to here.
+
+2016-11-30  David Malcolm  <dmalcolm@redhat.com>
+
+	PR c/78498
+	* selftest.c (selftest::assert_strndup_eq): New function.
+	(selftest::test_strndup): New function.
+	(selftest::test_libiberty): New function.
+	(selftest::selftest_c_tests): Call test_libiberty.
+
+2016-11-30  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78610
+	* ira.c (combine_and_move_insns): Don't substitute into TRAP_IF
+	instructions.
+
+2016-11-30  Bin Cheng  <bin.cheng@arm.com>
+
+	PR tree-optimization/78574
+	* tree-ssa-loop-ivopts.c (find_deriving_biv_for_expr): Skip loop
+	header PHI that doesn't define biv.
+
+2016-11-30  Jakub Jelinek  <jakub@redhat.com>
+
+	* emit-rtl.c (verify_insn_sharing): Call verify_rtx_sharing instead of
+	reset_used_flags.
+
+	* config/i386/i386.c (dimode_scalar_chain::convert_op): Avoid
+	sharing the SUBREG rtx between move and following insn.
+
+	* ira.c (ira_update_equiv_info_by_shuffle_insn): Use copy_rtx
+	for REG_EQUIV argument.
+
+2016-11-30  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/t-rmprofile: Add mappings for Cortex-M23 and Cortex-M33.
+
+2016-11-30  Markus Trippelsdorf  <markus@trippelsdorf.de>
+
+	PR ipa/78555
+	* real.c (real_hash): Add cast to avoid left
+	shifting of negative values.
+
+2016-11-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/78362
+	* config/aarch64/aarch64.md (add<mode>3): Extract inner expression
+	from a subreg in operands[1] and don't call REGNO on a non-reg
+	expression when deciding to force operands[2] into a reg.
+
+2016-11-30  Claudiu Zissulescu  <claziss@synopsys.com>
+	    Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* config/arc/arc-protos.h (arc_store_addr_hazard_p): Declare.
+	* config/arc/arc.c (arc_store_addr_hazard_p): New function.
+	(workaround_arc_anomaly): Call arc_store_addr_hazard_p for ARC700.
+	* config/arc/arc700.md: Add define_bypass for store/load.
+
+2016-11-30  Martin Liska  <mliska@suse.cz>
+
+	* cgraph.c (symbol_table::initialize): Initialize
+	ipa_clones_dump_file.
+	(cgraph_node::remove): Report to ipa_clones_dump_file.
+	* cgraph.h: Add new argument (suffix) to cloning methods.
+	* cgraphclones.c (dump_callgraph_transformation): New function.
+	(cgraph_node::create_clone): New argument.
+	(cgraph_node::create_virtual_clone): Likewise.
+	(cgraph_node::create_version_clone): Likewise.
+	* dumpfile.c: Add .ipa-clones dump file.
+	* dumpfile.h (enum tree_dump_index): Add TDI_clones
+	* ipa-inline-transform.c (clone_inlined_nodes): Report operation
+	to dump_callgraph_transformation.
+
+2016-11-30  Martin Liska  <mliska@suse.cz>
+
+	PR sanitizer/78541
+	* asan.c (asan_expand_mark_ifn): Properly
+	select a VAR_DECL from FRAME.* component reference.
+
+2016-11-30  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78583
+	* simplify-rtx.c (simplify_truncation): Add check missing from the
+	previous commit.
+
+2016-11-30  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78590
+	* combine.c (change_zero_ext): Transform zero_extend of subregs only
+	if the subreg_reg is a scalar integer mode.
+
+2016-11-30  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/78586
+	* gimple-ssa-sprintf.c (format_integer): Use TYPE_MAX_VALUE or
+	TYPE_MIN_VALUE or build_all_ones_cst instead of folding LSHIFT_EXPR.
+	Don't build_int_cst min/max twice.  Formatting fix.
+
+2016-11-30  Markus Trippelsdorf  <markus@trippelsdorf.de>
+
+	PR rtl-optimization/78588
+	* combine.c (if_then_else_cond): Also guard against BLKmode.
+	* rtlanal.c (num_sign_bit_copies1): Add assert.
+
+2016-11-29  Jeff Law  <law@redhat.com>
+
+	* common/config/arc/arc-common.c (arc_handle_option): Remove unused
+	variables.
+
+	* lra-constraints.c (check_and_process_move): Constrain the
+	range of DCLASS and SCLASS to avoid false positive out of bounds
+	array index warning.
+
+2016-11-29  David Malcolm  <dmalcolm@redhat.com>
+
+	* doc/install.texi (--with-target-bdw-gc): Remove stray '@'.
+
+2016-11-29  David Malcolm  <dmalcolm@redhat.com>
+
+	PR preprocessor/78569
+	* input.c (get_substring_ranges_for_loc): Fail gracefully if
+	line directives were present.
+
+2016-11-30  Matthias Klose  <doko@ubuntu.com>
+
+	* doc/install.texi: Document configure options --enable-objc-gc
+	and --with-target-bdw-gc.
+
+2016-11-29  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/78594
+	* config/rs6000/rs6000.md (mov<mode>_internal, QHI iterator): Add
+	'x' to stxsi<wd>x print pattern, so that QImode and HImode values
+	residing in traditional altivec registers can be stored
+	correctly.
+
+2016-11-29  Max Filippov  <jcmvbkbc@gmail.com>
+
+	PR target/78603
+	* config/xtensa/xtensa.c (hwloop_optimize): Don't emit zero
+	overhead loop start between a call and its CALL_ARG_LOCATION
+	note.
+
+2016-11-29  Waldemar Brodkorb  <wbx@openadk.org>
+
+	* config/bfin/linux.h (CPP_SPEC): Define.
+
+2016-11-29  Martin Sebor  <msebor@redhat.com>
+
+	PR tree-optimization/78512
+	* config/linux.h (TARGET_PRINTF_POINTER_FORMAT): Remove.
+	* config/rs6000/linux.h: Same.
+	* config/rs6000/linux64.h: Same.
+	* config/sol2.h: Same.
+	* config/sol2.c (solaris_printf_pointer_format): Remove.
+	* doc/tm.texi.in (TARGET_PRINTF_POINTER_FORMAT): Remove.
+	* doc/tm.texi: Regenerate.
+	* gimple-ssa-sprintf.c (format_pointer): Rempove.
+	(pass_sprintf_length::compute_format_length): Return bool.
+	(pass_sprintf_length::handle_gimple_call): Adjust.
+	* target.def (printf_pointer_format): Remove.
+	* targhooks.c (default_printf_pointer_format): Remove.
+	(linux_printf_pointer_format): Same.
+	* targhooks.h (default_printf_pointer_format): Remove.
+	(linux_printf_pointer_format, solaris_printf_pointer_format): Same.
+
+2016-11-29  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/sse.md (UNSPEC_MASKOP): Move from i386.md.
+	(mshift): Ditto.
+	(SWI1248_AVX512BWDQ): Ditto.
+	(SWI1248_AVX512BW): Ditto.
+	(k<any_logic:code><mode>): Ditto.
+	(kandn<mode>): Ditto.
+	(kxnor<mode>): Ditto.
+	(knot<mode>): Ditto.
+	(*k<any_lshift:code><mode>): Ditto.
+	(kortestzhi, kortestchi): Ditto.
+	(kunpckhi, kunpcksi, kunpckdi): Ditto.
+
+2016-11-29  Andrew Pinski  <apinski@cavium.com>
+
+	* tree-vrp.c (simplify_stmt_using_ranges): Use boolean_type_node
+	for the EQ_EXPR.
+
+2016-11-29  Chen Gang  <gang.chen.5i5j@gmail.com>
+
+	PR target/71331
+	* config/tilegx/tilegx.c (tilegx_function_profiler): Save r10
+	to stack before call mcount.
+	(tilegx_can_use_return_insn_p): Clean up code.
+
+2016-11-29  Pitchumani Sivanupandi <pitchumani.s@atmel.com>
+
+	* config/avr/avr-mcu.def: (avr_mcu_types): Add flash size info.
+
+2016-11-29  David Malcolm  <dmalcolm@redhat.com>
+
+	PR c++/72774
+	PR c++/72786
+	PR c++/77922
+	PR c++/78313
+	* spellcheck.c (selftest::test_find_closest_string): Verify that
+	we don't offer the goal string as a suggestion.
+	* spellcheck.h (best_match::get_best_meaningful_candidate): Don't
+	offer the goal string as a suggestion.
+
+
+2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.c (arc_override_options): Avoid selection of
+	compact casesi for ARCv2.
+
+2016-11-29  Richard Biener  <rguenther@suse.de>
+
+	* tree-cfg.c (lower_phi_internal_fn): Do not look for further
+	PHIs after a regular stmt.
+	(stmt_starts_bb_p): PHIs not preceeded by a PHI or a label
+	start a new BB.
+
+2016-11-29  Martin Liska  <mliska@suse.cz>
+
+	PR gcov-profile/78582
+	* tree-profile.c (gimple_gen_time_profiler): Make one extra BB
+	to prevent PHI argument clash.
+
+2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.opt (marclinux): Fix typo.
+	(marclinux_prof): Likewise.
+
+2016-11-29  Jiong Wang  <jiong.wang@arm.com>
+
+	* target.def (stack_protect_runtime_enabled_p): New.
+	* function.c (expand_function_end): Guard stack_protect_epilogue with
+	targetm.stack_protect_runtime_enabled_p.
+	* cfgexpand.c (pass_expand::execute): Likewise.
+	* calls.c (expand_call): Likewise.
+	* doc/tm.texi.in (TARGET_STACK_PROTECT_RUNTIME_ENABLED_P): Add it.
+	* doc/tm.texi: Regenerate.
+
+2016-11-29  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/78546
+	* match.pd: Add CST1 - (CST2 - A) -> CST3 + A missing case.
+
+2016-11-29  Janus Weil  <janus@gcc.gnu.org>
+
+	* doc/contrib.texi: Add a few missing gfortran contributors.
+
+2016-11-29  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* combine.c (change_zero_ext): Also handle extends from a subreg
+	to a mode bigger than that of the operand of the subreg.
+
+2016-11-29  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/77687
+	* config/rs6000/rs6000.c (rs6000_emit_stack_reset): Emit the
+	stack_restore_tie insn instead of stack_tie, for the SVR4 and
+	SPE ABIs.
+	* config/rs6000/rs6000.md (stack_restore_tie): New define_insn.
+
+2016-11-28  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* shrink-wrap.c (init_separate_shrink_wrap): Do not clear
+	head_components and tail_components.
+	(spread_components): New algorithm.
+	(emit_common_tails_for_components): Clear head_components and
+	tail_components.
+	(insert_prologue_epilogue_for_components): Write extra output to the
+	dump file for sibcalls and abnormal exits.
+
+2016-11-28  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78342
+	* combine.c: Include "cfghooks.h".
+	(try_combine): If we create an unconditional trap, break the basic
+	block in two just after it, and remove the edge between; also, set
+	the *new_direct_jump_p flag so that cleanup_cfg is run.
+
+2016-11-28  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* simplify-rtx.c (simplify_truncation): Handle truncate of zero_extract
+	and sign_extract.
+
+2016-11-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*and<mode>_1): Merge insn pattern from
+	*andsi_1 and *andhi_1 using SWI24 mode iterator.  Use multi-line
+	output template string.
+	(*anddi_1): Use multi-line output template string.
+	(*andqi_1): Ditto.
+
+2016-11-28  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/78540
+	* rtl.h (remove_reg_equal_equiv_notes): Return bool instead of void.
+	* rtlanal.c (remove_reg_equal_equiv_notes): Return true if any
+	note has been removed.
+	* postreload.c (reload_combine_recognize_pattern): If
+	remove_reg_equal_equiv_notes returns true, call df_notes_rescan.
+
+2016-11-28  Martin Sebor  <msebor@redhat.com>
+
+	PR middle-end/78520
+	* gimple-ssa-sprintf.c (target_max_value): Remove.
+	(target_int_max, target_size_max): Use TYPE_MAX_VALUE.
+	(get_width_and_precision): New function.
+	(format_integer, format_floating, get_string_length, format_string):
+	Correct handling of width and precision with unknown value.
+	(format_directive): Add warning.
+	(pass_sprintf_length::compute_format_length): Allow for precision
+	to consist of a sole period with no asterisk or digits after it.
+
+2016-11-28  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/78546
+	* simplify-rtx.c (neg_const_int): When negating most negative
+	number in mode wider than HOST_BITS_PER_WIDE_INT, use
+	simplify_const_unary_operation to produce CONST_DOUBLE or
+	CONST_WIDE_INT.
+	(simplify_plus_minus): Handle the case where neg_const_int
+	doesn't return a CONST_INT.
+
+2016-11-28  Markus Trippelsdorf  <markus@trippelsdorf.de>
+
+	PR target/78556
+	* config/rs6000/rs6000.c (vspltis_constant): Add casts to avoid
+	left shifting of negative values.
+
+2016-11-28  Jakub Jelinek  <jakub@redhat.com>
+
+	PR fortran/78298
+	* tree-nested.c (convert_local_reference_stmt): After adding
+	shared (FRAME.NN) clause to omp parallel, task or target,
+	add it also to all outer omp parallel, task or target constructs.
+
+2016-11-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (UNSPEC_KMASKOP): New.
+	(UNSPEC_KMOV): Remove.
+	(kmovw): Expand to plain HImode move.
+	(k<any_logic:code><mode>): Rename from *k<logic><mode>. Use
+	register_operand predicates.  Tag pattern with UNSPEC_KMASKOP.
+	Remove corresponding clobber-removing splitter.
+	(*anddi_1): Remove mask register alternatives.
+	(*andsi_1): Ditto.
+	(*andhi_1): Ditto.
+	(*andqi_1): Ditto.
+	(*<any_or:code><mode>_1): Ditto.
+	(*<any_or:code>qi_1): Ditto.
+	(kandn<mode>): Use SWI1248_AVX512BW mode iterator.  Remove
+	general register alternatives.  Tag pattern with UNSPEC_KMASKOP.
+	Remove corresponding splitter to operation with general registers.
+	(*andn<SWI38:mode>): Rename from *bmi_andn_<mode>.
+	(*andn<SWI12:mode>): New pattern.
+	(*kxnor<mode>): Remove general register alternatives.  Tag pattern
+	with UNSPEC_KMASKOP.  Remove corresponding splitter to operation
+	with general registers.
+	(knot<mode>): New insn pattern.
+	(*one_cmpl<mode>2_1): Remove mask register alternatives.
+	(one_cmplqi2_1): Ditto.
+	(*k<any_lshift:code><mode>): Rename from *k<mshift><mode>3.
+	Tag pattern with UNSPEC_KMASKOP. Add mode attribute.
+	* config/i386/predicates.md (mask_reg_operand): Remove predicate.
+	* config/i386/sse.md (vec_unpacks_hi_hi): Update pattern
+	to generate kmaskop shift.
+	(vec_unpacks_hi_<mode>): Ditto.
+	* config/i386/i386-builtin.def (__builtin_ia32_kandhi):
+	Use CODE_FOR_kandhi.
+	(__builtin_ia32_knothi): Use CODE_FOR_knothi.
+	(__builtin_ia32_korhi): Use CODE_FOR_kiorhi.
+	(__builtin_ia32_kxorhi): Use CODE_FOR_kxorhi.
+
+2016-11-28  Richard Biener  <rguenther@suse.de>
+
+	* tree-vrp.c (vrp_visit_assignment_or_call): Handle simplifications
+	to SSA names via extract_range_from_ssa_name if allowed.
+
+2016-11-28  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78542
+	* tree-ssa-ccp.c (evaluate_stmt): Only valueize simplification
+	if allowed.
+
+2016-11-28  Paolo Bonzini  <bonzini@gnu.org>
+
+	* combine.c (simplify_if_then_else): Simplify IF_THEN_ELSE that
+	isolates a single bit, even if the condition involves subregs.
+
+2016-11-28  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/aarch64-simd-builtins.def
+	(BSL_P): Added di and v2di mode.
+	* config/aarch64/arm_neon.h
+	(vsriq_n_p64, vsri_n_p64): Added poly type.
+	(vextq_p64, vext_p64): Likewise.
+	(vceq_p64, vbslq_p64, vbsl_p64): Likewise.
+
+2016-11-28  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/aarch64-builtins.c (TYPES_SETREGP): Added poly type.
+	(TYPES_GETREGP): Likewise.
+	(TYPES_SHIFTINSERTP): Likewise.
+	(TYPES_COMBINEP): Likewise.
+	(TYPES_STORE1P): Likewise.
+	* config/aarch64/aarch64-simd-builtins.def
+	(combine): Added poly generator.
+	(get_dregoi): Likewise.
+	(get_dregci): Likewise.
+	(get_dregxi): Likewise.
+	(ssli_n): Likewise.
+	(ld1): Likewise.
+	(st1): Likewise.
+	* config/aarch64/arm_neon.h
+	(poly64x1x2_t, poly64x1x3_t): New.
+	(poly64x1x4_t, poly64x2x2_t): Likewise.
+	(poly64x2x3_t, poly64x2x4_t): Likewise.
+	(poly64x1_t): Likewise.
+	(vcreate_p64, vcombine_p64): Likewise.
+	(vdup_n_p64, vdupq_n_p64): Likewise.
+	(vld2_p64, vld2q_p64): Likewise.
+	(vld3_p64, vld3q_p64): Likewise.
+	(vld4_p64, vld4q_p64): Likewise.
+	(vld2_dup_p64, vld3_dup_p64): Likewise.
+	(vld4_dup_p64, vsli_n_p64): Likewise.
+	(vsliq_n_p64, vst1_p64): Likewise.
+	(vst1q_p64, vst2_p64): Likewise.
+	(vst3_p64, vst4_p64): Likewise.
+	(__aarch64_vdup_lane_p64, __aarch64_vdup_laneq_p64): Likewise.
+	(__aarch64_vdupq_lane_p64, __aarch64_vdupq_laneq_p64): Likewise.
+	(vget_lane_p64, vgetq_lane_p64): Likewise.
+	(vreinterpret_p8_p64, vreinterpretq_p8_p64): Likewise.
+	(vreinterpret_p16_p64, vreinterpretq_p16_p64): Likewise.
+	(vreinterpret_p64_f16, vreinterpret_p64_f64): Likewise.
+	(vreinterpret_p64_s8, vreinterpret_p64_s16): Likewise.
+	(vreinterpret_p64_s32, vreinterpret_p64_s64): Likewise.
+	(vreinterpret_p64_f32, vreinterpret_p64_u8): Likewise.
+	(vreinterpret_p64_u16, vreinterpret_p64_u32): Likewise.
+	(vreinterpret_p64_u64, vreinterpret_p64_p8): Likewise.
+	(vreinterpretq_p64_f64, vreinterpretq_p64_s8): Likewise.
+	(vreinterpretq_p64_s16, vreinterpretq_p64_s32): Likewise.
+	(vreinterpretq_p64_s64, vreinterpretq_p64_f16): Likewise.
+	(vreinterpretq_p64_f32, vreinterpretq_p64_u8): Likewise.
+	(vreinterpretq_p64_u16, vreinterpretq_p64_u32): Likewise.
+	(vreinterpretq_p64_u64, vreinterpretq_p64_p8): Likewise.
+	(vreinterpret_f16_p64, vreinterpretq_f16_p64): Likewise.
+	(vreinterpret_f32_p64, vreinterpretq_f32_p64): Likewise.
+	(vreinterpret_f64_p64, vreinterpretq_f64_p64): Likewise.
+	(vreinterpret_s64_p64, vreinterpretq_s64_p64): Likewise.
+	(vreinterpret_u64_p64, vreinterpretq_u64_p64): Likewise.
+	(vreinterpret_s8_p64, vreinterpretq_s8_p64): Likewise.
+	(vreinterpret_s16_p64, vreinterpret_s32_p64): Likewise.
+	(vreinterpretq_s32_p64, vreinterpret_u8_p64): Likewise.
+	(vreinterpret_u16_p64, vreinterpretq_u16_p64): Likewise.
+	(vreinterpret_u32_p64, vreinterpretq_u32_p64): Likewise.
+	(vset_lane_p64, vsetq_lane_p64): Likewise.
+	(vget_low_p64, vget_high_p64): Likewise.
+	(vcombine_p64, vst2_lane_p64): Likewise.
+	(vst3_lane_p64, vst4_lane_p64): Likewise.
+	(vst2q_lane_p64, vst3q_lane_p64): Likewise.
+	(vst4q_lane_p64, vget_lane_p64): Likewise.
+	(vget_laneq_p64, vset_lane_p64): Likewise.
+	(vset_laneq_p64, vcopy_lane_p64): Likewise.
+	(vcopy_laneq_p64, vdup_n_p64): Likewise.
+	(vdupq_n_p64, vdup_lane_p64): Likewise.
+	(vdup_laneq_p64, vld1_p64): Likewise.
+	(vld1q_p64, vld1_dup_p64): Likewise.
+	(vld1q_dup_p64, vld1q_dup_p64): Likewise.
+	(vmov_n_p64, vmovq_n_p64): Likewise.
+	(vst3q_p64, vst4q_p64): Likewise.
+	(vld1_lane_p64, vld1q_lane_p64): Likewise.
+	(vst1_lane_p64, vst1q_lane_p64): Likewise.
+	(vcopy_laneq_p64, vcopyq_laneq_p64): Likewise.
+	(vdupq_laneq_p64): Likewise.
+
+2016-11-28  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/arm/arm_neon.h (vget_lane_p64): New.
+
+2016-11-28  Iain Sandoe  <iain@codesourcery.com>
+
+	PR target/71767
+	* configure.ac (with_ld64): Use portable method to extract the
+	major part of the version number.
+	* configure: Regenerated.
+
+2016-11-28  Jakub Jelinek  <jakub@redhat.com>
+
+	* gimple-ssa-sprintf.c (build_intmax_type_nodes): Look at
+	UINTMAX_TYPE rather than SIZE_TYPE.  Add gcc_unreachable if
+	intmax_t couldn't be determined.
+	(format_integer): Make {,u}intmax_type_node no longer static,
+	initialize them only when needed.  For z and t use
+	signed_or_unsigned_type_for instead of assuming size_t and
+	ptrdiff_t have the same precision.
+
+	PR lto/78211
+	* ipa-icf.h (sem_item_optimizer): Add m_classes_vec member.
+	* ipa-icf.c (sem_item_optimizer::sem_item_optimizer): Initialize it.
+	(sem_item_optimizer::~sem_item_optimizer): Traverse m_classes_vec
+	vector instead of traversing m_classes hash table.  Release
+	m_classes_vec.
+	(sem_item_optimizer::read_section, sem_item_optimizer::add_class):
+	Formatting fixes.
+	(sem_item_optimizer::get_group_by_hash): When inserting a new group,
+	add it also to m_classes_vec vector.
+	(sem_item_optimizer::remove_symtab_node,
+	sem_item_optimizer::build_hash_based_classes,
+	sem_item_optimizer::parse_nonsingleton_classes): Formatting fixes.
+	(sem_item_optimizer::subdivide_classes_by_equality,
+	sem_item_optimizer::subdivide_classes_by_sensitive_refs,
+	sem_item_optimizer::verify_classes): Traverse m_classes_vec vector
+	instead of traversing m_classes hash table.  Formatting fixes.
+	(sem_item_optimizer::traverse_congruence_split,
+	sem_item_optimizer::do_congruence_step_for_index,
+	sem_item_optimizer::do_congruence_step): Formatting fixes.
+	(sem_item_optimizer::process_cong_reduction): Traverse m_classes_vec
+	vector instead of traversing m_classes hash table.
+	(sem_item_optimizer::dump_cong_classes): Likewise.  Formatting fixes.
+	(sem_item_optimizer::merge_classes): Traverse m_classes_vec vector
+	instead of traversing m_classes hash table.
+
+2016-11-28  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.c (out_movhi_r_mr) [REG_X + PLUS]: Only SBIW if
+	X is not unused after.
+
+2016-11-28  Bernd Schmidt  <bschmidt@redhat.com>
+
+	PR rtl-optimization/78120
+	* rtlanal.c (insn_rtx_cost): Revert previous change.
+
+2016-11-28  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR 41076
+	* config/avr/avr.md (SPLIT34): New mode iterator.
+	(bitop): New code iterator.
+	(*iorhi3.ashift8-*). New insn-and-split patterns.
+	(*movhi): Post-reload split reg = 0.
+	[!MOVW]: Post-reload split reg = reg.
+	(*mov<mode>) [SI,SF,PSI,SQ,USQ,SA,USA]: Post-reload split reg = reg.
+	(andhi3, andpsi3, andsi3): Post-reload split reg-reg operations.
+	(iorhi3, iorpsi3, iorsi3): Same.
+	(xorhi3, xorpsi3, xorsi3): Same.
+	* config/avr/avr.c (avr_rtx_costs_1) [IOR && HImode]: Adjust rtx
+	costs to *iorhi3.ashift8-* patterns.
+
+2016-11-27  Iain Sandoe  <iain@codesourcery.com>
+	    Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	PR target/67710
+	* config.in: Regenerate
+	* config/darwin-driver.c (darwin_driver_init): Emit a version string
+	for the assembler.
+	* config/darwin.h(ASM_MMACOSX_VERSION_MIN_SPEC): New, new tests.
+	* config/darwin.opt(asm_macosx_version_min): New.
+	* config/i386/darwin.h: Handle ASM_MMACOSX_VERSION_MIN_SPEC.
+	* configure: Regenerate
+	* configure.ac: Check for mmacosx-version-min handling.
+
+2016-11-27  Iain Sandoe  <iain@codesourcery.com>
+
+	PR target/57438
+	* config/i386/i386.c (ix86_code_end): Note that we emitted code
+	where the function might otherwise appear empty for picbase thunks.
+	(ix86_output_function_epilogue): If we find a zero-sized function
+	assume that reaching it is UB and trap.  If we find a trailing label
+	append a nop.
+	* config/rs6000/rs6000.c (rs6000_output_function_epilogue): If we
+	find a zero-sized function assume that reaching it is UB and trap.
+	If we find a trailing label, append a nop.
+
+2016-11-27  Iain Sandoe  <iain@codesourcery.com>
+
+	PR target/71767
+	* config/darwin-sections.def (picbase_thunk_section): New.
+	* config/darwin.c (darwin_init_sections): Set up picbase thunk
+	section. (darwin_rodata_section, darwin_objc2_section,
+	machopic_select_section, darwin_asm_declare_constant_name,
+	darwin_emit_weak_or_comdat, darwin_function_section): Don’t use
+	coalesced with newer linkers.
+	(darwin_override_options): Decide on usage of coalesed sections
+	on the basis of the target linker version.
+	* config/darwin.h (MIN_LD64_NO_COAL_SECTS): New.
+	* config/darwin.opt  (mtarget-linker): New.
+	* config/i386/i386.c (ix86_code_end): Do not force the thunks into
+	a coalesced section, instead use a thunks section.
+
+2016-11-27  Iain Sandoe  <iain@codesourcery.com>
+
+	PR target/71767
+	* configure.ac (with-ld64): New var, set for Darwin, set on
+	detection of ld64, gcc_cv_ld64_export_dynamic: New, New test.
+	* config/darwin.h: Use LD64_HAS_DYNAMIC export. DEF_LD64: New, define.
+	* config/darwin10.h(DEF_LD64): Update for this target version.
+	* config/darwin12.h(LINK_GCC_C_SEQUENCE_SPEC): Remove rdynamic test.
+	(DEF_LD64): Update for this target version.
+	* configure: Regenerated.
+	* config.in: Regenerated.
+
+2016-11-27  Iain Sandoe  <iain@codesourcery.com>
+
+	PR target/71767
+	* config/darwin.c (imachopic_indirection_name): Make data
+	section indirections linker-visible.
+	* config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): Make local
+	constant labels linker-visible.
+
+2016-11-26  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	* tree.c (build_common_tree_nodes): Initialize ptrdiff_type_node.
+	(free_lang_data): Remove assignment to ptrdiff_type_node.
+
+2016-11-25  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/78526
+	* simplify-rtx.c (simplify_immed_subreg): Don't use wi::extract_uhwi
+	beyond val's precision.
+
+	PR rtl-optimization/78527
+	* combine.c (make_compound_operation_int): Ignore LSHIFTRT with
+	out of bounds shift count.
+
+2016-11-25  Martin Liska  <mliska@suse.cz>
+
+	PR web/71666
+	* doc/invoke.texi (-fprofile-use): Fix reference to a section
+	where -fprofile-generate is documented.
+
+2016-11-25  Martin Liska  <mliska@suse.cz>
+
+	PR gcov-profile/78086
+	* coverage.c (build_init_ctor): Don't use priority {cd}tors if
+	not supported by a target.  Set priority to 100 if possible.
+	(build_gcov_exit_decl): Likewise.
+
+2016-11-25  Richard Biener  <rguenther@suse.de>
+
+	PR ipa/78515
+	* ipa-prop.c (compute_complex_assign_jump_func): Properly identify
+	unary, binary and single RHSs.
+	* tree.def (BIT_INSERT_EXPR): Adjust tree code name.
+
+2016-11-25  Bin Cheng  <bin.cheng@arm.com>
+
+	PR middle-end/78507
+	PR middle-end/78510
+	PR middle-end/78517
+	* match.pd ((cond (cmp (convert1? @1) @3) (convert2? @1) @2)): Use
+	cmp directly, rather than cmp_code.  Initialize code to ERROR_MARK
+	and set it to result code if transformation is valid.  Use code EQ
+	directly in last simplification case.
+
+2016-11-25  Richard Biener  <rguenther@suse.de>
+
+	* gimple-fold.c (fold_stmt_1): Check may_propagate_copy
+	before valueizing return stmts.
+
+2016-11-24  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78343
+	* passes.def: Add CD-DCE pass after loop splitting.
+	* tree-ssa-dce.c (find_obviously_necessary_stmts): Move
+	SCEV init/finalize ...
+	(perform_tree_ssa_dce): ... here.  Deal with being
+	executed inside the loop pipeline in aggressive mode.
+
+2016-11-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* tree-ssa-math-opts.c (struct symbolic_number): Improve comment.
+
+2016-11-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	PR tree-optimization/77673
+	* tree-ssa-math-opts.c (struct symbolic_number): Add new src field.
+	(init_symbolic_number): Initialize src field from src parameter.
+	(perform_symbolic_merge): Select most dominated statement as the
+	source statement.  Set src field of resulting n structure from the
+	input src with the lowest address.
+	(find_bswap_or_nop): Rename source_stmt into ins_stmt.
+	(bswap_replace): Rename src_stmt into ins_stmt.  Initially get source
+	of load from src field rather than insertion statement.  Cancel
+	optimization if statement analyzed is not dominated by the insertion
+	statement.
+	(pass_optimize_bswap::execute): Rename src_stmt to ins_stmt.  Compute
+	dominance information.
+
+2016-11-25  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR ada/67205
+	* config/mips/mips.c (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Define.
+
+2016-11-25  Martin Jambor  <mjambor@suse.cz>
+
+	PR tree-optimization/70965
+	* passes.def (pass_build_ssa_passes): Add pass_rebuild_cgraph_edges.
+
+2016-11-24  James Greenahlgh  <james.greenhalgh@arm.com>
+
+	PR target/78509
+	* config/i386/i386.c (i386_excess_precision): Do not return
+	FLT_EVAL_METHOD_UNPREDICTABLE when "type" is
+	EXCESS_PRECISION_TYPE_STANDARD.
+	* target.def (excess_precision): Document that targets should
+	not return FLT_EVAL_METHOD_UNPREDICTABLE when "type" is
+	EXCESS_PRECISION_TYPE_STANDARD or EXCESS_PRECISION_TYPE_FAST.
+	Fix typo in first sentence.
+	* doc/tm.texi: Regenerate.
+
+2016-11-25  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78396
+	* tree-vectorizer.c (vectorize_loops): When the if-converted
+	body contains masked loads or stores do not attempt to
+	basic-block-vectorize it.
+
+2016-11-25  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* function.h (spill_slot_alignment): Declare.
+	* function.c (spill_slot_alignment): New function.
+	* lra-spills.c (slot): Add align and size fields.
+	(assign_mem_slot): Use them in the call to assign_stack_local.
+	(add_pseudo_to_slot): Update the fields.
+	(assign_stack_slot_num_and_sort_pseudos): Initialise the fields.
+
+2016-11-25  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* stor-layout.c (layout_type): Allow the caller to set the mode of
+	a float type.  Only choose one here if the mode is still VOIDmode.
+	* tree.c (build_common_tree_nodes): Set the type mode of decimal
+	floats before calling layout_type.
+	* config/rs6000/rs6000.c (rs6000_init_builtins): Likewise.
+
+2016-11-25  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-tailcall.c (find_tail_calls): Allow calls to reference
+	local variables if all references are known to be direct.
+
+2016-11-25  Jakub Jelinek  <jakub@redhat.com>
+	    Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR middle-end/78501
+	* tree-vrp.c (extract_range_basic): Check for ptrdiff_type_node to be
+	non null and it's precision matches precision of lhs's type.
+
+2016-11-24  Martin Sebor  <msebor@redhat.com>
+
+	PR tree-optimization/78476
+	* gimple-ssa-sprintf.c (struct pass_sprintf_length::call_info):
+	Add a member.
+	(handle_gimple_call): Adjust signature.
+	(try_substitute_return_value): Remove calls to bounded functions
+	with zero buffer size whose result is known.
+	(pass_sprintf_length::execute): Adjust call to handle_gimple_call.
+
+2016-11-24  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* varasm.c (assemble_start_function): Wrap align_log definition in
+	ASM_OUTPUT_MAX_SKIP_ALIGN.
+
+2016-11-24  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (wide AND insn to QImode splitter): Use
+	explicit mode macros.
+	(wide OR insn to QImode splitter): Ditto.
+
+2016-11-24  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/77541
+	* lra-constraints.c (struct input_reload): Add field match_p.
+	(get_reload_reg): Check modes of input reloads to generate unique
+	value reload pseudo.
+	(match_reload): Add input reload pseudo for the current insn.
+
+2016-11-24  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Update
+	__FLT_EVAL_METHOD__ and __FLT_EVAL_METHOD_C99__ when we switch
+	architecture levels.
+	* config/aarch64/aarch64.c (aarch64_promoted_type): Only promote
+	the aarch64_fp16_type_node, not all HFmode types.
+	(aarch64_libgcc_floating_mode_supported_p): Support HFmode.
+	(aarch64_scalar_mode_supported_p): Likewise.
+	(aarch64_excess_precision): New.
+	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
+	(TARGET_SCALAR_MODE_SUPPORTED_P): Likewise.
+	(TARGET_C_EXCESS_PRECISION): Likewise.
+
+2016-11-24  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64-c.c (aarch64_scalar_mode_supported_p): New.
+	(TARGET_SCALAR_MODE_SUPPORTED_P): Define.
+
+2016-11-24  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64.md (<optab>sihf2): Convert to expand.
+	(<optab>dihf2): Likewise.
+	(aarch64_fp16_<optab><mode>hf2): New.
+
+2016-11-24  Alexander Monakov  <amonakov@ispras.ru>
+
+	PR target/67822
+	* config/nvptx/mkoffload.c (main): Allow -fopenmp.
+
+2016-11-24  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* common/config/sparc/sparc-common.c (sparc_option_optimization_table):
+	Enable REE at -O2 and higher.
+	* config/sparc/sparc.c (sparc_option_override): Disable it by default
+	in 32-bit mode.
+
+2016-11-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/48863
+	PR inline-asm/70184
+	* tree-ssa-ter.c (temp_expr_table): Add reg_vars_cnt field.
+	(new_temp_expr_table): Initialise reg_vars_cnt.
+	(free_temp_expr_table): Release reg_vars_cnt.
+	(process_replaceable): Add reg_vars_cnt argument, set reg_vars_cnt
+	field of TAB.
+	(find_replaceable_in_bb): Use the above to record register variable
+	write occurrences and cancel replacement across them.
+
+2016-11-24  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR rtl-optimization/78437
+	* ree.c (get_uses): New function.
+	(combine_reaching_defs): When a copy is needed, return false if any
+	reaching use of the source register reads it in a mode larger than
+	the mode it is set in and WORD_REGISTER_OPERATIONS is true.
+
+2016-11-24  Martin Liska  <mliska@suse.cz>
+
+	* gimple-pretty-print.c (dump_edge_probability): New function.
+	(dump_gimple_switch): Dump label edge probabilities.
+	(dump_gimple_cond): Likewise.
+	(dump_gimple_label): Dump
+	(dump_gimple_bb_header): Dump basic block frequency.
+	(pp_cfg_jump): Replace e->dest argument with e.
+	(dump_implicit_edges): Likewise.
+	* tree-ssa-loop-ivopts.c (get_scaled_computation_cost_at):
+	Use gimple_bb (at) instead of at->bb.
+
+2016-11-24  Bernd Schmidt  <bschmidt@redhat.com>
+
+	* common.opt (flimit-function-alignment): New.
+	* doc/invoke.texi (-flimit-function-alignment): Document.
+	* emit-rtl.h (struct rtl_data): Add max_insn_address field.
+	* final.c (shorten_branches): Set it.
+	* varasm.c (assemble_start_function): Limit alignment if
+	requested.
+
+2016-11-24  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/71595
+	* cfgloopmanip.h (remove_path): Add irred_invalidated and
+	loop_closed_ssa_invalidated parameters, defaulted to NULL.
+	* cfgloopmanip.c (remove_path): Likewise, pass them along to
+	called functions.  Only fix irred flags if the caller didn't
+	request state.
+	* tree-ssa-loop-ivcanon.c (unloop_loops): Use add_bb_to_loop.
+	(unloop_loops): Pass irred_invalidated and loop_closed_ssa_invalidated
+	to remove_path.
+
+2016-11-24  Bernd Schmidt  <bschmidt@redhat.com>
+
+	PR rtl-optimization/78120
+	* ifcvt.c (noce_conversion_profitable_p): Check original cost in all
+	cases, and additionally test against max_seq_cost for speed
+	optimization.
+	(noce_process_if_block): Compute an estimate for the original cost when
+	optimizing for speed, using the minimum of then and else block costs.
+
+	PR rtl-optimization/78120
+	* rtlanal.c (insn_rtx_cost): Use set_rtx_cost.
+
+	PR rtl-optimization/78120
+	* config/i386/i386.c (ix86_rtx_costs): Fully handle SETs.
+
+2016-11-24  Bin Cheng  <bin.cheng@arm.com>
+
+	* match.pd: Refine type conversion in result expr for below pattern:
+	(cond (cmp (convert1? x) c1) (convert2? x) c2) -> (minmax (x c)).
+
+2016-11-24  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR middle-end/78429
+	* tree.h (wi::fits_to_boolean_p): New predicate.
+	(wi::fits_to_tree_p): Use it for boolean types.
+	* tree.c (int_fits_type_p): Likewise.
+
+2016-11-24  Martin Liska  <mliska@suse.cz>
+
+	* print-tree.c (struct bucket): Remove.
+	(print_node): Add new argument which drives whether a tree node
+	is printed briefly or not.
+	(debug_tree): Replace a custom hash table with hash_set<T>.
+	* print-tree.h (print_node): Add the argument.
+
+2016-11-24  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	* config/nios2/nios2.c (nios2_init_libfuncs): Add ATTRIBUTE_UNUSED.
+
+2016-11-23  Peter Bergner  <bergner@vnet.ibm.com>
+
+	PR target/78458
+	* config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Return MODE
+	if it is at least NREGS wide.
+
+2016-11-23  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p): For
+	TARGET_E500_DOUBLE. handle TDmode, TImode and PTImode the same as
+	TFmode, IFmode and KFmode.
+
+2016-11-23  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/rs6000/spe.md (*frob_<SPE64:mode>_ti_8): New insn
+	pattern.
+
+2016-11-23  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* combine.c (change_zero_ext): Only change the mode of a hard register
+	destination if can_change_dest_mode holds for that.
+
+2016-11-23  Jeff Law  <law@redhat.com>
+
+	* varasm.c (assemble_name): Increase buffer size for name.
+
+	* config/spu/spu.md (floatunsdidf2): Remove unused local variable.
+
+2016-11-23  Jakub Kicinski  <jakub.kicinski@netronome.com>
+
+	* doc/extend.texi: Constify first argument to __builtin_object_size.
+
+2016-11-23  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	* opth-gen.awk: Use unsigned shifts for bit masks.  Allow all bits
+	to be used.  Add brackets around macro argument.
+
+2016-11-23  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*<any_or:code>hi_1): Fix operand 2 constraints.
+
+2016-11-23  Jakub Jelinek  <jakub@redhat.com>
+
+	PR sanitizer/69278
+	* opts.c (parse_sanitizer_options): For -fsanitize=undefined,
+	restore enabling also SANITIZE_UNREACHABLE and SANITIZE_RETURN.
+
+2016-11-23  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/69183
+	* omp-low.c (build_outer_var_ref): Change lastprivate argument
+	to code, pass it recursively, adjust uses.  For OMP_CLAUSE_PRIVATE
+	on worksharing constructs, treat it like clauses on simd construct.
+	Formatting fix.
+	(lower_rec_input_clauses): For OMP_CLAUSE_PRIVATE_OUTER_REF pass
+	OMP_CLAUSE_PRIVATE as last argument to build_outer_var_ref.
+	(lower_lastprivate_clauses): Pass OMP_CLAUSE_LASTPRIVATE instead
+	of true as last argument to build_outer_var_ref.
+
+2016-11-23  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*movqi_internal): Calculate mode
+	attribute of alternatives 7,8,9 depending on TARGET_AVX512DQ.
+	<TYPE_MSKMOV>: Emit kmovw for MODE_HI insn mode attribute.
+	(*k<logic><mode>): Calculate mode attribute depending on
+	TARGET_AVX512DQ.  Emit k<logic>w for MODE_HI insn mode attribute.
+	(*andqi_1): Calculate mode attribute of alternative 3 depending
+	on TARGET_AVX512DQ.  Emit kandw for MODE_HI insn mode attribute.
+	(kandn<mode>): Calculate mode attribute of alternative 2 depending
+	on TARGET_AVX512DQ.  Emit kandnw for MODE_HI insn mode attribute.
+	(kxnor<mode>): Merge insn patterns using SWI1248_AVX512BW mode
+	iterator.  Calculate mode attribute of alternative 1 depending
+	on TARGET_AVX512DQ.  Emit kxnorw for MODE_HI insn mode attribute.
+	(*one_cmplqi2_1): Calculate mode attribute of alternative 2 depending
+	on TARGET_AVX512DQ.  Emit knotw for MODE_HI insn mode attribute.
+
+2016-11-23  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR middle-end/78153
+	* gimple-fold.c (fold_stmt_1): Handle case for GIMPLE_RETURN.
+	* tree-vrp.c (extract_range_basic): Handle case for
+	CFN_BUILT_IN_STRLEN.
+
+2016-11-23  Jeff Law  <law@redhat.com>
+
+	* config/mcore/mcore.c (emit_new_cond_insn): Fix prototype.
+
+	* config/iq2000/iq2000.c (iq2000_rtx_costs): Avoid multiplication
+	in boolean context warning.
+
+	* config/ia64/ia64.c (ia64_emit_insn_before): Fix prototype.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	PR target/63250
+	* config/arm/arm-builtins.c (arm_simd_floatHF_type_node): Rename to...
+	(arm_fp16_type_node): ...This, make visibile.
+	(arm_simd_builtin_std_type): Rename arm_simd_floatHF_type_node to
+	arm_fp16_type_node.
+	(arm_init_simd_builtin_types): Likewise.
+	(arm_init_fp16_builtins): Likewise.
+	* config/arm/arm.c (arm_excess_precision): New.
+	(arm_floatn_mode): Likewise.
+	(TARGET_C_EXCESS_PRECISION): Likewise.
+	(TARGET_FLOATN_MODE): Likewise.
+	(arm_promoted_type): Only promote arm_fp16_type_node.
+	* config/arm/arm.h (arm_fp16_type_node): Declare.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/arm/arm.c (arm_convert_to_type): Delete.
+	(TARGET_CONVERT_TO_TYPE): Delete.
+	(arm_init_libfuncs): Enable trunc_optab from DFmode to HFmode.
+	(arm_libcall_uses_aapcs_base): Add trunc_optab from DF- to HFmode.
+	* config/arm/arm.h (TARGET_FP16_TO_DOUBLE): New.
+	* config/arm/arm.md (truncdfhf2): Only convert through SFmode if we
+	are in fast math mode, and have no single step hardware instruction.
+	(extendhfdf2): Only expand through SFmode if we don't have a
+	single-step hardware instruction.
+	* config/arm/vfp.md (*truncdfhf2): New.
+	(extendhfdf2): Likewise.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* targhooks.c (default_floatn_mode): Enable _Float16 if a target
+	provides HFmode.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/s390/s390.h (TARGET_FLT_EVAL_METHOD): Delete.
+	* config/m68k/m68k.h (TARGET_FLT_EVAL_METHOD): Delete.
+	* config/i386/i386.h (TARGET_FLT_EVAL_METHOD): Delete.
+	* defaults.h (TARGET_FLT_EVAL_METHOD): Delete.
+	* doc/tm.texi.in (TARGET_FLT_EVAL_METHOD): Delete.
+	* doc/tm.texi: Regenerate.
+	* system.h (TARGET_FLT_EVAL_METHOD): Poison.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* toplev.c (init_excess_precision): Delete most logic.
+	* tree.c (excess_precision_type): Rewrite to use
+	TARGET_EXCESS_PRECISION.
+	* doc/invoke.texi (-fexcess-precision): Document behaviour in a
+	more generic fashion.
+	* ginclude/float.h: Wrap definition of FLT_EVAL_METHOD in
+	__STDC_WANT_IEC_60559_TYPES_EXT__.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* common.opt (fpermitted-flt-eval-methods): New.
+	* doc/invoke.texi (-fpermitted-flt-eval-methods): Document it.
+	* flag_types.h (permitted_flt_eval_methods): New.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/m68k/m68k.c (m68k_excess_precision): New.
+	(TARGET_C_EXCESS_PRECISION): Define.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/s390/s390.c (s390_excess_precision): New.
+	(TARGET_C_EXCESS_PRECISION): Define.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/i386/i386.c (ix86_excess_precision): New.
+	(TARGET_C_EXCESS_PRECISION): Define.
+
+2016-11-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* target.def (excess_precision): New hook.
+	* target.h (flt_eval_method): New.
+	(excess_precision_type): Likewise.
+	* targhooks.c (default_excess_precision): New.
+	* targhooks.h (default_excess_precision): New.
+	* doc/tm.texi.in (TARGET_C_EXCESS_PRECISION): New.
+	* doc/tm.texi: Regenerate.
+
+2016-11-23  Martin Sebor  <msebor@redhat.com>
+
+	PR middle-end/78461
+	* gimple-ssa-sprintf.c (format_string): Correct the maxima and
+	set the minimum number of bytes for an unknown string to zero.
+
+2016-11-23  Martin Jambor  <mjambor@suse.cz>
+	    Martin Liska  <mliska@suse.cz>
+
+	* hsa-builtins.def: New file.
+	* Makefile.in (BUILTINS_DEF): Add hsa-builtins.def dependency.
+	* builtins.def: Include hsa-builtins.def.
+	(DEF_HSA_BUILTIN): New macro.
+	* dumpfile.h (OPTGROUP_OPENMP): Define.
+	* dumpfile.c (optgroup_options): Added OPTGROUP_OPENMP.
+	* gimple.h (gf_mask): Added elements GF_OMP_FOR_GRID_INTRA_GROUP and
+	GF_OMP_FOR_GRID_GROUP_ITER.
+	(gimple_omp_for_grid_phony): Added checking assert.
+	(gimple_omp_for_set_grid_phony): Likewise.
+	(gimple_omp_for_grid_intra_group): New function.
+	(gimple_omp_for_set_grid_intra_group): Likewise.
+	(gimple_omp_for_grid_group_iter): Likewise.
+	(gimple_omp_for_set_grid_group_iter): Likewise.
+	* omp-low.c (check_omp_nesting_restrictions): Allow GRID loop where
+	previosuly only distribute loop was permitted.
+	(lower_lastprivate_clauses): Allow non tcc_comparison predicates.
+	(grid_get_kernel_launch_attributes): Support multiple HSA grid
+	dimensions.
+	(grid_expand_omp_for_loop): Likewise and also support standalone
+	distribute constructs.  New parameter INTRA_GROUP, updated both users.
+	(grid_expand_target_grid_body): Support standalone distribute
+	constructs.
+	(pass_data_expand_omp): Changed optinfo_flags to OPTGROUP_OPENMP.
+	(pass_data_expand_omp_ssa): Likewise.
+	(pass_data_omp_device_lower): Likewsie.
+	(pass_data_lower_omp): Likewise.
+	(pass_data_diagnose_omp_blocks): Likewise.
+	(pass_data_oacc_device_lower): Likewise.
+	(pass_data_omp_target_link): Likewise.
+	(grid_lastprivate_predicate): New function.
+	(lower_omp_for_lastprivate): Call grid_lastprivate_predicate for
+	gridified loops.
+	(lower_omp_for): Support standalone distribute constructs.
+	(grid_prop): New type.
+	(grid_safe_assignment_p): Check for assignments to group_sizes, new
+	parameter GRID.
+	(grid_seq_only_contains_local_assignments): New parameter GRID, pass
+	it to callee.
+	(grid_find_single_omp_among_assignments_1): Likewise, improve missed
+	optimization info messages.
+	(grid_find_single_omp_among_assignments): Likewise.
+	(grid_find_ungridifiable_statement): Do not bail out for SIMDs.
+	(grid_parallel_clauses_gridifiable): New function.
+	(grid_inner_loop_gridifiable_p): Likewise.
+	(grid_dist_follows_simple_pattern): Likewise.
+	(grid_gfor_follows_tiling_pattern): Likewise.
+	(grid_call_permissible_in_distribute_p): Likewise.
+	(grid_handle_call_in_distribute): Likewise.
+	(grid_dist_follows_tiling_pattern): Likewise.
+	(grid_target_follows_gridifiable_pattern): Support standalone
+	distribute constructs.
+	(grid_var_segment): New enum.
+	(grid_mark_variable_segment): New function.
+	(grid_copy_leading_local_assignments): Call grid_mark_variable_segment
+	if a new argument says so.
+	(grid_process_grid_body): New function.
+	(grid_eliminate_combined_simd_part): Likewise.
+	(grid_mark_tiling_loops): Likewise.
+	(grid_mark_tiling_parallels_and_loops): Likewise.
+	(grid_process_kernel_body_copy): Support standalone distribute
+	constructs.
+	(grid_attempt_target_gridification): New grid variable holding overall
+	gridification state.  Support standalone distribute constructs and
+	collapse clauses.
+	* doc/optinfo.texi (Optimization groups): Document OPTGROUP_OPENMP.
+	* hsa.h (hsa_bb): Add method method append_phi.
+	(hsa_insn_br): Renamed to hsa_insn_cbr, renamed all
+	occurences in all files too.
+	(hsa_insn_br): New class, now the ancestor of hsa_incn_cbr.
+	(is_a_helper <hsa_insn_br *>::test): New function.
+	(is_a_helper <hsa_insn_cbr *>::test): Adjust to only cover conditional
+	branch instructions.
+	(hsa_insn_signal): Make a direct descendant of
+	hsa_insn_basic.  Add memorder constructor parameter and
+	m_memory_order and m_signalop member variables.
+	(hsa_insn_queue): Changed constructor parameters to common form.
+	Added m_segment and m_memory_order member variables.
+	(hsa_summary_t): Add private member function
+	process_gpu_implementation_attributes.
+	(hsa_function_summary): Rename m_binded_function to
+	m_bound_function.
+	(hsa_insn_basic_p): Remove typedef.
+	(hsa_op_with_type): Change hsa_insn_basic_p into plain pointers.
+	(hsa_op_reg_p): Remove typedef.
+	(hsa_function_representation): Change hsa_op_reg_p into plain
+	pointers.
+	(hsa_insn_phi): Removed new and delete operators.
+	(hsa_insn_br): Likewise.
+	(hsa_insn_cbr): Likewise.
+	(hsa_insn_sbr): Likewise.
+	(hsa_insn_cmp): Likewise.
+	(hsa_insn_mem): Likewise.
+	(hsa_insn_atomic): Likewise.
+	(hsa_insn_signal): Likewise.
+	(hsa_insn_seg): Likewise.
+	(hsa_insn_call): Likewise.
+	(hsa_insn_arg_block): Likewise.
+	(hsa_insn_comment): Likewise.
+	(hsa_insn_srctype): Likewise.
+	(hsa_insn_packed): Likewise.
+	(hsa_insn_cvt): Likewise.
+	(hsa_insn_alloca): Likewise.
+	* hsa.c (hsa_destroy_insn): Also handle instances of hsa_insn_br.
+	(process_gpu_implementation_attributes): New function.
+	(link_functions): Move some functionality into it.  Adjust after
+	renaming m_binded_functions to m_bound_functions.
+	(hsa_insn_basic::op_output_p): Add BRIG_OPCODE_DEBUGTRAP
+	to the list of instructions with no output registers.
+	(get_in_type): Return this if it is a register of
+	matching size.
+	(hsa_get_declaration_name): Moved to...
+	* hsa-gen.c (hsa_get_declaration_name): ...here.  Allocate
+	temporary string on an obstack instead from ggc.
+	(query_hsa_grid): Renamed to query_hsa_grid_dim, reimplemented, cut
+	down to two overloads.
+	(hsa_allocp_operand_address): Removed.
+	(hsa_allocp_operand_immed): Likewise.
+	(hsa_allocp_operand_reg): Likewise.
+	(hsa_allocp_operand_code_list): Likewise.
+	(hsa_allocp_operand_operand_list): Likewise.
+	(hsa_allocp_inst_basic): Likewise.
+	(hsa_allocp_inst_phi): Likewise.
+	(hsa_allocp_inst_mem): Likewise.
+	(hsa_allocp_inst_atomic): Likewise.
+	(hsa_allocp_inst_signal): Likewise.
+	(hsa_allocp_inst_seg): Likewise.
+	(hsa_allocp_inst_cmp): Likewise.
+	(hsa_allocp_inst_br): Likewise.
+	(hsa_allocp_inst_sbr): Likewise.
+	(hsa_allocp_inst_call): Likewise.
+	(hsa_allocp_inst_arg_block): Likewise.
+	(hsa_allocp_inst_comment): Likewise.
+	(hsa_allocp_inst_queue): Likewise.
+	(hsa_allocp_inst_srctype): Likewise.
+	(hsa_allocp_inst_packed): Likewise.
+	(hsa_allocp_inst_cvt): Likewise.
+	(hsa_allocp_inst_alloca): Likewise.
+	(hsa_allocp_bb): Likewise.
+	(hsa_obstack): New.
+	(hsa_init_data_for_cfun): Initialize obstack.
+	(hsa_deinit_data_for_cfun): Release memory of the obstack.
+	(hsa_op_immed::operator new): Use obstack instead of object_allocator.
+	(hsa_op_reg::operator new): Likewise.
+	(hsa_op_address::operator new): Likewise.
+	(hsa_op_code_list::operator new): Likewise.
+	(hsa_op_operand_list::operator new): Likewise.
+	(hsa_insn_basic::operator new): Likewise.
+	(hsa_insn_phi::operator new): Likewise.
+	(hsa_insn_br::operator new): Likewise.
+	(hsa_insn_sbr::operator new): Likewise.
+	(hsa_insn_cmp::operator new): Likewise.
+	(hsa_insn_mem::operator new): Likewise.
+	(hsa_insn_atomic::operator new): Likewise.
+	(hsa_insn_signal::operator new): Likewise.
+	(hsa_insn_seg::operator new): Likewise.
+	(hsa_insn_call::operator new): Likewise.
+	(hsa_insn_arg_block::operator new): Likewise.
+	(hsa_insn_comment::operator new): Likewise.
+	(hsa_insn_srctype::operator new): Likewise.
+	(hsa_insn_packed::operator new): Likewise.
+	(hsa_insn_cvt::operator new): Likewise.
+	(hsa_insn_alloca::operator new): Likewise.
+	(hsa_init_new_bb): Likewise.
+	(hsa_bb::append_phi): New function.
+	(gen_hsa_phi_from_gimple_phi): Use it.
+	(get_symbol_for_decl): Fix dinstinguishing between
+	global and local functions.  Put local variables into a segment
+	according to their attribute or static flag, if there is one.
+	(hsa_insn_br::hsa_insn_br): New.
+	(hsa_insn_br::operator new): Likewise.
+	(hsa_insn_cbr::hsa_insn_cbr): Set width via ancestor constructor.
+	(query_hsa_grid_nodim): New function.
+	(multiply_grid_dim_characteristics): Likewise.
+	(gen_get_num_threads): Likewise.
+	(gen_get_num_teams): Reimplemented.
+	(gen_get_team_num): Likewise.
+	(gen_hsa_insns_for_known_library_call): Updated calls to the above
+	helper functions.
+	(get_memory_order_name): Removed.
+	(get_memory_order): Likewise.
+	(hsa_memorder_from_tree): New function.
+	(gen_hsa_ternary_atomic_for_builtin): Renamed to
+	gen_hsa_atomic_for_builtin, can also create signals.
+	(gen_hsa_insns_for_call): Handle many new builtins.  Adjust to use
+	hsa_memory_order_from_tree and gen_hsa_atomic_for_builtin.
+	(hsa_insn_atomic): Fix function comment.
+	(hsa_insn_signal::hsa_insn_signal): Fix comment.  Update call to
+	ancestor constructor and initialization of new member variables.
+	(hsa_insn_queue::hsa_insn_queue): Added initialization of new
+	member variables.
+	(hsa_get_host_function): Handle functions with no bound CPU
+	implementation.  Fix binded to bound.
+	(get_brig_function_name): Likewise.
+	(HSA_SORRY_ATV): Remove semicolon after macro.
+	(HSA_SORRY_AT): Likewise.
+	(omp_simple_builtin::generate): Add missing semicolons.
+	(hsa_insn_phi::operator new): Removed.
+	(hsa_insn_br::operator new): Likewise.
+	(hsa_insn_cbr::operator new): Likewise.
+	(hsa_insn_sbr::operator new): Likewise.
+	(hsa_insn_cmp::operator new): Likewise.
+	(hsa_insn_mem::operator new): Likewise.
+	(hsa_insn_atomic::operator new): Likewise.
+	(hsa_insn_signal::operator new): Likewise.
+	(hsa_insn_seg::operator new): Likewise.
+	(hsa_insn_call::operator new): Likewise.
+	(hsa_insn_arg_block::operator new): Likewise.
+	(hsa_insn_comment::operator new): Likewise.
+	(hsa_insn_srctype::operator new): Likewise.
+	(hsa_insn_packed::operator new): Likewise.
+	(hsa_insn_cvt::operator new): Likewise.
+	(hsa_insn_alloca::operator new): Likewise.
+	(get_symbol_for_decl): Accept CONST_DECLs, put them to
+	readonly segment.
+	(gen_hsa_addr): Also process CONST_DECLs.
+	(gen_hsa_addr_insns): Process CONST_DECLs by creating private
+	copies.
+	(gen_hsa_unary_operation): Make sure the function does
+	not use bittype source type for firstbit and lastbit operations.
+	(gen_hsa_popcount_to_dest): Make sure the function uses a bittype
+	source type.
+	* hsa-brig.c (emit_insn_operands): Cope with zero operands in an
+	instruction.
+	(emit_branch_insn): Renamed to emit_cond_branch_insn.
+	Emit the width stored in the class.
+	(emit_generic_branch_insn): New function.
+	(emit_insn): Call emit_generic_branch_insn.
+	(emit_signal_insn): Remove obsolete comment.  Update
+	member variable name, pick a type according to profile.
+	(emit_alloca_insn): Remove obsolete comment.
+	(emit_atomic_insn): Likewise.
+	(emit_queue_insn): Get segment and memory order from the IR object.
+	(hsa_brig_section): Make allocate_new_chunk, chunks
+	and cur_chunk provate, add a default NULL parameter to add method.
+	(hsa_brig_section::add): Added a new parameter, store pointer to
+	output data there if it is non-NULL.
+	(emit_function_directives): Use this new parameter instead of
+	calculating the pointer itself, fix function comment.
+	(hsa_brig_emit_function): Add forgotten endian conversion.
+	(hsa_output_kernels): Remove unnecessary building of
+	kernel_dependencies_vector_type.
+	(emit_immediate_operand): Declare.
+	(emit_directive_variable): Also emit initializers of CONST_DECLs.
+	(gen_hsa_insn_for_internal_fn_call): Also handle IFN_RSQRT.
+	(verify_function_arguments): Properly detect variadic
+	arguments.
+	* hsa-dump.c (hsa_width_specifier_name): New function.
+	(dump_hsa_insn_1): Dump generic branch instructions, update signal
+	member variable name.  Special dumping for queue objects.
+	* ipa-hsa.c (process_hsa_functions): Adjust after renaming
+	m_binded_functions to m_bound_functions.  Copy externally visible flag
+	to the node.
+	(ipa_hsa_write_summary): Likewise.
+	(ipa_hsa_read_section): Likewise.
+
+2016-11-23  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78396
+	* tree-vectorizer.c (vectorize_loops): If an innermost loop didn't
+	vectorize try vectorizing an if-converted body using BB vectorization.
+
+2016-11-23  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* rtlanal.c (subreg_get_info): Use more local variables.
+	Remark that for HARD_REGNO_NREGS_HAS_PADDING, each scalar unit
+	occupies at least one register.  Assume that full hard registers
+	have consistent endianness.  Share previously-duplicated if block.
+	Rework the main handling so that it operates on independently-
+	addressable YMODE-sized blocks.  Use subreg_size_lowpart_offset
+	to check lowpart offsets, without trying to find an equivalent
+	integer mode first.  Handle WORDS_BIG_ENDIAN != REG_WORDS_BIG_ENDIAN
+	as a final register-endianness correction.
+
+2016-11-23  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/77881
+	PR bootstrap/78390
+	PR target/78438
+	PR bootstrap/78477
+	* combine.c (make_compound_operation_int): Do not convert a subreg of
+	a non-constant logical shift right to a zero_extract.  Handle the case
+	where some zero bits have been shifted into the range covered by that
+	subreg.
+
+2016-11-23  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* rtl.h (subreg_size_offset_from_lsb): Declare.
+	(subreg_offset_from_lsb): New function.
+	(subreg_size_lowpart_offset): Declare.
+	(subreg_lowpart_offset): Turn into an inline function.
+	(subreg_size_highpart_offset): Declare.
+	(subreg_highpart_offset): Turn into an inline function.
+	* emit-rtl.c (subreg_size_lowpart_offset): New function.
+	(subreg_size_highpart_offset): Likewise
+	* rtlanal.c (subreg_size_offset_from_lsb): Likewise.
+
+2016-11-23  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78482
+	* tree-cfgcleanup.c: Include tree-ssa-loop-niter.h.
+	(remove_forwarder_block_with_phi): When merging with a loop
+	header creates a new latch reset number of iteration information
+	of the loop.
+
+2016-11-23  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc.md (*ashrsi3_extend): Rename to...
+	(*ashrsi3_extend0): ...this.  Accept constant integers.
+	(*ashrsi3_extend2): Rename to...
+	(*ashrsi3_extend1): ...this.
+	(*ashrsi3_extend2): New pattern.
+	(*lshrsi3_extend1): Accept constant integers.
+	(*lshrsi3_extend2): Fix condition on operand 2.
+
+2016-11-23  Martin Liska  <mliska@suse.cz>
+
+	* config/i386/i386.c: Initialize function pointer to NULL.
+
+2016-11-23  Bin Cheng  <bin.cheng@arm.com>
+
+	* fold-const.c (fold_cond_expr_with_comparison): Move simplification
+	for A == C1 ? A : C2 to below.
+	* match.pd: Move from above to here:
+	(cond (eq (convert1? x) c1) (convert2? x) c2)
+	  -> (cond (eq x c1) c1 c2).
+
+2016-11-23  Bin Cheng  <bin.cheng@arm.com>
+
+	* fold-const.c (fold_cond_expr_with_comparison): Move simplification
+	for A cmp C1 ? A : C2 to below, also simplify remaining code.
+	* match.pd: Move and extend simplification from above to here:
+	(cond (cmp (convert1? x) c1) (convert2? x) c2) -> (minmax (x c)).
+	* tree-if-conv.c (ifcvt_follow_ssa_use_edges): New func.
+	(predicate_scalar_phi): Call fold_stmt using the new valueize func.
+
+2016-11-23  Martin Liska  <mliska@suse.cz>
+	    Martin Jambor  <mjambor@suse.cz>
+
+	* doc/install.texi: Remove entry about --with-hsa-kmt-lib.
+
+2016-11-23  Aldy Hernandez  <aldyh@redhat.com>
+
+	PR target/78213
+	* opts.c (finish_options): Set -fsyntax-only if running self tests.
+
+2016-11-23  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/71762
+	* match.pd ((~X & Y) -> X < Y, (X & ~Y) -> Y < X,
+	(~X | Y) -> X <= Y, (X | ~Y) -> Y <= X): Remove.
+
+2016-11-23  Richard Biener  <rguenther@suse.de>
+
+	PR lto/78472
+	* tree.c (gimple_canonical_types_compatible_p): Ignore zero-sized
+	fields.
+
+2016-11-23  Richard Biener  <rguenther@suse.de>
+	    Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.rog>
+
+	PR tree-optimization/78154
+	* tree-vrp.c (gimple_stmt_nonzero_warnv_p): Return true if function
+	returns it's argument and the argument is nonnull.
+	* builtin-attrs.def: Define ATTR_RETURNS_NONNULL,
+	ATT_RETNONNULL_NOTHROW_LEAF.
+	* builtins.def (BUILT_IN_MEMPCPY): Change attribute to
+	ATTR_RETNONNULL_NOTHROW_LEAF.
+	(BUILT_IN_STPCPY): Likewise.
+	(BUILT_IN_STPNCPY): Likewise.
+	(BUILT_IN_MEMPCPY_CHK): Likewise.
+	(BUILT_IN_STPCPY_CHK): Likewise.
+	(BUILT_IN_STPNCPY_CHK): Likewise.
+	(BUILT_IN_STRCAT): Change attribute to ATTR_RET1_NOTHROW_NONNULL_LEAF.
+	(BUILT_IN_STRNCAT): Likewise.
+	(BUILT_IN_STRNCPY): Likewise.
+	(BUILT_IN_MEMSET_CHK): Likewise.
+	(BUILT_IN_STRCAT_CHK): Likewise.
+	(BUILT_IN_STRCPY_CHK): Likewise.
+	(BUILT_IN_STRNCAT_CHK): Likewise.
+	(BUILT_IN_STRNCPY_CHK): Likewise.
+
+2016-11-23  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
+
+	* fold-const.c (tree_expr_nonzero_p) : Make non-static.
+	* fold-const.h (tree_expr_nonzero_p) : Declare.
+	* match.pd (cmp (mult:c @0 @1) (mult:c @2 @1) : New Pattern.
+
+2016-11-23  Paolo Bonzini  <bonzini@gnu.org>
+
+	* system.h (HAVE_DESIGNATED_INITIALIZERS,
+	HAVE_DESIGNATED_UNION_INITIALIZERS): Do not use
+	"defined" in macros.
+	* doc/cpp.texi (Defined): Mention -Wexpansion-to-defined.
+	* doc/cppopts.texi (Invocation): Document -Wexpansion-to-defined.
+	* doc/invoke.texi (Warning Options): Document -Wexpansion-to-defined.
+
+2016-11-23  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/60300
+	* config/avr/constraints.md (Csp): Widen range to [-11..6].
+	* config/avr/avr.c (avr_prologue_setup_frame): Limit number
+	of RCALLs in prologue to 3.
+
+2016-11-22  Michael Collison  <michael.collison@arm.com>
+
+	* config/aarch64/aarch64-protos.h
+	(aarch64_and_split_imm1, aarch64_and_split_imm2)
+	(aarch64_and_bitmask_imm): New prototypes
+	* config/aarch64/aarch64.c (aarch64_and_split_imm1):
+	New overloaded function to create bit mask covering the
+	lowest to highest bits set.
+	(aarch64_and_split_imm2): New overloaded functions to create bit
+	mask of zeros between first and last bit set.
+	(aarch64_and_bitmask_imm): New function to determine if a integer
+	is a valid two instruction "and" operation.
+	* config/aarch64/aarch64.md:(and<mode>3): New define_insn and _split
+	allowing wider range of constants with "and" operations.
+	* (ior<mode>3, xor<mode>3): Use new LOGICAL2 iterator to prevent
+	"and" operator from matching restricted constant range used for
+	ior and xor operators.
+	* config/aarch64/constraints.md (UsO constraint): New SImode constraint
+	for constants in "and" operantions.
+	(UsP constraint): New DImode constraint for constants
+	in "and" operations.
+	* config/aarch64/iterators.md (lconst2): New mode iterator.
+	(LOGICAL2): New code iterator.
+	* config/aarch64/predicates.md (aarch64_logical_and_immediate): New
+	predicate.
+	(aarch64_logical_and_operand): New predicate allowing extended
+	constants for "and" operations.
+
+2016-11-22  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/tilegx.md (trap): New pattern.
+	* config/tilepro/tilepro.md (trap): Likewise.
+
+2016-11-22  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/tilegx.md (*zero_extract): Use
+	define_insn_and_split instead of define_insn; Handle pos + size >
+	64.
+	(*sign_extract): Likewise.
+
+2016-11-22  Marek Polacek  <polacek@redhat.com>
+
+	PR tree-optimization/78455
+	* tree-ssa-uninit.c (can_chain_union_be_invalidated_p): Fix typo.
+
+2016-11-22  Ian Lance Taylor  <iant@golang.org>
+
+	PR go/78431
+	PR go/78432
+	* godump.c (go_format_type): Always pass alignment as 1 when
+	calling go_append_padding at end of struct/union.
+
+2016-11-22  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/78451
+	* config/i386/avx512bwintrin.h (_mm512_setzero_qi,
+	_mm512_setzero_hi): Removed.
+	(_mm512_maskz_mov_epi16, _mm512_maskz_loadu_epi16,
+	_mm512_maskz_mov_epi8, _mm512_maskz_loadu_epi8,
+	_mm512_maskz_broadcastb_epi8, _mm512_maskz_set1_epi8,
+	_mm512_maskz_broadcastw_epi16, _mm512_maskz_set1_epi16,
+	_mm512_mulhrs_epi16, _mm512_maskz_mulhrs_epi16, _mm512_mulhi_epi16,
+	_mm512_maskz_mulhi_epi16, _mm512_mulhi_epu16,
+	_mm512_maskz_mulhi_epu16, _mm512_maskz_mullo_epi16,
+	_mm512_cvtepi8_epi16, _mm512_maskz_cvtepi8_epi16, _mm512_cvtepu8_epi16,
+	_mm512_maskz_cvtepu8_epi16, _mm512_permutexvar_epi16,
+	_mm512_maskz_permutexvar_epi16, _mm512_avg_epu8, _mm512_maskz_avg_epu8,
+	_mm512_maskz_add_epi8, _mm512_maskz_sub_epi8, _mm512_avg_epu16,
+	_mm512_maskz_avg_epu16, _mm512_subs_epi8, _mm512_maskz_subs_epi8,
+	_mm512_subs_epu8, _mm512_maskz_subs_epu8, _mm512_adds_epi8,
+	_mm512_maskz_adds_epi8, _mm512_adds_epu8, _mm512_maskz_adds_epu8,
+	_mm512_maskz_sub_epi16, _mm512_subs_epi16, _mm512_maskz_subs_epi16,
+	_mm512_subs_epu16, _mm512_maskz_subs_epu16, _mm512_maskz_add_epi16,
+	_mm512_adds_epi16, _mm512_maskz_adds_epi16, _mm512_adds_epu16,
+	_mm512_maskz_adds_epu16, _mm512_srl_epi16, _mm512_maskz_srl_epi16,
+	_mm512_packs_epi16, _mm512_sll_epi16, _mm512_maskz_sll_epi16,
+	_mm512_maddubs_epi16, _mm512_maskz_maddubs_epi16, _mm512_unpackhi_epi8,
+	_mm512_maskz_unpackhi_epi8, _mm512_unpackhi_epi16,
+	_mm512_maskz_unpackhi_epi16, _mm512_unpacklo_epi8,
+	_mm512_maskz_unpacklo_epi8, _mm512_unpacklo_epi16,
+	_mm512_maskz_unpacklo_epi16, _mm512_shuffle_epi8,
+	_mm512_maskz_shuffle_epi8, _mm512_min_epu16, _mm512_maskz_min_epu16,
+	_mm512_min_epi16, _mm512_maskz_min_epi16, _mm512_max_epu8,
+	_mm512_maskz_max_epu8, _mm512_max_epi8, _mm512_maskz_max_epi8,
+	_mm512_min_epu8, _mm512_maskz_min_epu8, _mm512_min_epi8,
+	_mm512_maskz_min_epi8, _mm512_max_epi16, _mm512_maskz_max_epi16,
+	_mm512_max_epu16, _mm512_maskz_max_epu16, _mm512_sra_epi16,
+	_mm512_maskz_sra_epi16, _mm512_srav_epi16, _mm512_maskz_srav_epi16,
+	_mm512_srlv_epi16, _mm512_maskz_srlv_epi16, _mm512_sllv_epi16,
+	_mm512_maskz_sllv_epi16, _mm512_maskz_packs_epi16, _mm512_packus_epi16,
+	_mm512_maskz_packus_epi16, _mm512_abs_epi8, _mm512_maskz_abs_epi8,
+	_mm512_abs_epi16, _mm512_maskz_abs_epi16, _mm512_dbsad_epu8,
+	_mm512_maskz_dbsad_epu8, _mm512_srli_epi16, _mm512_maskz_srli_epi16,
+	_mm512_slli_epi16, _mm512_maskz_slli_epi16, _mm512_shufflehi_epi16,
+	_mm512_maskz_shufflehi_epi16, _mm512_shufflelo_epi16,
+	_mm512_maskz_shufflelo_epi16, _mm512_srai_epi16,
+	_mm512_maskz_srai_epi16, _mm512_packs_epi32,
+	_mm512_maskz_packs_epi32, _mm512_packus_epi32,
+	_mm512_maskz_packus_epi32): Use _mm512_setzero_si512 instead of
+	_mm512_setzero_qi or _mm512_setzero_hi.
+	(_mm512_maskz_alignr_epi8, _mm512_dbsad_epu8,
+	_mm512_maskz_dbsad_epu8): Formatting fixes.
+	(_mm512_srli_epi16, _mm512_maskz_srli_epi16, _mm512_slli_epi16,
+	_mm512_maskz_slli_epi16, _mm512_shufflehi_epi16,
+	_mm512_maskz_shufflehi_epi16, _mm512_shufflelo_epi16,
+	_mm512_maskz_shufflelo_epi16, _mm512_srai_epi16,
+	_mm512_maskz_srai_epi16): Use _mm512_setzero_si512 instead of
+	_mm512_setzero_qi or _mm512_setzero_hi.
+
+2016-11-22  Nathan Sidwell  <nathan@acm.org>
+
+	* gcc-ar.c (main): Fix indentation.
+	* gcov-io.c (gcov_write_summary): Remove extraneous {...}
+	* ggc-page.c (move_ptes_to_front): Fix formatting.
+	* hsa-dump.c (dump_has_cfun): Fix indentation.
+	* sel-sched-ir.h: Remove trailing blank lines.
+
+2016-11-22  Jakub Jelinek  <jakub@redhat.com>
+	    Alexander Monakov  <amonakov@ispras.ru>
+
+	* internal-fn.c (expand_GOMP_USE_SIMT): New function.
+	* tree.c (omp_clause_num_ops): OMP_CLAUSE__SIMT_ has 0 operands.
+	(omp_clause_code_name): Add _simt_ name.
+	(walk_tree_1): Handle OMP_CLAUSE__SIMT_.
+	* tree-core.h (enum omp_clause_code): Add OMP_CLAUSE__SIMT_.
+	* omp-low.c (scan_sharing_clauses): Handle OMP_CLAUSE__SIMT_.
+	(scan_omp_simd): New function.
+	(scan_omp_1_stmt): Use it in target regions if needed.
+	(omp_max_vf): Don't max with omp_max_simt_vf.
+	(lower_rec_simd_input_clauses): Use omp_max_simt_vf if
+	OMP_CLAUSE__SIMT_ is present.
+	(lower_rec_input_clauses): Compute maybe_simt from presence of
+	OMP_CLAUSE__SIMT_.
+	(lower_lastprivate_clauses): Likewise.
+	(expand_omp_simd): Likewise.  Remove explicit offloaded region check.
+	(execute_omp_device_lower): Lower IFN_GOMP_USE_SIMT.
+	* internal-fn.def (GOMP_USE_SIMT): New internal function.
+	* tree-pretty-print.c (dump_omp_clause): Handle OMP_CLAUSE__SIMT_.
+
+2016-11-22  Alexander Monakov  <amonakov@ispras.ru>
+
+	* internal-fn.c (expand_GOMP_SIMT_LANE): New.
+	(expand_GOMP_SIMT_VF): New.
+	(expand_GOMP_SIMT_LAST_LANE): New.
+	(expand_GOMP_SIMT_ORDERED_PRED): New.
+	(expand_GOMP_SIMT_VOTE_ANY): New.
+	(expand_GOMP_SIMT_XCHG_BFLY): New.
+	(expand_GOMP_SIMT_XCHG_IDX): New.
+	* internal-fn.def (GOMP_SIMT_LANE): New.
+	(GOMP_SIMT_VF): New.
+	(GOMP_SIMT_LAST_LANE): New.
+	(GOMP_SIMT_ORDERED_PRED): New.
+	(GOMP_SIMT_VOTE_ANY): New.
+	(GOMP_SIMT_XCHG_BFLY): New.
+	(GOMP_SIMT_XCHG_IDX): New.
+	* omp-low.c (omp_maybe_offloaded_ctx): New, outlined from...
+	(create_omp_child_function): ...here.  Set "omp target entrypoint"
+	or "omp declare target" attribute based on is_gimple_omp_offloaded.
+	(omp_max_simt_vf): New.  Use it...
+	(omp_max_vf): ...here.
+	(lower_rec_input_clauses): Add reduction lowering for SIMT execution.
+	(lower_lastprivate_clauses): Likewise, for "lastprivate" lowering.
+	(lower_omp_ordered): Likewise, for "ordered" lowering.
+	(expand_omp_simd): Add SIMT transforms.
+	(pass_data_lower_omp): Add PROP_gimple_lomp_dev.
+	(execute_omp_device_lower): New.
+	(pass_data_omp_device_lower): New.
+	(pass_omp_device_lower): New pass.
+	(make_pass_omp_device_lower): New.
+	* passes.def (pass_omp_device_lower): Position new pass.
+	* tree-pass.h (PROP_gimple_lomp_dev): Define.
+	(make_pass_omp_device_lower): Declare.
+
+2016-11-22  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/78451
+	* config/i386/avx512vlintrin.h (_mm_setzero_di): Removed.
+	(_mm_maskz_mov_epi64): Use _mm_setzero_si128 instead of
+	_mm_setzero_di.
+	(_mm_maskz_load_epi64): Likewise.
+	(_mm_setzero_hi): Removed.
+	(_mm_maskz_loadu_epi64): Use _mm_setzero_si128 instead of
+	_mm_setzero_di.
+	(_mm_abs_epi64, _mm_maskz_abs_epi64, _mm_maskz_srl_epi64,
+	_mm_maskz_unpackhi_epi64, _mm_maskz_unpacklo_epi64,
+	_mm_maskz_compress_epi64, _mm_srav_epi64, _mm_maskz_srav_epi64,
+	_mm_maskz_sllv_epi64, _mm_maskz_srlv_epi64, _mm_rolv_epi64,
+	_mm_maskz_rolv_epi64, _mm_rorv_epi64, _mm_maskz_rorv_epi64,
+	_mm_min_epi64, _mm_max_epi64, _mm_max_epu64, _mm_min_epu64,
+	_mm_lzcnt_epi64, _mm_maskz_lzcnt_epi64, _mm_conflict_epi64,
+	_mm_maskz_conflict_epi64, _mm_sra_epi64, _mm_maskz_sra_epi64,
+	_mm_maskz_sll_epi64, _mm_rol_epi64, _mm_maskz_rol_epi64,
+	_mm_ror_epi64, _mm_maskz_ror_epi64, _mm_alignr_epi64,
+	_mm_maskz_alignr_epi64, _mm_srai_epi64, _mm_maskz_slli_epi64):
+	Likewise.
+	(_mm_cvtepi32_epi8, _mm256_cvtepi32_epi8, _mm_cvtsepi32_epi8,
+	_mm256_cvtsepi32_epi8, _mm_cvtusepi32_epi8, _mm256_cvtusepi32_epi8,
+	_mm_cvtepi32_epi16, _mm256_cvtepi32_epi16, _mm_cvtsepi32_epi16,
+	_mm256_cvtsepi32_epi16, _mm_cvtusepi32_epi16, _mm256_cvtusepi32_epi16,
+	_mm_cvtepi64_epi8, _mm256_cvtepi64_epi8, _mm_cvtsepi64_epi8,
+	_mm256_cvtsepi64_epi8, _mm_cvtusepi64_epi8, _mm256_cvtusepi64_epi8,
+	_mm_cvtepi64_epi16, _mm256_cvtepi64_epi16, _mm_cvtsepi64_epi16,
+	_mm256_cvtsepi64_epi16, _mm_cvtusepi64_epi16, _mm256_cvtusepi64_epi16,
+	_mm_cvtepi64_epi32, _mm256_cvtepi64_epi32, _mm_cvtsepi64_epi32,
+	_mm256_cvtsepi64_epi32, _mm_cvtusepi64_epi32, _mm256_cvtusepi64_epi32,
+	_mm_maskz_set1_epi32, _mm_maskz_set1_epi64): Formatting fixes.
+	(_mm_maskz_cvtps_ph, _mm256_maskz_cvtps_ph): Use _mm_setzero_si128
+	instead of _mm_setzero_hi.
+	(_mm256_permutex_pd, _mm256_maskz_permutex_epi64, _mm256_insertf32x4,
+	_mm256_maskz_insertf32x4, _mm256_inserti32x4, _mm256_maskz_inserti32x4,
+	_mm256_extractf32x4_ps, _mm256_maskz_extractf32x4_ps,
+	_mm256_shuffle_i32x4, _mm256_maskz_shuffle_i32x4, _mm256_shuffle_f64x2,
+	_mm256_maskz_shuffle_f64x2, _mm256_shuffle_f32x4,
+	_mm256_maskz_shuffle_f32x4, _mm256_maskz_shuffle_pd,
+	_mm_maskz_shuffle_pd, _mm256_maskz_shuffle_ps, _mm_maskz_shuffle_ps,
+	_mm256_maskz_srli_epi32, _mm_maskz_srli_epi32, _mm_maskz_srli_epi64,
+	_mm256_mask_slli_epi32, _mm256_maskz_slli_epi32, _mm256_mask_slli_epi64,
+	_mm256_maskz_slli_epi64, _mm256_roundscale_ps,
+	_mm256_maskz_roundscale_ps, _mm256_roundscale_pd,
+	_mm256_maskz_roundscale_pd, _mm_roundscale_ps, _mm_maskz_roundscale_ps,
+	_mm_roundscale_pd, _mm_maskz_roundscale_pd, _mm256_getmant_ps,
+	_mm256_maskz_getmant_ps, _mm_getmant_ps, _mm_maskz_getmant_ps,
+	_mm256_getmant_pd, _mm256_maskz_getmant_pd, _mm_getmant_pd,
+	_mm_maskz_getmant_pd, _mm256_maskz_shuffle_epi32,
+	_mm_maskz_shuffle_epi32, _mm256_rol_epi32, _mm256_maskz_rol_epi32,
+	_mm_rol_epi32, _mm_maskz_rol_epi32, _mm256_ror_epi32,
+	_mm256_maskz_ror_epi32, _mm_ror_epi32, _mm_maskz_ror_epi32,
+	_mm_maskz_alignr_epi32, _mm_maskz_alignr_epi64,
+	_mm256_maskz_srai_epi32, _mm_maskz_srai_epi32, _mm_srai_epi64,
+	_mm_maskz_srai_epi64, _mm256_maskz_permutex_pd,
+	_mm256_maskz_permute_pd, _mm256_maskz_permute_ps, _mm_maskz_permute_pd,
+	_mm_maskz_permute_ps, _mm256_permutexvar_ps): Formatting fixes.
+	(_mm_maskz_slli_epi64, _mm_rol_epi64, _mm_maskz_rol_epi64,
+	_mm_ror_epi64, _mm_maskz_ror_epi64): Use _mm_setzero_si128 instead of
+	_mm_setzero_di.
+	(_mm_maskz_cvtps_ph, _mm256_maskz_cvtps_ph): Use _mm_setzero_si128
+	instead of _mm_setzero_hi.
+	* config/i386/avx512dqintrin.h (_mm512_broadcast_f64x2,
+	_mm512_broadcast_i64x2, _mm512_broadcast_f32x2, _mm512_broadcast_i32x2,
+	_mm512_broadcast_f32x8, _mm512_broadcast_i32x8): Formatting fixes.
+	(_mm512_extracti64x2_epi64, _mm512_maskz_extracti64x2_epi64): Use
+	_mm_setzero_si128 instead of _mm_setzero_di.
+	(_mm512_cvtt_roundpd_epi64, _mm512_mask_cvtt_roundpd_epi64,
+	_mm512_maskz_cvtt_roundpd_epi64, _mm512_cvtt_roundpd_epu64,
+	_mm512_mask_cvtt_roundpd_epu64, _mm512_maskz_cvtt_roundpd_epu64,
+	_mm512_cvtt_roundps_epi64, _mm512_mask_cvtt_roundps_epi64,
+	_mm512_maskz_cvtt_roundps_epi64, _mm512_cvtt_roundps_epu64,
+	_mm512_mask_cvtt_roundps_epu64, _mm512_maskz_cvtt_roundps_epu64,
+	_mm512_cvt_roundpd_epi64, _mm512_mask_cvt_roundpd_epi64,
+	_mm512_maskz_cvt_roundpd_epi64, _mm512_cvt_roundpd_epu64,
+	_mm512_mask_cvt_roundpd_epu64, _mm512_maskz_cvt_roundpd_epu64,
+	_mm512_cvt_roundps_epi64, _mm512_mask_cvt_roundps_epi64,
+	_mm512_maskz_cvt_roundps_epi64, _mm512_cvt_roundps_epu64,
+	_mm512_mask_cvt_roundps_epu64, _mm512_maskz_cvt_roundps_epu64,
+	_mm512_cvt_roundepi64_ps, _mm512_mask_cvt_roundepi64_ps,
+	_mm512_maskz_cvt_roundepi64_ps, _mm512_cvt_roundepu64_ps,
+	_mm512_mask_cvt_roundepu64_ps, _mm512_maskz_cvt_roundepu64_ps,
+	_mm512_cvt_roundepi64_pd, _mm512_mask_cvt_roundepi64_pd,
+	_mm512_maskz_cvt_roundepi64_pd, _mm512_cvt_roundepu64_pd,
+	_mm512_mask_cvt_roundepu64_pd, _mm512_maskz_cvt_roundepu64_pd,
+	_mm512_reduce_pd, _mm512_maskz_reduce_pd, _mm512_reduce_ps,
+	_mm512_maskz_reduce_ps, _mm512_extractf32x8_ps,
+	_mm512_maskz_extractf32x8_ps, _mm512_extractf64x2_pd,
+	_mm512_maskz_extractf64x2_pd, _mm512_extracti32x8_epi32,
+	_mm512_maskz_extracti32x8_epi32, _mm512_range_pd,
+	_mm512_maskz_range_pd, _mm512_range_ps, _mm512_maskz_range_ps,
+	_mm512_range_round_pd, _mm512_maskz_range_round_pd,
+	_mm512_range_round_ps, _mm512_maskz_range_round_ps,
+	_mm512_maskz_insertf64x2, _mm512_insertf32x8,
+	_mm512_maskz_insertf32x8): Formatting fixes.
+	(_mm512_extracti64x2_epi64, _mm512_maskz_extracti64x2_epi64): Use
+	_mm_setzero_si128 instead of _mm_setzero_di.
+	* config/i386/avx512vldqintrin.h (_mm_cvttpd_epi64,
+	_mm_cvttpd_epu64, _mm_cvtpd_epi64, _mm_cvtpd_epu64,
+	_mm_cvttps_epi64, _mm_maskz_cvttps_epi64, _mm_cvttps_epu64,
+	_mm_maskz_cvttps_epu64, _mm_maskz_mullo_epi64, _mm_cvtps_epi64,
+	_mm_maskz_cvtps_epi64, _mm_cvtps_epu64, _mm_maskz_cvtps_epu64,
+	_mm256_extracti64x2_epi64, _mm256_maskz_extracti64x2_epi64): Use
+	_mm_setzero_si128 instead of _mm_setzero_di.
+	(_mm256_extracti64x2_epi64, _mm256_maskz_extracti64x2_epi64):
+	Likewise in macros.
+	* config/i386/avx512vlbwintrin.h (_mm_maskz_mov_epi8,
+	_mm_maskz_loadu_epi16, _mm_maskz_mov_epi16, _mm_maskz_loadu_epi8,
+	_mm_permutexvar_epi16, _mm_maskz_maddubs_epi16): Use
+	_mm_setzero_si128 instead of _mm_setzero_hi.
+	(_mm_maskz_min_epu16, _mm_maskz_max_epu8, _mm_maskz_max_epi8,
+	_mm_maskz_min_epu8, _mm_maskz_min_epi8, _mm_maskz_max_epi16,
+	_mm_maskz_max_epu16, _mm_maskz_min_epi16): Use _mm_setzero_si128
+	instead of _mm_setzero_di.
+	(_mm_dbsad_epu8, _mm_maskz_shufflehi_epi16,
+	_mm_maskz_shufflelo_epi16): Use _mm_setzero_si128 instead of
+	_mm_setzero_hi.
+	(_mm_maskz_shufflehi_epi16, _mm_maskz_shufflelo_epi16,
+	_mm_maskz_slli_epi16): Use _mm_setzero_si128 instead of
+	_mm_setzero_hi.
+	(_mm_maskz_alignr_epi8): Use _mm_setzero_si128 instead of
+	_mm_setzero_di.
+	(_mm_maskz_mulhi_epi16, _mm_maskz_mulhi_epu16, _mm_maskz_mulhrs_epi16,
+	_mm_maskz_mullo_epi16, _mm_srav_epi16, _mm_srlv_epi16,
+	_mm_sllv_epi16): Use _mm_setzero_si128 instead of _mm_setzero_hi.
+
+2016-11-22  Carl Love  <cel@us.ibm.com>
+
+	* config/rs6000/rs6000-c.c: Add built-in support for vector compare
+	equal and vector compare not equal.  The vector compares take two
+	arguments of type vector bool char, vector bool short, vector bool int,
+	vector bool long long with the same return type.
+	* doc/extend.texi: Update built-in documentation file for the new
+	powerpc built-ins.
+
+2016-11-22  Uros Bizjak  <ubizjak@gmail.com>
+
+	* Makefile.in ($(lang_checks_parallelized)): Fix detection
+	of -j argument.
+
+2016-11-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config.gcc: Allow new rmprofile value for configure option
+	--with-multilib-list.
+	* config/arm/t-rmprofile: New file.
+	* doc/install.texi (--with-multilib-list): Document new rmprofile value
+	for ARM.
+
+2016-11-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/78439
+	* config/arm/vfp.md (*movdi_vfp_cortexa8): Use 'q' constraints for the
+	register operand in alternatives 4,5,6.
+
+2016-11-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	PR target/77904
+	* config/arm/arm.c (thumb1_compute_save_reg_mask): Mark frame pointer
+	in save register mask if it is needed.
+
+2016-11-22  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/78436
+	* gimple-ssa-store-merging.c (zero_char_buf): Removed.
+	(shift_bytes_in_array, shift_bytes_in_array_right,
+	merged_store_group::apply_stores): Formatting fixes.
+	(clear_bit_region): Likewise.  Use memset.
+	(encode_tree_to_bitpos): Formatting fixes.  Fix comment typos - EPXR
+	instead of EXPR and inerted instead of inserted.  Use memset instead
+	of zero_char_buf.  For !BYTES_BIG_ENDIAN decrease byte_size by 1
+	if shift_amnt is 0.
+
+	PR middle-end/78416
+	* expmed.c (expand_divmod): Use wide_int for computation of
+	op1_is_pow2.  Don't set it if op1 is 0.  Formatting fixes.
+	Use size <= HOST_BITS_PER_WIDE_INT instead of
+	HOST_BITS_PER_WIDE_INT >= size.
+
+	PR tree-optimization/78445
+	* tree-if-conv.c (tree_if_conversion): If any_pred_load_store or
+	any_complicated_phi, version loop even if flag_tree_loop_if_convert
+	is 1.  Formatting fix.
+
+2016-11-22  Martin Liska  <mliska@suse.cz>
+
+	PR ipa/78309
+	* ipa-icf.c (void sem_item::set_hash): Update m_hash_set.
+	(sem_function::get_hash): Use the new field.
+	(sem_function::parse): Remove an argument from ctor.
+	(sem_variable::parse): Likewise.
+	(sem_variable::get_hash): Use the new field.
+	(sem_item_optimizer::read_section): Use new ctor and set hash.
+	* ipa-icf.h: _hash is removed from sem_item::sem_item,
+	sem_variable::sem_variable, sem_function::sem_function.
+
+2016-11-21  Jeff Law  <law@redhat.com>
+
+	PR target/68538
+	* config/cris/cris.md: Don't call copy_to_mode_reg unless
+	can_create_pseudo_p is true.
+
+2016-11-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/68803
+	* config/rs6000/rs6000.md (*rotlsi3_insert_5, *rotldi3_insert_6,
+	*rotldi3_insert_7): New define_insns.
+
+2016-11-21  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000.md (movdi_internal32): Change constraints
+	so that DImode can be allocated to FP/vector registers in more
+	cases, and we can avoid direct move operations.  If the register
+	needs reloading, prefer GPRs over FP/vector registers.  In the
+	case of FPR vs. Altivec registers, prefer FPR registers unless we
+	have the ISA 3.0 reg+offset scalar instructions.
+	(movdi_internal64): Likewise.
+
+2016-11-21  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/67335
+	* omp-simd-clone.c (simd_clone_adjust_argument_types): Use NULL prefix
+	for tmp simd array if DECL_NAME (parm) is NULL.
+
+2016-11-20  Jeff Law  <law@redhat.com>
+
+	PR target/25128
+	* config/m68k/predicates.md (swap_peephole_relational_operator): New
+	predicate.
+	* config/m68k/m68k.md (relational tests against 65535/65536): New
+	peephole2.
+
+2016-11-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* tree-ssa-loop-prefetch.c: Delete FIXME after the includes.
+
+2016-11-21  Martin Sebor  <msebor@redhat.com>
+
+	* doc/invoke.texi (-fprintf-return-value): Document that option
+	is enabled by default.
+
+2016-11-21  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr-c.c (avr_register_target_pragmas): Use C++
+	for-loop declaration of loop variable.
+	(avr_register_target_pragmas, avr_cpu_cpp_builtins): Same.
+	* config/avr/avr.c (avr_popcount_each_byte)
+	(avr_init_expanders, avr_regs_to_save, sequent_regs_live)
+	(get_sequence_length, avr_prologue_setup_frame, avr_map_metric)
+	(avr_expand_epilogue, avr_function_arg_advance)
+	(avr_out_compare, avr_out_plus_1, avr_out_bitop, avr_out_fract)
+	(avr_rotate_bytes, _reg_unused_after, avr_assemble_integer)
+	(avr_adjust_reg_alloc_order, output_reload_in_const)
+	(avr_conditional_register_usage, avr_find_unused_d_reg)
+	(avr_map_decompose, avr_fold_builtin): Same.
+
+2016-11-21  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.c (avr_popcount): Remove static function.
+	(avr_popcount_each_byte, avr_out_bitop): Use popcount_hwi instead.
+
+2016-11-21  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.opt (mapcs-float): Delete option.
+	* arm.c (arm_option_override): Remove hunk relating to
+	TARGET_APCS_FLOAT.
+	* doc/invoke.texi (arm options): Remove documentation for -mapcs-float.
+
+2016-11-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-tailcall.c (process_assignment): Simplify the check for
+	a valid copy, allowing the source to be a local variable as
+	well as an SSA name.
+	(find_tail_calls): Allow copies between local variables to follow
+	the call.  Allow the result to be stored in any local variable,
+	even if it's an aggregate.
+	(eliminate_tail_call): Check whether the result is an SSA name
+	before updating its SSA_NAME_DEF_STMT.
+
+2016-11-21  David Malcolm  <dmalcolm@redhat.com>
+
+	PR preprocessor/78324
+	* input.c (get_substring_ranges_for_loc): Fail gracefully if
+	-ftrack-macro-expansion has a value other than 2.
+
+2016-11-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78400
+	* shrink-wrap.c (try_shrink_wrapping_separate): Call
+	df_update_entry_exit_and_calls instead of df_update_entry_block_defs
+	and df_update_exit_block_uses.
+
+2016-11-21  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	PR c++/71973
+	* doc/invoke.texi (-Wno-builtin-declaration-mismatch): Document the
+	new default-enabled warning..
+	* builtin-types.def (BT_CONST_TM_PTR): New primitive type.
+	(BT_PTR_CONST_STRING): Updated.
+	(BT_FN_SIZE_STRING_SIZE_CONST_STRING_CONST_PTR): Removed.
+	(BT_FN_SIZE_STRING_SIZE_CONST_STRING_CONST_TM_PTR): New function type.
+	* builtins.def (DEF_TM_BUILTIN): Disable BOTH_P for TM builtins.
+	(strftime): Update builtin function.
+	* tree-core.h (TI_CONST_TM_PTR_TYPE): New enum value.
+	* tree.h (const_tm_ptr_type_node): New type node.
+	* tree.c (free_lang_data, build_common_tree_nodes): Initialize
+	const_tm_ptr_type_node.
+
+2016-11-21  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	PR tree-optimization/78413
+	* tree-if-conv.c (versionable_outer_loop_p): Require that both
+	inner and outer loop latches have single predecessors.
+
+2016-11-21  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/78093
+	* config/avr/avr.c (avr_decl_maybe_lds_p): New static function.
+	(avr_encode_section_info) [TARGET_ABSDATA && AVR_TINY]: Use it.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* rtl.h: Adjust prototype.
+	* rtlanal.c (dead_or_set_p): Change argument type to rtx_insn *.
+	(dead_or_set_regno_p): Likewise.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* rtl.h: Adjust prototype.
+	* rtlanal.c (add_int_reg_note): Change argument type to rtx_insn *.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* function.c (contains): Change argument type to rtx_insn *.
+	(prologue_contains): Likewise.
+	(epilogue_contains): Likewise.
+	(prologue_epilogue_contains): Likewise.
+	* function.h: Adjust prototype.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* optabs.c (emit_libcall_block): Change argument type to
+	rtx_insn *.
+	* optabs.h: Adjust prototype.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* cfgrtl.c (delete_insn): Change argument type to rtx_insn *.
+	(fixup_reorder_chain): Adjust.
+	* cfgrtl.h: Adjust prototype.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* rtl.h: Adjust prototype.
+	* rtlanal.c (replace_label_in_insn): Change argument type to
+	rtx_insn *.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* config/v850/v850.c (expand_prologue): Adjust.
+	(expand_epilogue): Likewise.
+	* expr.c (init_expr_target): Likewise.
+	* genrecog.c (print_subroutine): Always make the argument type
+	rtx_insn *.
+	* recog.h: Adjust prototype.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* config/aarch64/aarch64.c (aarch64_emit_unlikely_jump): split
+	up variables to make some rtx_insn *.
+	* config/alpha/alpha.c (emit_unlikely_jump): Likewise.
+	* config/arc/arc.c: Likewise.
+	* config/arm/arm.c: Likewise.
+	* config/mn10300/mn10300.c (mn10300_legitimize_pic_address): Likewise.
+	* config/rs6000/rs6000.c (rs6000_expand_split_stack_prologue):
+	Likewise.
+	* config/spu/spu.c (spu_emit_branch_hint): Likewise.
+
+2016-11-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* config/arm/arm.c (legitimize_pic_address): Change to use
+	rtx_insn * as the type of variables.
+	(arm_pic_static_addr): Likewise.
+	(arm_emit_movpair): Likewise.
+	* config/c6x/c6x.c (reorg_split_calls): Likewise.
+	* config/darwin.c (machopic_legitimize_pic_address): Likewise.
+	* config/frv/frv.c (frv_optimize_membar_local): Likewise.
+	* config/frv/frv.md: Likewise.
+	* config/i386/i386-protos.h: Likewise.
+	* config/i386/i386.c (ix86_expand_split_stack_prologue): Likewise.
+	(ix86_split_fp_branch): Likewise.
+	(predict_jump): Likewise.
+	* config/ia64/ia64.c: Likewise.
+	* config/mcore/mcore.c: Likewise.
+	* config/rs6000/rs6000.c (rs6000_legitimize_tls_address): Likewise.
+	* config/s390/s390.c: Likewise.
+	* config/s390/s390.md: Likewise.
+	* config/spu/spu.md: Likewise.
+	* config/tilegx/tilegx.c (tilegx_legitimize_tls_address): Likewise.
+	* lower-subreg.c (resolve_simple_move): Likewise.
+
+2016-11-20  Jeff Law  <law@redhat.com>
+
+	PR target/48551
+	* reload.h (struct target_reload): Make x_double_reg_address_ok
+	be per-mode rather.
+	* reload.c (find_reloads_address): Check if double_reg_address_ok
+	is true for the mode of the memory reference.
+	* reload1.c (init_reload): Initialize double_reg_address_ok for
+	each mode.
+
+2016-11-20  Aldy Hernandez  <aldyh@redhat.com>
+
+	PR middle-end/61409
+	* tree-ssa-uninit.c: Define new global max_phi_args.
+	(compute_uninit_opnds_pos): Use max_phi_args.
+	(prune_uninit_phi_opnds): Same.
+	(use_pred_not_overlap_with_undef_path_pred): Remove reference to
+	missing NUM_PREDS in function comment.
+	(can_one_predicate_be_invalidated_p): New.
+	(can_chain_union_be_invalidated_p): New.
+	(flatten_out_predicate_chains): New.
+	(uninit_ops_invalidate_phi_use): New.
+	(is_use_properly_guarded): Call uninit_ops_invalidate_phi_use.
+
+2016-11-20  Marc Glisse  <marc.glisse@inria.fr>
+
+	* fold-const.c (fold_comparison): Ignore EXACT_DIV_EXPR.
+	* match.pd (A /[ex] B CMP C): New simplifications.
+
+2016-11-20  Marc Glisse  <marc.glisse@inria.fr>
+
+	* match.pd (0 / X, X / X, X % X): New simplifications.
+
+2016-11-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/i386.c (ix86_can_inline_p): Use || instead of &
+	when checking if callee's isa flags are subset of caller's isa flags.
+	Fix comment wording.
+
+	* config/i386/i386.c (ix86_valid_target_attribute_tree): Don't
+	clear opts->x_ix86_isa_flags, clear opts->x_ix86_isa_flags2
+	instead and using = 0 instead of &= 0.
+
+	* config/i386/i386.c (def_builtin, def_builtin2, def_builtin_const2,
+	ix86_add_new_builtins): Formatting fixes.
+	(ix86_expand_builtin): Use || instead of && for isa vs. isa2.
+	(ix86_get_builtin): Likewise.
+
+	* config/i386/i386.c (ix86_expand_builtin): Remove msk_mov variable,
+	don't initialize it, don't use it for the case where it isn't
+	provable %{z} nor using the same argument, instead move merge
+	argument into a new pseudo and use that as target.  Formatting fixes.
+
+2016-11-19  Jeff Law  <law@redhat.com>
+
+	PR target/25111
+	* config/m68k/m68k.md (bsetdreg): New pattern.
+	(bchgdreg, bclrdreg): Likewise.
+
+2016-11-19  Kaz Kojima  <kkojima@gcc.gnu.org>
+
+	PR target/78426
+	* config/sh/sh-mem.cc (sh_expand_cmpnstr): Use copy_to_mode_reg
+	instead of force_reg.
+	(sh_expand_setmem): Likewise.
+
+2016-11-19  Krister Walfridsson  <krister.walfridsson@gmail.com>
+
+	* config.gcc (*-*-netbsd): Set use_gcc_stdint=wrap.
+
+2016-11-18  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/tilegx.c (tilegx_gen_bundles): Preserve
+	  end-of-bundle marker for consecutive barriers.
+
+2016-11-18  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/tilegx.md (clzsi2): Fix for big-endian.
+
+2016-11-18  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/78419
+	* multiple_target.c (get_attr_len): Start with argnum and increment
+	argnum on every arg.  Use strchr in a loop instead of counting commas
+	manually.
+	(get_attr_str): Increment argnum for every comma in the string.
+	(separate_attrs): Use for instead of while loop, simplify.
+	(expand_target_clones): Rename defenition argument to definition.
+	Free attrs and attr_str even when diagnosing errors.  Temporarily
+	change input_location around targetm.target_option.valid_attribute_p
+	calls.  Don't emit warning or errors if that function fails.
+
+	* dwarf2out.c (size_of_discr_list): Fix typo in function comment.
+
+	PR debug/78191
+	* dwarf2out.c (abbrev_opt_base_type_end): New variable.
+	(die_abbrev_cmp): Sort dies with die_abbrev smaller than
+	abbrev_opt_base_type_end only by increasing die_abbrev, before
+	any other dies.
+	(optimize_abbrev_table): Don't change abbrev numbers of
+	base types and CU or optimize implicit consts in them if
+	calc_base_type_die_sizes has been called during build_abbrev_table.
+	(calc_base_type_die_sizes): If abbrev_opt_start, set
+	abbrev_opt_base_type_end to one plus largest base type's die_abbrev.
+
+2016-11-18  Jeff Law  <law@redhat.com>
+
+	PR target/25112
+	* config/m68k/m68k.c (moveq feeding equality comparison): New
+	peepholes.
+	* config/m68k/predicates.md (addq_subq_operand): New predicate.
+	(equality_comparison_operator): Likewise.
+
+2016-11-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* rtlanal.c (load_extend_op): Move to...
+	* rtl.h: ...here and make inline.
+
+2016-11-18  Terry Guo  <terry.guo@arm.com>
+	    Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* common/config/arm/arm-common.c (arm_target_thumb_only): New function.
+	* config/arm/arm-opts.h: Include arm-flags.h.
+	(struct arm_arch_core_flag): Define.
+	(arm_arch_core_flags): Define.
+	* config/arm/arm-protos.h: Include arm-flags.h
+	(FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32,
+	FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E,
+	FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM,
+	FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV,
+	FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT,
+	FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST,
+	FL_TUNE, FL_FOR_ARCH2, FL_FOR_ARCH3, FL_FOR_ARCH3M, FL_FOR_ARCH4,
+	FL_FOR_ARCH4T, FL_FOR_ARCH5, FL_FOR_ARCH5T, FL_FOR_ARCH5E,
+	FL_FOR_ARCH5TE, FL_FOR_ARCH5TEJ, FL_FOR_ARCH6, FL_FOR_ARCH6J,
+	FL_FOR_ARCH6K, FL_FOR_ARCH6Z, FL_FOR_ARCH6ZK, FL_FOR_ARCH6KZ,
+	FL_FOR_ARCH6T2, FL_FOR_ARCH6M, FL_FOR_ARCH7, FL_FOR_ARCH7A,
+	FL_FOR_ARCH7VE, FL_FOR_ARCH7R, FL_FOR_ARCH7M, FL_FOR_ARCH7EM,
+	FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A, FL2_FOR_ARCH8_2A, FL_FOR_ARCH8M_BASE,
+	FL_FOR_ARCH8M_MAIN, arm_feature_set, ARM_FSET_MAKE,
+	ARM_FSET_MAKE_CPU1, ARM_FSET_MAKE_CPU2, ARM_FSET_CPU1, ARM_FSET_CPU2,
+	ARM_FSET_EMPTY, ARM_FSET_ANY, ARM_FSET_HAS_CPU1, ARM_FSET_HAS_CPU2,
+	ARM_FSET_HAS_CPU, ARM_FSET_ADD_CPU1, ARM_FSET_ADD_CPU2,
+	ARM_FSET_DEL_CPU1, ARM_FSET_DEL_CPU2, ARM_FSET_UNION, ARM_FSET_INTER,
+	ARM_FSET_XOR, ARM_FSET_EXCLUDE, ARM_FSET_IS_EMPTY,
+	ARM_FSET_CPU_SUBSET): Move to ...
+	* config/arm/arm-flags.h: This new file.
+	* config/arm/arm.h (TARGET_MODE_SPEC_FUNCTIONS): Define.
+	(EXTRA_SPEC_FUNCTIONS): Add TARGET_MODE_SPEC_FUNCTIONS to its value.
+	(TARGET_MODE_SPECS): Define.
+	(DRIVER_SELF_SPECS): Add TARGET_MODE_SPECS to its value.
+
+2016-11-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm-protos.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M,
+	FL_MODE26, FL_MODE32, FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED,
+	FL_STRONG, FL_ARCH5E, FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF,
+	FL_ARCH6K, FL_THUMB2, FL_NOTM, FL_THUMB_DIV, FL_VFPV3, FL_NEON,
+	FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, FL_ARCH8, FL_CRC32, FL_SMALLMUL,
+	FL_NO_VOLATILE_CE, FL_IWMMXT, FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1,
+	FL2_ARCH8_2, FL2_FP16INST): Reindent comment, add final dot when
+	missing and make value unsigned.
+	(arm_feature_set): Use unsigned entries instead of unsigned long.
+
+2016-11-18  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	Re-apply after PR bootstrap/77359 is fixed:
+	2016-08-23  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	* explow.c (get_dynamic_stack_size): Take known alignment of stack
+	pointer + STACK_DYNAMIC_OFFSET into account when calculating the
+	size needed.
+
+2016-11-18  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+	PR bootstrap/77359
+	* config/rs6000/rs6000.c (rs6000_stack_info): Properly align local
+	variables in functions calling alloca.  Also update the ASCII
+	drawings.
+	* config/rs6000/rs6000.h (STARTING_FRAME_OFFSET)
+	(STACK_DYNAMIC_OFFSET): Likewise.
+	* config/rs6000/aix.h (STARTING_FRAME_OFFSET)
+	(STACK_DYNAMIC_OFFSET): Copy AIX specific versions of the rs6000.h
+	macros to aix.h.
+
+2016-11-18  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* combine.c (try_combine): Use rtx_mode_t instead of std::make_pair.
+	* dwarf2out.c (mem_loc_descriptor, loc_descriptor): Likewise.
+	(add_const_value_attribute): Likewise.
+	* explow.c (plus_constant): Likewise.
+	* expmed.c (expand_mult, make_tree): Likewise.
+	* expr.c (convert_modes): Likewise.
+	* loop-doloop.c (doloop_optimize): Likewise.
+	* postreload.c (reload_cse_simplify_set): Likewise.
+	* simplify-rtx.c (simplify_const_unary_operation): Likewise
+	(simplify_binary_operation_1, simplify_const_binary_operation):
+	Likewise.
+	(simplify_const_relational_operation, simplify_immed_subreg): Likewise.
+	* wide-int.h: Update documentation to recommend rtx_mode_t
+	instead of std::make_pair.
+
+2016-11-18  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* tree.h (SET_DECL_MODE): New macro.
+	* cfgexpand.c (avoid_deep_ter_for_debug): Use SET_DECL_MODE.
+	(expand_gimple_basic_block): Likewise.
+	* function.c (split_complex_args): Likeise.
+	* ipa-prop.c (ipa_modify_call_arguments): Likewise.
+	* omp-simd-clone.c (ipa_simd_modify_stmt_ops): Likewise.
+	* stor-layout.c (layout_decl, relayout_decl): Likewise.
+	(finish_bitfield_representative): Likewise.
+	* tree.c (make_node_stat): Likewise.
+	* tree-inline.c (remap_ssa_name): Likewise.
+	(tree_function_versioning): Likewise.
+	* tree-into-ssa.c (rewrite_debug_stmt_uses): Likewise.
+	* tree-sra.c (sra_ipa_reset_debug_stmts): Likewise.
+	* tree-ssa-ccp.c (optimize_atomic_bit_test_and): Likewise.
+	* tree-ssa-loop-ivopts.c (remove_unused_ivs): Likewise.
+	* tree-ssa.c (insert_debug_temp_for_var_def): Likewise.
+	* tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
+	* varasm.c (make_debug_expr_from_rtl): Likewise.
+
+2016-11-18  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/71785
+	* bb-reorder.c (maybe_duplicate_computed_goto): New function.
+	(duplicate_computed_gotos): New function.
+	(pass_duplicate_computed_gotos::execute): Rewrite.
+
+2016-11-17  Jeff Law  <law@redhat.com>
+
+	PR target/47192
+	* config/m68k/m68k.c (m68k_expand_epilogue): Emit a scheduling
+	barrier prior to deallocating the stack.
+
+2016-11-17  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* config/arc/arc.md (cmem bit/sign-extend peephole2): New peephole
+	to make better use of cmem loads in the case where a single bit is
+	being accessed.
+	* config/arc/predicates.md (ge_lt_comparison_operator): New predicate.
+
+2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>
+
+	* config/i386/i386.c (processor_features): Add F_AVX5124VNNIW,
+	F_AVX5124FMAPS.
+	(isa_names_table): Handle new features.
+
+2016-11-17  Kirill Yukhin  <kirill.yukhin@gmail.com>
+	    Andrew Senkevich <andrew.senkevich@intel.com>
+
+	* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX5124FMAPS_SET,
+	OPTION_MASK_ISA_AVX5124FMAPS_UNSET, OPTION_MASK_ISA_AVX5124VNNIW_SET,
+	OPTION_MASK_ISA_AVX5124VNNIW_UNSET): New.
+	(ix86_handle_option): Handle OPT_mavx5124fmaps, OPT_mavx5124vnniw.
+	* config.gcc: Add avx5124fmapsintrin.h, avx5124vnniwintrin.h.
+	* config/i386/avx5124fmapsintrin.h: New file.
+	* config/i386/avx5124vnniwintrin.h: Ditto.
+	* config/i386/constraints.md (h): New constraint.
+	* config/i386/cpuid.h (bit_AVX5124VNNIW, bit_AVX5124FMAPS): New.
+	* config/i386/driver-i386.c (host_detect_local_cpu):
+	Detect avx5124fmaps, avx5124vnniw.
+	* config/i386/i386-builtin-types.def: Add types
+	V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI,
+	V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF,
+	V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF,
+	V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI,
+	V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI,
+	V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI.
+	* config/i386/i386-builtin.def (__builtin_ia32_4fmaddps_mask,
+	__builtin_ia32_4fmaddps, __builtin_ia32_4fmaddss,
+	__builtin_ia32_4fmaddss_mask, __builtin_ia32_4fnmaddps_mask,
+	__builtin_ia32_4fnmaddps, __builtin_ia32_4fnmaddss,
+	__builtin_ia32_4fnmaddss_mask, __builtin_ia32_vp4dpwssd,
+	__builtin_ia32_vp4dpwssd_mask, __builtin_ia32_vp4dpwssds,
+	__builtin_ia32_vp4dpwssds_mask): New.
+	* config/i386/i386-c.c (ix86_target_macros_internal):
+	Define __AVX5124FMAPS__, __AVX5124VNNIW__.
+	* config/i386/i386-modes.def: Fixed comment typos, added new
+	modes (VECTOR_MODES (FLOAT, 256), VECTOR_MODE (INT, SI, 64)).
+	* config/i386/i386.c (ix86_target_string): Add -mavx5124fmaps,
+	-mavx5124vnniw.
+	(PTA_AVX5124FMAPS, PTA_AVX5124VNNIW): Define.
+	(ix86_option_override_internal): Handle new options.
+	(ix86_valid_target_attribute_inner_p): Add avx5124fmaps,
+	avx5124vnniw.
+	(ix86_expand_builtin): Handle new builtins.
+	(ix86_additional_allocno_class_p): New.
+	* config/i386/i386.h (TARGET_AVX5124FMAPS, TARGET_AVX5124FMAPS_P,
+	TARGET_AVX5124VNNIW, TARGET_AVX5124VNNIW_P): Define.
+	(reg_class): Add MOD4_SSE_REGS.
+	(MOD4_SSE_REG_P, MOD4_SSE_REGNO_P): New.
+	* config/i386/i386.opt: Add mavx5124fmaps, mavx5124vnniw.
+	* config/i386/immintrin.h: Include avx5124fmapsintrin.h,
+	avx5124vnniwintrin.h.
+	* config/i386/sse.md (unspec): Add UNSPEC_VP4FMADD, UNSPEC_VP4FNMADD,
+	UNSPEC_VP4DPWSSD, UNSPEC_VP4DPWSSDS.
+	(define_mode_iterator IMOD4): New.
+	(define_mode_attr imod4_narrow): Ditto.
+	(define_insn "mov<mode>"): Ditto.
+	(define_insn "avx5124fmaddps_4fmaddps"): Ditto.
+	(define_insn "avx5124fmaddps_4fmaddps_mask"): Ditto.
+	(define_insn "avx5124fmaddps_4fmaddps_maskz"): Ditto.
+	(define_insn "avx5124fmaddps_4fmaddss"): Ditto.
+	(define_insn "avx5124fmaddps_4fmaddss_mask"): Ditto.
+	(define_insn "avx5124fmaddps_4fmaddss_maskz"): Ditto.
+	(define_insn "avx5124fmaddps_4fnmaddps"): Ditto.
+	(define_insn "avx5124fmaddps_4fnmaddps_mask"): Ditto.
+	(define_insn "avx5124fmaddps_4fnmaddps_maskz"): Ditto.
+	(define_insn "avx5124fmaddps_4fnmaddss"): Ditto.
+	(define_insn "avx5124fmaddps_4fnmaddss_mask"): Ditto.
+	(define_insn "avx5124fmaddps_4fnmaddss_maskz"): Ditto.
+	(define_insn "avx5124vnniw_vp4dpwssd"): Ditto.
+	(define_insn "avx5124vnniw_vp4dpwssd_mask"): Ditto.
+	(define_insn "avx5124vnniw_vp4dpwssd_maskz"): Ditto.
+	(define_insn "avx5124vnniw_vp4dpwssds"): Ditto.
+	(define_insn "avx5124vnniw_vp4dpwssds_mask"): Ditto.
+	(define_insn "avx5124vnniw_vp4dpwssds_maskz"): Ditto.
+	* init-regs.c (initialize_uninitialized_regs): Add emit_clobber call.
+	* genmodes.c (mode_size_inline): Extend return type.
+	* machmode.h (mode_size, mode_base_align): Extend type.
+
+2016-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/78101
+	* config/rs6000/predicates.md (fusion_addis_mem_combo_load): Add
+	the appropriate checks for SFmode/DFmode load/stores in GPR
+	registers.
+	(fusion_addis_mem_combo_store): Likewise.
+	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Rename
+	fusion_fpr_* to fusion_vsx_* and add in support for ISA 3.0 scalar
+	d-form instructions for traditional Altivec registers.
+	(emit_fusion_p9_load): Likewise.
+	(emit_fusion_p9_store): Likewise.
+	* config/rs6000/rs6000.md (p9 fusion store peephole2): Remove
+	early clobber from scratch register.  Do not match if the register
+	being stored is the scratch register.
+	(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load): Rename fusion_fpr_*
+	to fusion_vsx_* and add in support for ISA 3.0 scalar d-form
+	instructions for traditional Altivec registers.
+	(fusion_fpr_<P:mode>_<FPR_FUSION:mode>_load): Likewise.
+	(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store): Likewise.
+	(fusion_fpr_<P:mode>_<FPR_FUSION:mode>_store): Likewise.
+
+2016-11-17  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	PR target/77933
+	* config/arm/arm.c (thumb1_expand_prologue): Distinguish between lr
+	being live in the function and lr needing to be saved.  Distinguish
+	between already saved pushable registers and registers to push.
+	Check for LR being an available pushable register.
+
+2016-11-17  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
+
+	* config/i386/i386.md (cmpstrnsi): New test to bail out if neither
+	string input is a string constant.
+	* builtins.c (expand_builtin_strncmp): Attempt expansion of strncmp
+	via cmpstrnsi even if neither string is constant.
+
+2016-11-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/78201
+	* varasm.c (default_use_anchors_for_symbol_p): Fix a comment typo.
+	Don't test decl != NULL.  Don't look at DECL_SIZE, but DECL_SIZE_UNIT
+	instead, return false if it is NULL, or doesn't fit into uhwi, or
+	is larger or equal to targetm.max_anchor_offset.
+
+2016-11-17  Pip Cet  <pipcet@gmail.com>
+	    Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR rtl-optimization/78355
+	* doc/tm.texi.in (SLOW_UNALIGNED_ACCESS): Document that the macro only
+	needs to deal with unaligned accesses.
+	* doc/tm.texi: Regenerate.
+	* lra-constraints.c (simplify_operand_subreg): Only invoke
+	SLOW_UNALIGNED_ACCESS on innermode if the MEM is not aligned enough.
+
+2016-11-17  David Malcolm  <dmalcolm@redhat.com>
+
+	* input.c (selftest::test_lexer_string_locations_long_line): New
+	function.
+	(selftest::test_lexer_string_locations_raw_string_multiline): New
+	function.
+	(selftest::input_c_tests): Call the new functions, via
+	for_each_line_table_case.
+
+2016-11-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.md (mov<mode>): Call
+	aarch64_split_dimode_const_store on DImode constant stores.
+	* config/aarch64/aarch64-protos.h (aarch64_split_dimode_const_store):
+	New prototype.
+	* config/aarch64/aarch64.c (aarch64_split_dimode_const_store): New
+	function.
+
+2016-11-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+	    Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/77848
+	* tree-if-conv.c (tree_if_conversion): Always version loops unless
+	the user specified -ftree-loop-if-convert.
+
+2016-11-17  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	PR target/77308
+	* config/arm/arm.md (*thumb2_ldrd, *thumb2_ldrd_base,
+	*thumb2_ldrd_base_neg, *thumb2_strd, *thumb2_strd_base,
+	*thumb2_strd_base_neg): Recognize insn regardless of
+	current_tune->prefer_ldrd_strd.
+	* config/arm/ldrdstrd.md: Enable all ldrd/strd peephole rules
+	whenever possible.
+
+2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.c (arc_ccfsm_post_advance): Handle return
+	instruction type.
+
+2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc-arches.def: Add FPX quarkse instruction as valid
+	for arcem.
+	* config/arc/arc-c.def (__ARC_FPX_QUARK__): Define.
+	* config/arc/arc-cpus.def (quarkse_em): Add.
+	* config/arc/arc-options.def (FL_FPX_QUARK, FL_QUARK): Likewise.
+	* config/arc/arc-opts.h (FPX_QK): Define.
+	* config/arc/arc-tables.opt: Regenerate.
+	* config/arc/arc.c (gen_compare_reg): Change.
+	(arc_register_move_cost): Avoid Dy,Dx moves.
+	* config/arc/arc.h (TARGET_HARD_FLOAT): Change.
+	(TARGET_FPX_QUARK, TARGET_FP_ASSIST): Define.
+	* config/arc/arc.md (divsf3, sqrtsf2, fix_truncsfsi2, floatsisf2):
+	New expands.
+	* config/arc/fpu.md (divsf3_fpu, sqrtsf2_fpu, floatsisf2_fpu)
+	(fix_truncsfsi2_fpu): Rename.
+	* config/arc/fpx.md (cmp_quark, cmpsf_quark_, cmpsf_quark_ord)
+	(cmpsf_quark_uneq, cmpsf_quark_eq, divsf3_quark, sqrtsf2_quark)
+	(fix_truncsfsi2_quark, floatsisf2_quark): New patterns.
+	* config/arc/t-multilib: Regenerate.
+
+2016-11-17  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.c (avr_print_operand_address): Use CONST_INT_P if
+	appropriate.
+	(ashlqi3_out, ashlsi3_out, ashrqi3_out, ashrhi3_out): Same.
+	(ashrsi3_out, lshrqi3_out, lshrhi3_out, lshrsi3_out): Same.
+	(avr_rtx_costs_1, extra_constraint_Q): Same.
+	(avr_address_cost): Use SUBREG_P if possible.
+
+2016-11-17  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/78383
+	* tree-cfgcleanup.c (cleanup_control_flow_bb): Do not turn
+	non-local goto into CFG.
+
+2016-11-17  Richard Biener  <rguenther@suse.de>
+
+	* common.opt (ftree-loop-if-convert-stores): Mark as preserved for
+	backward compatibility.
+	* doc/invoke.texi (ftree-loop-if-convert-stores): Remove.
+	* tree-if-conv.c (pass_if_conversion::gate): Do not test
+	flag_tree_loop_if_convert_stores.
+	(pass_if_conversion::execute): Likewise.
+
+2016-11-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/predicates.md (aarch64_reg_or_fp_zero): Check for
+	const_double code before calling aarch64_float_const_zero_rtx_p.
+
+2016-11-17  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78306
+	* ipa-inline-analysis.c (initialize_inline_failed): Do not
+	inhibit inlining if function calls cilk_spawn.
+	(can_inline_edge_p): Likewise.
+
+2016-11-17  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/78305
+	* fold-const.c (negate_expr_p): Fix multiplication case.
+
+2016-11-17  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	PR target/78357
+	* config/nios2/nios2.c (nios2_init_libfuncs): Remove TARGET_LINUX_ABI
+	condition.
+	(TARGET_INIT_LIBFUNCS): Delete definition and...
+	* config/nios2/linux.h (TARGET_INIT_LIBFUNCS): ...move to here, add
+	comments.
+
+2016-11-17  Krister Walfridsson  <krister.walfridsson@gmail.com>
+
+	* config/netbsd-stdint.h: New.
+	* config.gcc (i[34567]86-*-netbsd): Add netbsd-stdint.h to tm_file.
+	(x86_64-*-netbsd*): Likewise.
+
+2016-11-16  Andrew PInski  <apinski@cavium.com>
+
+	* config/aarch64/aarch64.opt (mverbose-cost-dump): New option.
+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Use
+	flag_aarch64_verbose_cost instead of checking for details dump.
+	(aarch64_rtx_costs_wrapper): Likewise.
+
+2016-11-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/78378
+	* combine.c (make_extraction): Use force_to_mode for non-{REG,MEM}
+	inner only if pos is 0.  Fix up formatting.
+
+2016-11-17  Alan Modra  <amodra@gmail.com>
+
+	PR rtl-optimization/78325
+	PR rtl-optimization/70890
+	* ira.c (combine_and_move_insns): Only remove REG_EQUIV notes
+	for dead regno.
+
+2016-11-16  Jason Merrill  <jason@redhat.com>
+
+	* rtl.h: Declare gt_ggc_mx and gt_pch_nx.
+
+2016-11-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+	    Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/77848
+	* tree-if-conv.c (version_loop_for_if_conversion): When versioning
+	an outer loop, only save basic block aux information for the inner
+	loop.
+	(versionable_outer_loop_p): New function.
+	(tree_if_conversion): Version the outer loop instead of the inner
+	one if the pattern will be recognized for outer-loop
+	vectorization.
+
+2016-11-16  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* gcc/bb-reorder.c: Remove 'toplev.h' include.
+	(pass_partition_blocks::gate): No longer check
+	user_defined_section_attribute, instead check the function decl
+	for a section attribute.
+	* gcc/c-family/c-attribs.c (handle_section_attribute): No longer
+	set user_defined_section_attribute.
+	* gcc/final.c (rest_of_handle_final): Likewise.
+	* gcc/toplev.c: Remove definition of user_defined_section_attribute.
+	* gcc/toplev.h: Remove declaration of
+	user_defined_section_attribute.
+
+2016-11-16  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* config/mips/mips.md (casesi_internal_mips16_<mode>):
+	Explicitly switch between JR and JRC for the table jump.  Adjust
+	instruction count.
+
+2016-11-16  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* config/mips/mips.md (casesi_internal_mips16_<mode>): Set
+	`insn_count' to 11 rather than 16.
+
+2016-11-16  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* config/mips/mips.md (casesi_internal_mips16_<mode>): Use the
+	`ltu' rather than `leu' operation in the RTL pattern
+
+2016-11-16  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* config/mips/mips.md (casesi_internal_mips16_<mode>): Add
+	missing <d> instruction prefixes throughout.  Correct
+	formatting.
+
+2016-11-16  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* config/mips/mips.c (mips_output_jump): Output R_MICROMIPS_JALR
+	rather than R_MIPS_JALR relocation in microMIPS code.  Do not
+	cancel short delay slots in PIC call relaxation.
+
+2016-11-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.md (arm_addsi3): Add alternative for addition of
+	general register with general register or ARM constant into SP
+	register.
+
+2016-11-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR fortran/78299
+	* omp-low.c (expand_omp_for_static_nochunk): Don't assert
+	that loop->header == body_bb if broken_loop.
+
+2015-11-16  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* tree-ssa-math-opts.c (bswap_replace): Remove test
+	of SLOW_UNALIGNED_ACCESS.
+
+2016-11-16  Alexander Monakov  <amonakov@ispras.ru>
+
+	* config/nvptx/mkoffload.c (main): Check that either OpenACC or OpenMP
+	is selected.  Pass -mgomp to offload compiler in OpenMP case.
+	* config/nvptx/nvptx-protos.h (nvptx_shuffle_kind): Move enum
+	declaration from nvptx.c.
+	(nvptx_gen_shuffle): Declare.
+	(nvptx_output_set_softstack): Declare.
+	* config/nvptx/nvptx.c (nvptx_shuffle_kind): Move to nvptx-protos.h.
+	(need_softstack_decl): New variable.
+	(need_unisimt_decl): New variable.
+	(diagnose_openacc_conflict): New.  Use it...
+	(nvptx_option_override): ...here.  Handle TARGET_GOMP.
+	(nvptx_encode_section_info): Handle "shared" attribute.
+	(write_as_kernel): Restrict to OpenACC target regions.
+	(init_softstack_frame): New.
+	(nvptx_init_unisimt_predicate): New.
+	(write_omp_entry): New.  Use it...
+	(nvptx_declare_function_name): ...here to emit OpenMP target region
+	entrypoints.  Handle TARGET_SOFT_STACK.  Call
+	nvptx_init_unisimt_predicate.
+	(nvptx_output_set_softstack): New.
+	(nvptx_get_drap_rtx): Return %argp as the DRAP if needed.
+	(nvptx_gen_shuffle): Export.
+	(nvptx_output_call_insn): Handle COND_EXEC patterns.  Emit instruction
+	predicate.
+	(nvptx_print_operand): Fix handling of instruction predicates.
+	(nvptx_get_unisimt_master): New helper function.
+	(nvptx_get_unisimt_predicate): Ditto.
+	(nvptx_call_insn_is_syscall_p): Ditto.
+	(nvptx_unisimt_handle_set): Ditto.
+	(nvptx_reorg_uniform_simt): New.  Transform code for -muniform-simt.
+	(nvptx_reorg): Call nvptx_reorg_uniform_simt.
+	(nvptx_handle_shared_attribute): New.  Use it...
+	(nvptx_attribute_table): ... here (new entry).
+	(nvptx_record_offload_symbol): Handle NULL attributes.
+	(nvptx_file_end): Handle need_softstack_decl and need_unisimt_decl.
+	(nvptx_simt_vf): New.
+	(TARGET_SIMT_VF): Define.
+	* config/nvptx/nvptx.h (TARGET_CPU_CPP_BUILTINS): Define
+	__nvptx_softstack or __nvptx_unisimt__ when -msoft-stack, or resp.
+	-muniform-simt option is active.
+	(STACK_SIZE_MODE): Define.
+	(FIXED_REGISTERS): Adjust.
+	(SOFTSTACK_SLOT_REGNUM): New.
+	(SOFTSTACK_PREV_REGNUM): New.
+	(REGISTER_NAMES): Adjust.
+	(struct machine_function): New fields.
+	* config/nvptx/nvptx.md (UNSPEC_SET_SOFTSTACK): New.
+	(UNSPEC_VOTE_BALLOT): Ditto.
+	(UNSPEC_LANEID): Ditto.
+	(UNSPECV_NOUNROLL): Ditto.
+	(atomic): New attribute.
+	(predicable): New attribute.  Generate predicated forms via
+	define_cond_exec.
+	(br_true): Mark as not predicable.
+	(br_false): Ditto.
+	(br_true_uni): Ditto.
+	(br_false_uni): Ditto.
+	(return): Ditto.
+	(trap_if_true): Ditto.
+	(trap_if_false): Ditto.
+	(nvptx_fork): Ditto.
+	(nvptx_forked): Ditto.
+	(nvptx_joining): Ditto.
+	(nvptx_join): Ditto.
+	(nvptx_barsync): Ditto.
+	(epilogue): Emit stack restore if TARGET_SOFT_STACK.
+	(allocate_stack): Implement for TARGET_SOFT_STACK.  Remove unused code.
+	(allocate_stack_<mode>): Remove unused pattern.
+	(set_softstack_insn): New pattern.
+	(restore_stack_block): Handle for TARGET_SOFT_STACK.
+	(nvptx_vote_ballot): New pattern.
+	(omp_simt_lane): Ditto.
+	(omp_simt_last_lane): Ditto.
+	(omp_simt_ordered): Ditto.
+	(omp_simt_vote_any): Ditto.
+	(omp_simt_xchg_bfly): Ditto.
+	(omp_simt_xchg_idx): Ditto.
+	(nvptx_nounroll): Ditto.
+	(atomic_compare_and_swap<mode>_1): Mark with atomic attribute.
+	(atomic_exchange<mode>): Ditto.
+	(atomic_fetch_add<mode>): Ditto.
+	(atomic_fetch_addsf): Ditto.
+	(atomic_fetch_<logic><mode>): Ditto.
+	* config/nvptx/nvptx.opt (msoft-stack): New option.
+	(muniform-simt): Ditto.
+	(mgomp): Ditto.
+	* config/nvptx/t-nvptx (MULTILIB_OPTIONS): New.
+	* doc/extend.texi (Nvidia PTX Variable Attributes): New section.
+	* doc/invoke.texi (msoft-stack): Document.
+	(muniform-simt): Document
+	(mgomp): Document.
+	* doc/tm.texi: Regenerate.
+	* doc/tm.texi.in (TARGET_SIMT_VF): New hook.
+	* target.def: Define it.
+	* target-insns.def (omp_simt_lane): New.
+	(omp_simt_last_lane): New.
+	(omp_simt_ordered): New.
+	(omp_simt_vote_any): New.
+	(omp_simt_xchg_bfly): New.
+	(omp_simt_xchg_idx): New.
+
+2016-11-16  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* config/mips/mips-protos.h (mips_set_text_contents_type): New
+	prototype.
+	* config/mips/mips.h (ASM_OUTPUT_BEFORE_CASE_LABEL): New macro.
+	(ASM_OUTPUT_CASE_END): Likewise.
+	* config/mips/mips.c (mips_set_text_contents_type): New function.
+	(mips16_emit_constants): Record the pool's initial label number
+	with the `consttable' insn.  Emit a `consttable_end' insn at the end.
+	(mips_final_prescan_insn): Call `mips_set_text_contents_type'
+	for `consttable' insns.
+	(mips_final_postscan_insn): Call `mips_set_text_contents_type'
+	for `consttable_end' insns.
+	* config/mips/mips.md (unspec): Add UNSPEC_CONSTTABLE_END enum value.
+	(consttable): Add operand.
+	(consttable_end): New insn.
+
+2016-11-16  Yuri Rumyantsev  <ysrumyan@gmail.com>
+
+	* params.def (PARAM_VECT_EPILOGUES_NOMASK): New.
+	* tree-if-conv.c (tree_if_conversion): Make public.
+	* * tree-if-conv.h: New file.
+	* tree-vect-data-refs.c (vect_analyze_data_ref_dependences) Avoid
+	dynamic alias checks for epilogues.
+	* tree-vect-loop-manip.c (vect_do_peeling): Return created epilog.
+	* tree-vect-loop.c: include tree-if-conv.h.
+	(new_loop_vec_info): Add zeroing orig_loop_info field.
+	(vect_analyze_loop_2): Don't try to enhance alignment for epilogues.
+	(vect_analyze_loop): Add argument ORIG_LOOP_INFO which is not NULL
+	if epilogue is vectorized, set up orig_loop_info field of loop_vinfo
+	using passed argument.
+	(vect_transform_loop): Check if created epilogue should be returned
+	for further vectorization with less vf.  If-convert epilogue if
+	required. Print vectorization success for epilogue.
+	* tree-vectorizer.c (vectorize_loops): Add epilogue vectorization
+	if it is required, pass loop_vinfo produced during vectorization of
+	loop body to vect_analyze_loop.
+	* tree-vectorizer.h (struct _loop_vec_info): Add new field
+	orig_loop_info.
+	(LOOP_VINFO_ORIG_LOOP_INFO): New.
+	(LOOP_VINFO_EPILOGUE_P): New.
+	(LOOP_VINFO_ORIG_VECT_FACTOR): New.
+	(vect_do_peeling): Change prototype to return epilogue.
+	(vect_analyze_loop): Add argument of loop_vec_info type.
+	(vect_transform_loop): Return created loop.
+
+2016-11-16  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/rs6000.c (rs6000_components_for_bb): Mark the LR
+	component as used also if LR_REGNO is a live input to the bb.
+	* df-scan.c (df_get_entry_block_def_set): Return immediately after
+	clearing the set if DF_SCAN_EMPTY_ENTRY_EXIT is set.
+	(df_get_exit_block_use_set): Ditto.
+	* df.h (df_scan_flags): New enum.
+	* shrink-wrap.c (try_shrink_wrapping_separate): Set
+	DF_SCAN_EMPTY_ENTRY_EXIT in df_scan->local_flags, and call
+	df_update_entry_block_defs and df_update_exit_block_uses
+	at the start; clear the flag and call those functions at the end.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* tree-vect-loop-manip.c (slpeel_make_loop_iterate_ntimes): Set
+	nb_iterations to the number of latch iterations rather than the
+	number of loop iterations.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* combine.c (maybe_swap_commutative_operands): New function.
+	(combine_simplify_rtx): Use it.
+	(change_zero_ext): Likewise.
+	(make_compound_operation_int): New function, split out of...
+	(make_compound_operation): ...here.  Use
+	maybe_swap_commutative_operands for both.
+
+2016-11-16  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm/arm-fpus.def (vfpv2): New FPU, currently an alias for 'vfp'.
+	(neon-vfpv3): New FPU, currently an alias for 'neon'.
+	* arm/arm-tables.opt: Regenerated.
+	* arm/t-aprofile (MULTILIB_REUSE): Add reuse rules for vfpv2 and
+	neon-vfpv3.
+	* doc/invoke.texi (ARM: -mfpu): Document new options.  Note that 'vfp'
+	and 'neon' are aliases for specific implementations.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* optabs.c (vector_compare_rtx): Add a cmp_mode parameter
+	and use it in the final call to gen_rtx_fmt_ee.
+	(expand_vec_cond_expr): Update accordingly.
+	(expand_vec_cmp_expr): Likewise.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* cprop.c (local_cprop_find_used_regs): Use df_read_modify_subreg_p.
+
+2016-11-16  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/78333
+	* gimplify.c (gimplify_function_tree): Do not instrument
+	GNU extern inline functions.
+
+2016-11-16  Martin Liska  <mliska@suse.cz>
+
+	PR sanitizer/78270
+	* gimplify.c (gimplify_switch_expr): Always save previous
+	gimplify_ctxp->live_switch_vars.
+
+2016-11-16  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* config/arc/arc.md (movb peephole2): New peephole2 to merge two
+	zero_extract operations to allow a movb to occur.
+	* testsuite/gcc.target/arc/movb-1.c: Update little endian arc results.
+	* testsuite/gcc.target/arc/movb-2.c: Likewise.
+	* testsuite/gcc.target/arc/movb-5.c: Likewise.
+	* testsuite/gcc.target/arc/movh_cl-1.c: Extend test to cover
+	little endian arc.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* expr.c (emit_group_load_1): Tighten check for whether an
+	access involves only one operand of a CONCAT.  Use extract_bit_field
+	for constants if the bit range does span the whole operand.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* rtlanal.c (rtx_addr_can_trap_p_1): Handle unknown sizes.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* tree-vect-loop.c (vect_transform_loop): Protect the updates of
+	all three iteration counts with an any_* test.  Use a single update
+	for each count.  Fix the calculation of nb_iterations_estimate.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/pdp11/pdp11.c: Include dbxout.h.
+
+2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/arc/arc.c (arc_loop_hazard): Add missing brackets.
+
+2016-11-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/78364
+	* config/arm/arm.md (*extv_reg): Restrict operands 2 and 3 to the
+	proper ranges for an SBFX instruction.
+	(extzv_t2): Likewise for UBFX.
+
+2016-11-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78348
+	* tree-loop-distribution.c (enum partition_kind): Add PKIND_MEMMOVE.
+	(generate_memcpy_builtin): Honor PKIND_MEMCPY on the partition.
+	(classify_partition): Set PKIND_MEMCPY if dependence analysis
+	revealed no dependency, PKIND_MEMMOVE otherwise.
+
+2016-11-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR sanitizer/77823
+	* ubsan.c (ubsan_build_overflow_builtin): Add DATAP argument, if
+	it points to non-NULL tree, use it instead of ubsan_create_data.
+	(instrument_si_overflow): Handle vector signed integer overflow
+	checking.
+	* ubsan.h (ubsan_build_overflow_builtin): Add DATAP argument.
+	* tree-vrp.c (simplify_internal_call_using_ranges): Punt for
+	vector IFN_UBSAN_CHECK_*.
+	* internal-fn.c (expand_addsub_overflow): Add DATAP argument,
+	pass it through to ubsan_build_overflow_builtin.
+	(expand_neg_overflow, expand_mul_overflow): Likewise.
+	(expand_vector_ubsan_overflow): New function.
+	(expand_UBSAN_CHECK_ADD, expand_UBSAN_CHECK_SUB,
+	expand_UBSAN_CHECK_MUL): Use tit for vector arithmetics.
+	(expand_arith_overflow): Adjust expand_*_overflow callers.
+
+2016-11-16  Matthias Klose  <doko@ubuntu.com>
+
+	* doc/install.texi: Remove references to java/libjava.
+
+2016-11-16  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* tree-ssa-coalesce.c (register_default_def): Remove
+	register_ssa_partition.
+	(create_outofssa_var_map): Likewise.
+	* tree-ssa-live.c (register_ssa_partition_check): Remove.
+	* tree-ssa-live.h (register_ssa_partition): Likewise.
+
+2016-11-15  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	* genattrtab.c (attr_rtx_1): Avoid allocating new rtx objects.
+	Clear ATTR_CURR_SIMPLIFIED_P for re-used binary rtx objects.
+	Use DEF_ATTR_STRING for string arguments.  Use RTL_HASH for
+	integer arguments.  Only set ATTR_PERMANENT_P on newly hashed
+	rtx when all sub-rtx are also permanent.
+	(attr_eq): Simplify.
+	(attr_copy_rtx): Remove.
+	(make_canonical, get_attr_value): Use attr_equal_p.
+	(copy_boolean): Rehash NOT.
+	(simplify_test_exp_in_temp,
+	optimize_attrs): Remove call to attr_copy_rtx.
+	(attr_alt_intersection, attr_alt_union,
+	attr_alt_complement, mk_attr_alt): Rehash EQ_ATTR_ALT.
+	(make_automaton_attrs): Use attr_eq.
+
+2016-11-15  Matthias Klose  <doko@ubuntu.com>
+
+	* doc/install.texi: Remove references to java/libjava.
+	* doc/sourcebuild.texi: Likewise.
+	* doc/invoke.texi: Likewise.
+	* doc/standards.texi: Likewise.
+
+2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* config/i386/i386.h (INCOMING_RETURN_ADDR_RTX): Use Pmode instead
+	of VOIDmode.
+	* config/ia64/ia64.h (INCOMING_RETURN_ADDR_RTX): Likewise.
+	* config/iq2000/iq2000.h (INCOMING_RETURN_ADDR_RTX): Likewise.
+	* config/m68k/m68k.h (INCOMING_RETURN_ADDR_RTX): Likewise.
+	* config/microblaze/microblaze.h (INCOMING_RETURN_ADDR_RTX): Likewise.
+	* config/mips/mips.h (INCOMING_RETURN_ADDR_RTX): Likewise.
+	* config/mn10300/mn10300.h (INCOMING_RETURN_ADDR_RTX): Likewise.
+	* config/nios2/nios2.h (INCOMING_RETURN_ADDR_RTX): Likewise.
+
+2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* dce.c (check_argument_store): Pass the size instead of
+	the memory reference.
+	(find_call_stack_args): Pass MEM_SIZE to check_argument_store.
+
+2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* alias.c (canon_rtx): Use simplify_gen_binary.
+
+2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* rtl.h (load_extend_op): Declare.
+	* rtlanal.c (load_extend_op): New function.
+	(nonzero_bits1): Use it.
+	(num_sign_bit_copies1): Likewise.
+	* cse.c (cse_insn): Likewise.
+	* fold-const.c (fold_single_bit_test): Likewise.
+	(fold_unary_loc): Likewise.
+	* fwprop.c (free_load_extend): Likewise.
+	* postreload.c (reload_cse_simplify_set): Likewise.
+	(reload_cse_simplify_operands): Likewise.
+	* combine.c (try_combine): Likewise.
+	(simplify_set): Likewise.  Remove redundant SUBREG_BYTE and
+	subreg_lowpart_p checks.
+
+2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* combine.c (simplify_shift_const_1): Use the number of bits
+	in the inner mode to determine the range of the shift.
+	When handling shifts of vectors, skip any rules that apply
+	only to scalars.
+
+2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* rtlanal.c (num_sign_bit_copies1): Calculate bitwidth after
+	handling VOIDmode.
+
+2016-11-15  Matthias Klose  <doko@ubuntu.com>
+
+	* doc/install.texi: Remove references to gcj/libjava.
+	* doc/invoke.texi: Likewise.
+
+2016-11-15  Jeff Law  <law@redhat.com>
+
+	* tree-ssa-threadbackward.c (fsm_find_thread_path): Remove unneeded
+	parameter.  Callers changed.
+	(check-subpath_and_update_thread_path): Extracted from
+	fsm_find_control_statement_thread_paths.
+	(handle_phi, handle_assignment, handle_assignment_p): Likewise.
+	(handle_phi, handle_assignment): Allow any constant node, not
+	just INTEGER_CST.
+
+2016-11-15  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc-arch.h: New file.
+	* config/arc/arc-arches.def: Likewise.
+	* config/arc/arc-cpus.def: Likewise.
+	* config/arc/arc-options.def: Likewise.
+	* config/arc/t-multilib: Likewise.
+	* config/arc/genmultilib.awk: Likewise.
+	* config/arc/genoptions.awk: Likewise.
+	* config/arc/arc-tables.opt: Likewise.
+	* config/arc/driver-arc.c: Likewise.
+	* testsuite/gcc.target/arc/nps400-cpu-flag.c: Likewise.
+	* common/config/arc/arc-common.c (arc_handle_option): Trace
+	toggled options.
+	* config.gcc (arc*-*-*): Add arc-tables.opt to arc's extra
+	options; check for supported cpu against arc-cpus.def file.
+	(arc*-*-elf*, arc*-*-linux-uclibc*): Use new make fragment; define
+	TARGET_CPU_BUILD macro; add driver-arc.o as an extra object.
+	* config/arc/arc-c.def: Add emacs local variables.
+	* config/arc/arc-opts.h (processor_type): Use arc-cpus.def file.
+	(FPU_FPUS, FPU_FPUD, FPU_FPUDA, FPU_FPUDA_DIV, FPU_FPUDA_FMA)
+	(FPU_FPUDA_ALL, FPU_FPUS_DIV, FPU_FPUS_FMA, FPU_FPUS_ALL)
+	(FPU_FPUD_DIV, FPU_FPUD_FMA, FPU_FPUD_ALL): New defines.
+	(DEFAULT_arc_fpu_build): Define.
+	(DEFAULT_arc_mpy_option): Define.
+	* config/arc/arc-protos.h (arc_init): Delete.
+	* config/arc/arc.c (arc_cpu_name): New variable.
+	(arc_selected_cpu, arc_selected_arch, arc_arcem, arc_archs)
+	(arc_arc700, arc_arc600, arc_arc601): New variable.
+	(arc_init): Add static; remove selection of default tune value,
+	cleanup obsolete error messages.
+	(arc_override_options): Make use of .def files for selecting the
+	right cpu and option configurations.
+	* config/arc/arc.h (stdbool.h): Include.
+	(TARGET_CPU_DEFAULT): Define.
+	(CPP_SPEC): Remove mcpu=NPS400 handling.
+	(arc_cpu_to_as): Declare.
+	(EXTRA_SPEC_FUNCTIONS): Define.
+	(OPTION_DEFAULT_SPECS): Likewise.
+	(ASM_DEFAULT): Remove.
+	(ASM_SPEC): Use arc_cpu_to_as.
+	(DRIVER_SELF_SPECS): Remove deprecated options.
+	(arc_base_cpu):	Declare.
+	(TARGET_ARC600, TARGET_ARC601, TARGET_ARC700, TARGET_EM)
+	(TARGET_HS, TARGET_V2, TARGET_ARC600): Make them use arc_base_cpu
+	variable.
+	(MULTILIB_DEFAULTS): Use ARC_MULTILIB_CPU_DEFAULT.
+	* config/arc/arc.md (attr_cpu): Remove.
+	* config/arc/arc.opt (mno-mpy): Deprecate.
+	(mcpu=ARC600, mcpu=ARC601, mcpu=ARC700, mcpu=NPS400, mcpu=ARCEM)
+	(mcpu=ARCHS): Remove.
+	(mcrc, mdsp-packa, mdvbf, mmac-d16, mmac-24, mtelephony, mrtsc):
+	Deprecate.
+	(mbarrel_shifte, mspfp_, mdpfp_, mdsp_pack, mmac_): Remove.
+	(arc_fpu): Use new defines.
+	(mpy-option): Change to use numeric or string like inputs.
+	* config/arc/t-arc (driver-arc.o): New target.
+	(arc-cpus, t-multilib, arc-tables.opt): Likewise.
+	* config/arc/t-arc-newlib: Delete.
+	* config/arc/t-arc-uClibc: Renamed to t-uClibc.
+	* doc/invoke.texi (ARC): Update arc options.
+
+2016-11-15  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* config/mips/mips.c (mips16_emit_constants): Emit `consttable'
+	insn at the beginning of the constant pool.
+	(mips_insert_insn_pseudos): New function.
+	(mips_machine_reorg2): Call it.
+	* config/mips/mips.md (unspec): Add UNSPEC_CONSTTABLE and
+	UNSPEC_INSN_PSEUDO enum values.
+	(insn_pseudo, consttable): New insns.
+
+2016-11-15  Michael Matz  <matz@suse.de>
+
+	PR missed-optimization/77881
+	* combine.c (simplify_comparison): Remove useless subregs
+	also inside the loop, not just after it.
+	(make_compound_operation): Recognize some subregs as being
+	masking as well.
+
+2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* dwarf2out.c (mem_loc_descriptor): Fix GET_MODE_CLASS/
+	GET_MODE_SIZE typo.
+
+2016-11-14  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000.c (rs6000_expand_vector_set): Add support
+	for using xxinsertw and vinsert{b,h} on ISA 3.0.
+
+	* config/rs6000/vsx.md (vsx_extract_<mode>): Update comment.
+	(vsx_set_<mode>_p9): New insn to generate xxinsertw and
+	vinsert{b,h} on ISA 3.0.
+
+2016-11-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* tree-ssa-math-opts.c (find_bswap_or_nop): Zero out bytes in cmpxchg
+	and cmpnop in two steps: first the ones not accessed in original gimple
+	expression in a endian independent way and then the ones not accessed
+	in the final result in an endian-specific way.
+	(bswap_replace): Stop doing big endian adjustment.
+
+2016-11-14  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (*andndi3_doubleword): Merge operand constraints.
+	(*ashl<mode>3_doubleword): Ditto.
+
+2016-11-14  Martin Liska  <mliska@suse.cz>
+
+	* tree-ssa-dse.c (dse_optimize_stmt): Remove quotes and extra new line.
+
+2016-11-14  Prasad Ghangal  <prasad.ghangal@gmail.com>
+	    Richard Biener  <rguenther@suse.de>
+
+	* doc/invoke.texi (fgimple): Document.
+	* dumpfile.h (TDF_GIMPLE): Add.
+	* dumpfile.c (dump_options): Add gimple.
+	* gimple-pretty-print.c (dump_gimple_switch): Adjust dump
+	for TDF_GIMPLE.
+	(dump_gimple_label): Likewise.
+	(dump_gimple_phi): Likewise.
+	(dump_gimple_bb_header): Likewise.
+	(dump_phi_nodes): Likewise.
+	(pp_cfg_jump): Likewise.  Pass in dump flags.
+	(dump_implicit_edges): Adjust.
+	* passes.c (pass_init_dump_file): Do not dump function header
+	for TDF_GIMPLE.
+	* tree-cfg.c (dump_function_to_file): Dump function return type
+	and __GIMPLE keyword for TDF_GIMPLE.  Change guard for dumping
+	GIMPLE stmts.
+	* tree-pretty-print.c (dump_decl_name): Adjust dump for TDF_GIMPLE.
+	(dump_generic_node): Likewise.
+	* function.h (struct function): Add pass_startwith member.
+	* passes.c (execute_one_pass): Implement startwith.
+	* tree-ssanames.c (make_ssa_name_fn): New argument, check for version
+	and assign proper version for parsed ssa names.
+	* tree-ssanames.h (make_ssa_name_fn): Add new argument to the function.
+	* internal-fn.c (expand_PHI): New function.
+	* internal-fn.h (expand_PHI): Declared here.
+	* internal-fn.def: New defination for PHI.
+	* tree-cfg.c (lower_phi_internal_fn): New function.
+	(build_gimple_cfg): Call it.
+	(verify_gimple_call): Condition for passing label as arg in internal
+	function PHI.
+	* tree-into-ssa.c (rewrite_add_phi_arguments): Handle already
+	present PHIs with arguments.
+
+2016-11-14  Martin Liska  <mliska@suse.cz>
+
+	PR bootstrap/78069
+	* common.opt: Add prefer-atomic as a new enum value for
+	-fprofile-update.
+	* coretypes.h: Likewise.
+	* doc/invoke.texi: Document the new option value.
+	* gcc.c: Replace atomic with prefer-atomic.  Remove warning.
+	* tree-profile.c (tree_profiling): Select default value
+	of -fprofile-update when 'prefer-atomic' is selected.
+
+2016-11-14  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/arm/cortex-a57.md (cortex_a57_alu): Move extend here, bfm...
+	(cortex_a57_alu_shift): ...here.
+
+2016-11-14  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3)
+	Use bfx attribute.
+	(aarch64_lshr_sisd_or_int_<mode>3): Likewise.
+	(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
+	(<optab>si3_insn_uxtw): Likewise.
+	(<optab><mode>3_insn): Likewise.
+	(<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>): Likewise.
+	(zero_extend<GPI:mode>_lshr<SHORT:mode>): Likewise.
+	(extend<GPI:mode>_ashr<SHORT:mode>): Likewise.
+	(<optab><mode>): Likewise.
+	(insv<mode>): Likewise.
+	(andim_ashift<mode>_bfiz): Likewise.
+	* config/aarch64/thunderx.md (thunderx_shift): Add bfx.
+	* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
+	* config/arm/cortex-a57.md (cortex_a57_alu): Add bfx.
+	* config/arm/exynos-m1.md (exynos_m1_alu): Add bfx.
+	(exynos_m1_alu_p): Likewise.
+	* config/arm/types.md: Add bfx.
+	* config/arm/xgene1.md (xgene1_bfm): Add bfx.
+
+2016-11-14  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64.c (cortexa57_vector_cost):
+	Change vec_stmt_cost, vec_align_load_cost and vec_unalign_load_cost.
+
+2016-11-14  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78312
+	* gimple-ssa-backprop.c (backprop::prepare_change): Reset
+	flow-sensitive info.
+
+2016-11-14  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/78093
+	* doc/invoke.texi (AVR Options) [-mabsdata]: Document new option.
+	* config/avr/avr.opt (-mabsdata): New option.
+	* config/avr/avr-arch.h (avr_device_specific_features):	Add AVR_ISA_LDS.
+	* config/avr/avr.c (avr_encode_section_info) [AVR_TINY]: If
+	-mabsdata & symbol is not progmem, tag as AVR_SYMBOL_FLAG_TINY_ABSDATA.
+	* config/avr/avr-mcus.def (attiny4/5/9/10/20): Use AVR_ISA_LDS.
+	* config/avr/gen-avr-mmcu-specs.c (print_mcu): Print cc1_absdata
+	spec depending on AVR_ISA_LDS.
+	* config/avr/specs.h (CC1_SPEC): Enhanced by cc1_absdata spec.
+
+2016-11-13  Jakub Jelinek  <jakub@redhat.com>
+
+	* match.pd: Don't try to compare addresses of variables with
+	DECL_VALUE_EXPR.
+
+2016-11-13  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* ipa-cp.c (ipa_get_jf_pass_through_result): Skip unary expressions.
+	(propagate_vr_accross_jump_function): Handle unary expressions.
+	* ipa-prop.c (ipa_set_jf_unary_pass_through): New.
+	(load_from_param_1): New.
+	(load_from_unmodified_param): Factor common part into load_from_param_1.
+	(load_from_param): New.
+	(compute_complex_assign_jump_func): Handle unary expressions.
+	(update_jump_functions_after_inlining): Likewise.
+	(ipa_write_jump_function): Likewise.
+	(ipa_read_jump_function): Likewise.
+
+2016-11-13  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR c/35503
+	* doc/invoke.texi: Document Wrestrict.
+	* pretty-print.c (pp_format): Add case for "Z" specifier.
+	(test_pp_format): Test "Z" specifier.
+
+2016-11-13  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* ipa-icf.c (sem_function::merge): Do not create a wrapper also if the
+	original function needs a static chain.
+
+2016-11-13  David Edelsohn  <dje.gcc@gmail.com>
+
+	PR target/78336
+	* config/rs6000/rs6000.c (rs6000_asm_weaken_decl): Protect
+	ASM_OUTPUT_DEF.
+
+2016-11-12  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/77957
+	* config/rs6000/rs6000.c (rs6000_output_function_epilogue): Don't
+	return early if !optional_tbtab.
+
+2016-11-11  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR rtl-optimization/59461
+	* doc/rtl.texi (paradoxical subregs): Add missing word.
+	* combine.c (reg_nonzero_bits_for_combine): Do not discard results
+	in modes with precision larger than that of last_set_mode.
+	* rtlanal.c (nonzero_bits1) <SUBREG>: If WORD_REGISTER_OPERATIONS is
+	set and LOAD_EXTEND_OP is appropriate, propagate results from inner
+	REGs to paradoxical SUBREGs.
+	(num_sign_bit_copies1) <SUBREG>: Likewise.  Check that the mode is not
+	larger than a word before invoking LOAD_EXTEND_OP on it.
+
+2016-11-11  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/78243
+	* config/rs6000/vsx.md (vsx_extract_<mode>_p9): Correct the
+	element order for little endian ordering.
+
+	* config/rs6000/altivec.md (reduc_plus_scal_<mode>): Use
+	VECTOR_ELT_ORDER_BIG and not BYTES_BIG_ENDIAN to adjust element
+	number.
+
+2016-11-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78310
+	* config/i386/i386.md (rotate to rotatex splitter): Avoid overflow
+	when calculating operand 2.
+	(rotate to rotatex zext splitter): Ditto.
+
+2016-11-11  Jeff Law  <law@redhat.com>
+
+	* gimple-ssa-isolate-paths.c (is_divmod_with_given_divisor): New
+	function.
+	(stmt_uses_name_in_undefined_way): New function, extracted from
+	find_implicit_erroneous_behavior and extended for div/mod case.
+	(stmt_uses_0_or_null_in_undefined_way): New function, extracted from
+	find_explicit_erroneous_behavior and extended for div/mod case.
+	(find_implicit_erroneous_behavior): Use new helper function.
+	(find_explicit_erroneous_behavior): Use new helper function.
+
+2016-11-11  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/71575
+	* graphite-isl-ast-to-gimple.c (copy_cond_phi_nodes): Remove
+	bogus assert.
+
+2016-11-11  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/78295
+	* tree-ssa-uninit.c (warn_uninitialized_vars): Do not warn
+	about uninitialized destination arg of BIT_INSERT_EXPR.
+
+2016-11-10  Sandra Loosemore  <sandra@codesourcery.com>
+
+	PR c/37998
+	* doc/invoke.texi (Code Gen Options) [-fno-common]: Use correct
+	terminology.  Expand to remove ambiguity.
+
+2016-11-10  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78232
+	* combine.c (try_combine): Add a big comment about why reusing i2dest
+	is undesirable.
+	(change_zero_ext): Do not call simplify_gen_binary, do the
+	simplifications manually.
+
+2016-11-10  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If ISA 3.0,
+	enable HImode and QImode to go in vector registers by default if
+	the -mvsx-small-integer option is enabled.
+	(rs6000_secondary_reload_simple_move): Likewise.
+	(rs6000_preferred_reload_class): Don't force integer constants to
+	be loaded into vector registers that we can easily make into
+	memory (or being created in the GPRs and moved over with direct move).
+	* config/rs6000/vsx.md (UNSPEC_P9_MEMORY): Delete, no longer used.
+	(vsx_extract_<mode>): Rework V4SImode, V8HImode, and V16QImode
+	vector extraction on ISA 3.0 when the scalar integer can be
+	allocated in vector registers.  Generate the VEC_SELECT directy,
+	and don't use UNSPEC's to avoid having the scalar type in a vector
+	register.  Make the expander target registers, and let the
+	combiner fold in results storing to memory, if the machine
+	supports stores.
+	(vsx_extract_<mode>_di): Likewise.
+	(vsx_extract_<mode>_p9): Likewise.
+	(vsx_extract_<mode>_di_p9): Likewise.
+	(vsx_extract_<mode>_store_p9): Likewise.
+	(vsx_extract_si): Likewise.
+	(vsx_extract_<mode>_p8): Likewise.
+	(p9_lxsi<wd>zx): Delete, no longer used.
+	(p9_stxsi<wd>x): Likewise.
+	* config/rs6000/rs6000.md (INT_ISA3): New mode iterator for
+	integers in vector registers for ISA 3.0.
+	(QHI): Update comment.
+	(zero_extendqi<mode>2): Add support for ISA 3.0 scalar load or
+	vector extract instructions in sign/zero extend.
+	(zero_extendhi<mode>): Likewise.
+	(extendqi<mode>): Likewise.
+	(extendhi<mode>2): Likewise.
+	(HImode splitter for load/sign extend in vector register): Likewise.
+	(float<QHI:mode><FP_ISA3:mode>2): Eliminate old method of
+	optimizing floating point conversions to/from small data types and
+	rewrite it to support QImode/HImode being allowed in vector
+	registers on ISA 3.0.
+	(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
+	(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
+	(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
+	(fix_trunc<SFDF:mode><QHI:mode>2): Likewise.
+	(fix_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
+	(fixuns_trunc<SFDF:mode><QHI:mode>2): Likewise.
+	(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
+	VSPLITISW on ISA 2.07.
+	(movhi_internal): Combine movhi_internal and movqi_internal into
+	one mov<mode>_internal with an iterator.  Add support for QImode
+	and HImode being allowed in vector registers.  Make large number
+	of attributes and constraints easier to read.
+	(movqi_internal): Likewise.
+	(mov<mode>_internal): Likewise.
+	(movdi_internal64): Fix constraint to allow loading -16..15 with
+	VSPLITISW on ISA 2.07.
+	(integer XXSPLTIB splitter): Add support for QI, HI, and SImode as
+	well as DImode.
+
+2016-11-10  Pat Haugen  <pthaugen@us.ibm.com>
+
+	PR rtl-optimization/78241
+	* loop-unroll.c (unroll_loop_runtime_iterations): Don't adjust 'niter',
+	but emit initial peel copy if niter expr is not reliable.
+
+2016-11-10  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* dwarf2cfi.c (dump_cfi_row): Add forward declaration.
+	(maybe_record_trace_start): If the CFI is different on the new and
+	old paths, print out both to the dump file before ICEing.
+
+2016-11-10  Vladimir Makarov  <vmakarov@redhat.com>
+
+	* target.def (additional_allocno_class_p): New.
+	* hooks.h (hook_bool_reg_class_t_false): New prototype.
+	* hooks.c (hook_bool_reg_class_t_false): New.
+	* ira.c (setup_allocno_and_important_classes): Use the new hook.
+	* doc/tm.texi.in (TARGET_ADDITIONAL_ALLOCNO_CLASS_P): Add it.
+	* doc/tm.texi: Update.
+
+2016-11-10  Jason Merrill  <jason@redhat.com>
+
+	* gengtype.c (new_structure): Append to structures list.
+	(find_structure): Likewise.
+
+2016-11-10  Jim Wilson  <jim.wilson@linaro.org>
+
+	* tree-loop-distribution.c (pg_add_dependence_edges): Return 2 if
+	this_dir is 2.  Check for this_dir non-zero before dir != this_dir
+	check.
+
+2016-11-10  Jakub Jelinek  <jakub@redhat.com>
+
+	* omp-low.c (lower_omp_target): Fix up argument to is_reference.
+	(expand_omp_ordered_sink): Handle TREE_PURPOSE of deps being
+	TRUNC_DIV_EXPR.
+	* gimplify.c (gimplify_scan_omp_clauses): Likewise.  Set
+	ctx->target_map_scalars_firstprivate on OMP_TARGET even for Fortran.
+	Remove omp_no_lastprivate callers.  Propagate lastprivate on combined
+	teams distribute parallel for simd even to distribute and teams
+	construct.  For OMP_CLAUSE_DEPEND add missing break at the end of
+	OMP_CLAUSE_DEPEND_SINK case.
+	(omp_notice_variable): Use lang_hooks.decls.omp_scalar_p.
+	(omp_no_lastprivate): Removed.
+	(gimplify_adjust_omp_clauses): Remove omp_no_lastprivate callers.
+	(gimplify_omp_for): Likewise.
+	(computable_teams_clause): Fail for automatic vars from current
+	function not yet seen in bind expr.
+	* langhooks.c (lhd_omp_scalar_p): New function.
+	* langhooks.h (struct lang_hooks_for_decls): Add omp_scalar_p.
+	* varpool.c (varpool_node::get_create): Set node->offloading
+	even for DECL_EXTERNAL decls.
+	* langhooks-def.h (lhd_omp_scalar_p): New prototype.
+	(LANG_HOOKS_OMP_SCALAR_P): Define.
+	(LANG_HOOKS_DECLS): Use it.
+
+2016-11-10  Martin Liska  <mliska@suse.cz>
+
+	PR sanitizer/78270
+	* gimplify.c (gimplify_switch_expr): Create live_switch_vars
+	only when SWITCH_BODY is a BIND_EXPR.
+
+2016-11-10  Pierre-Marie de Rodat  <derodat@adacore.com>
+
+	PR debug/78112
+	* dwarf2out.c (dwarf2out_early_global_decl): Call dwarf2out_decl
+	on the context only when it has no DIE yet.
+
+2016-11-10  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h (target_cpus): Delete.
+	* arm-opts.h (enum processor_type): Prefix entires with TARGET_CPU_.
+	* arm.c (all_cores): Prefix IDENT with TARGET_CPU_.
+	(all_architectures): Likewise.
+	(arm_option_override): Adjust use of CPU enums.
+	(arm_sched_reorder): Likewise.
+	* vfp.md (movdi_vfp, movdi_vfp_cortexa8): Likewise.
+	* arm.opt (mcpu, mtune): Adjust use of CPU enums.
+	* arm/genopt.sh (processor_type): Prefix enumeration entries with
+	TARGET_CPU_.
+	* arm-tables.opt: Regenerated.
+
+2016-11-10  Siddhesh Poyarekar  <siddhesh.poyarekar@linaro.org>
+
+	* config/aarch64/aarch64-cores.def (qdf24xx): Update part number.
+	(falkor): New core.
+	* config/aarch64/aarch64-tune.md: Regenerated.
+	* config/arm/arm-cores.def (falkor): New core.
+	* config/arm/arm-tables.opt: Regenerated.
+	* config/arm/arm-tune.md: Regenerated.
+	* config/arm/bpabi.h (BE8_LINK_SPEC): Add falkor support.
+	* config/arm/t-aprofile (MULTILIB_MATCHES): Likewise.
+	* doc/invoke.texi (AArch64 Options/-mtune): Document it.
+	(ARM Options/-mtune): Likewise.
+
+2016-11-10  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	Revert
+	2016-11-09  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* ipa-cp.c (ipa_get_jf_pass_through_result): Handle unary expressions.
+	(propagate_vr_accross_jump_function): Likewise.
+	* ipa-prop.c (ipa_set_jf_unary_pass_through): New.
+	(load_from_param_1): New.
+	(load_from_unmodified_param): Factor common part into load_from_param_1.
+	(load_from_param): New.
+	(compute_complex_assign_jump_func): Handle unary expressions.
+	(ipa_write_jump_function): Likewise.
+	(ipa_read_jump_function): Likewise.
+
+2016-11-09  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* simplify-rtx.c (simplify_binary_operation_1): Simplify
+	(xor (and (xor A B) C) B) to (ior (and A C) (and B ~C)) and
+	(xor (and (xor A B) C) A) to (ior (and A ~C) (and B C)) if C
+	is a const_int.
+
+2016-11-09  David Malcolm  <dmalcolm@redhat.com>
+
+	* print-rtl-function.c: Include varasm.h.
+	(print_any_param_name): New function.
+	(print_param): New function.
+	(print_rtx_function): Call print_param for each argument.
+	* print-rtl.c (rtx_writer::finish_directive): New function.
+	* print-rtl.h (rtx_writer::finish_directive): New decl.
+
+2016-11-09  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78262
+	* config/i386/i386.md (*<shift_insn><mode>3_doubleword): Mark
+	operand 0 as earlyclobber.
+	(*ashl<mode>3_doubleword): Ditto for all operand 0 alternatives.
+
+2016-11-09  Martin Liska  <mliska@suse.cz>
+
+	* fold-const-call.c (fold_const_call): Fix up type of s0 and s1.
+
+2016-11-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/77718
+	* builtins.c (expand_builtin_memcmp): Formatting fix.
+
+	* flag-types.h (enum sanitize_code): Add SANITIZE_SHIFT_BASE
+	and SANITIZE_SHIFT_EXPONENT, change SANITIZE_SHIFT to bitwise
+	or of them, renumber other enumerators.
+	* opts.c (sanitizer_opts): Add shift-base and shift-exponent.
+	* doc/invoke.texi: Document -fsanitize=shift-base and
+	-fsanitize-shift-exponent, document -fsanitize=shift as
+	having those 2 suboptions.
+
+2016-11-09  Richard Biener  <rguenther@suse.de>
+
+	* fold-const.c (tree_swap_operands_p): Remove unused arg.
+	* fold-const.c (tree_swap_operands_p): Likewise.
+	(fold_binary_loc): Adjust.
+	(fold_ternary_loc): Likewise.
+	* genmatch.c (dt_operand::gen_gimple_exp): Likewise.
+	* gimple-fold.c (fold_stmt_1): Likewise.
+	* gimple-match-head.c (gimple_resimplify2): Likewise.
+	(gimple_resimplify3): Likewise.
+	(gimple_simplify): Likewise.
+	* tree-ssa-dom.c (record_equality): Likewise.
+	* tree-ssa-reassoc.c (optimize_range_tests_var_bound): Likewise.
+	* tree-ssa-sccvn.c (vn_nary_op_compute_hash): Likewise.
+	* tree-ssa-threadedge.c (simplify_control_stmt_condition_1): Likewise.
+
+2016-11-09  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-dom.c (canonicalize_comparison): Remove.
+	(optimize_stmt): Remove redundant pre-propagation canonicalization
+	of comparison operand order.
+
+2016-11-09  Martin Liska  <mliska@suse.cz>
+
+	* fold-const-call.c (fold_const_call): Fix the folding.
+
+2016-11-09  Richard Biener  <rguenther@suse.de>
+
+	* common.opt (flag_evaluation_order): Remove.
+	* expr.c (expand_operands): Remove code guarded by
+	flag_evaluation_order.
+	* fold-const.c (reorder_operands_p): Remove, it always returns
+	true.
+	(negate_expr_p): Remove calls to reorder_operands_p.
+	(fold_negate_expr): Likewise.
+	(tree_swap_operands_p): Likewise.
+	(fold_binary_loc): Likewise.
+
+2016-11-09  Andreas Schwab  <schwab@suse.de>
+
+	PR target/78254
+	* config/m68k/m68k.md: Reject out-of-range bit pos in bit-fields
+	insns operating on a register.
+
+2016-11-09  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78007
+	* tree-vect-stmts.c (vectorizable_bswap): New function.
+	(vectorizable_call): Call vectorizable_bswap for
+	BUILT_IN_BSWAP{16,32,64} if arguments are not promoted.
+
+2016-11-09  Richard Biener  <rguenther@suse.de>
+
+	* tree-vect-data-refs.c (vect_compute_data_ref_alignment):
+	Look at the DR_BASE_ADDRESS object for forcing alignment.
+
+2016-11-09  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* ipa-cp.c (ipa_get_jf_pass_through_result): Handle unary expressions.
+	(propagate_vr_accross_jump_function): Likewise.
+	* ipa-prop.c (ipa_set_jf_unary_pass_through): New.
+	(load_from_param_1): New.
+	(load_from_unmodified_param): Factor common part into load_from_param_1.
+	(load_from_param): New.
+	(compute_complex_assign_jump_func): Handle unary expressions.
+	(ipa_write_jump_function): Likewise.
+	(ipa_read_jump_function): Likewise.
+
+2016-11-09  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	PR ipa/78121
+	* ipa-cp.c (propagate_vr_accross_jump_function): Pass param type.
+	Also fold constant passed as argument while computing value range.
+	(propagate_constants_accross_call): Pass param type.
+	* ipa-prop.c: export ipa_get_callee_param_type.
+	* ipa-prop.h: export ipa_get_callee_param_type.
+
+2016-11-09  Maxim Ostapenko  <m.ostapenko@samsung.com>
+
+	* asan.h (asan_intercepted_p): Handle BUILT_IN_STRCSPN,
+	BUILT_IN_STRPBRK, BUILT_IN_STRSPN and BUILT_IN_STRSTR.
+
+2016-11-09  Maxim Ostapenko  <m.ostapenko@samsung.com>
+
+	* asan.h (ASAN_STACK_MAGIC_PARTIAL): Remove.
+	* asan.c (ASAN_STACK_MAGIC_PARTIAL): Replace with
+	ASAN_STACK_MAGIC_MIDDLE.
+	(asan_global_struct): Increase the size of fields.
+	(asan_add_global): Add new field constructor.
+	* sanitizer.def (__asan_version_mismatch_check_v6): Replace with
+	__asan_version_mismatch_check_v8.
+
+2016-11-08  David Edelsohn  <dje.gcc@gmail.com>
+
+	* dwarf2asm.c (USE_LINKONCE_INDIRECT): Test XCOFF_DEBUGGING_INFO
+	at runtime.
+
+2016-11-08  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/70799
+	* config/i386/i386.c (dimode_scalar_to_vector_candidate_p):
+	Handle ASHIFT and LSHIFTRT.
+	(dimode_scalar_chain::compute_convert_gain): Ditto.
+	(dimode_scalar_chain::convert_insn): Ditto.
+
+2016-11-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gimple-ssa-store-merging.c: Include selftest.h
+	(verify_array_eq): New function.
+	(verify_shift_bytes_in_array): Likewise.
+	(verify_shift_bytes_in_array_right): Likewise.
+	(verify_clear_bit_region): Likewise.
+	(verify_clear_bit_region_be): Likewise.
+	(store_merging_c_tests): Likewise.
+	* selftest.h (store_merging_c_tests): Declare prototype.
+	* selftest-run-tests.c (selftest::run_tests): Run
+	store_merging_c_tests.
+
+2016-11-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/arm/arm.opt (mold-rtx-costs): Delete.
+	(mnew-generic-costs): Delete.
+	* config/arm/arm-protos.h (struct tune_params): Delete rtx_costs field.
+	* config/arm/arm.c (arm_rtx_costs_1): Delete.
+	(arm_size_rtx_costs): Likewise.
+	(arm_slowmul_rtx_costs): Likewise.
+	(arm_fastmul_rtx_costs): Likewise.
+	(arm_xscale_rtx_costs): Likewise.
+	(arm_9e_rtx_costs): Likewise.
+	(arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune,
+	arm_xscale_tune, arm_9e_tune, arm_v6t2_tune, arm_cortex_tune,
+	arm_cortex_a8_tune, arm_cortex_a7_tune, arm_cortex_a15_tune,
+	arm_cortex_a53_tune, arm_cortex_a57_tune, arm_cortex_a9_tune,
+	arm_cortex_a12_tune, arm_v7m_tune, arm_v6m_tune, arm_fa726te_tune
+	arm_cortex_a5_tune, arm_xgene1_tune, arm_marvell_pj4_tune,
+	arm_cortex_a35_tune, arm_exynosm1_tune, arm_cortex_a73_tune,
+	arm_cortex_m7_tune):
+	Delete rtx_costs field.
+	(arm_new_rtx_costs): Rename to...
+	(arm_rtx_costs_internal): ... This.
+	(arm_rtx_costs): Remove old way of doing rtx costs.
+
+2016-11-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/arm/arm.c (arm_slowmul_tune): Use generic_extra_costs.
+	(arm_fastmul_tune): Likewise.
+	(arm_strongarm_tune): Likewise.
+	(arm_xscale_tune): Likewise.
+	(arm_9e_tune): Likewise.
+	(arm_marvell_pj4_tune): Likewise.
+	(arm_v6t2_tune): Likewise.
+	(arm_v6m_tune): Likewise.
+	(arm_fa726te_tune): Likewise.
+
+2016-11-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR tree-optimization/78234
+	* gimple-ssa-store-merging.c (clear_bit_region): Fix off-by-one error
+	in start != 0 case.
+
+2016-11-08  Martin Liska  <mliska@suse.cz>
+
+	PR testsuite/78242
+	* dbgcnt.def: Add new debug counter asan_use_after_scope.
+	* gimplify.c (gimplify_decl_expr): Do not sanitize vars
+	with a value expr.  Do not add artificial variables to
+	live_switch_vars.  Use the debug counter.
+	(gimplify_target_expr): Use the debug counter.
+	* internal-fn.def: Remove ECF_TM_PURE from ASAN_MARK builtin.
+	* sanitizer.def: Set ATTR_NOTHROW_LEAF_LIST to
+	BUILT_IN_ASAN_CLOBBER_N and BUILT_IN_ASAN_UNCLOBBER_N.
+
+2016-11-08  Richard Biener  <rguenther@suse.de>
+
+	* tree-vect-stmts.c (get_group_load_store_type): If the
+	access is aligned do not trigger peeling for gaps.
+	* tree-vect-data-refs.c (vect_compute_data_ref_alignment): Do not
+	force alignment of vars with DECL_USER_ALIGN.
+
+2016-11-08  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/t-aarch64 (aarch64-c.o): Depend on TARGET_H.
+
+2016-11-08  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78205
+	* tree-vect-stmts.c (vectorizable_load): Move check whether
+	we may run into gaps when BB vectorizing SLP permutations ...
+	* tree-vect-slp.c (vect_supported_load_permutation_p): ...
+	here where we can do a more precise check.
+
+2016-11-08  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78224
+	* tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
+	Split the fallthru edge in case its successor may have PHIs.
+	Do not free dominance info.
+
+2016-11-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/78229
+	* config/i386/i386.c (ix86_gimple_fold_builtin): Do not adjust
+	EH info even for bzhi and pdep/pext.
+
+2016-11-07  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* config.gcc (powerpc*-*-*, rs6000*-*-*): Remove setting of
+	INCLUDE_EXTRA_SPEC for Advance Toolchain builds.
+
+2016-11-07  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/rs6000.md (div<mode>3): Expand using rs6000_emit_swdiv
+	if appropriate.
+	* config/rs6000/vector.md (div<mode>3): Ditto.
+
+2016-11-07  David Edelsohn  <dje.gcc@gmail.com>
+
+	* configure.ac (.hidden): Change to conftest_s string. Provide string
+	for AIX assembler.
+	(gcc_cv_ld_hidden): Yes for AIX.
+	* configure: Regenerate.
+
+	* dwarf2asm.c (USE_LINKONCE_INDIRECT): Don't set for AIX (XCOFF).
+
+	* config/rs6000/rs6000-protos.h (rs6000_asm_weaken_decl): Declare
+	(rs6000_xcoff_asm_output_aligned_decl_common): Declare.
+	* config/rs6000/xcoff.h (TARGET_ASM_GLOBALIZE_DECL_NAME): Define.
+	(ASM_OUTPUT_ALIGNED_DECL_COMMON): Define.
+	(ASM_OUTPUT_ALIGNED_COMMON): Delete.
+	* config/rs6000/rs6000.c (rs6000_init_builtins): Change clog rename
+	from #if to if.
+	(rs6000_xcoff_visibility): New.
+	(rs6000_xcoff_declare_function_name): Add visibility support.
+	(rs6000_xcoff_asm_globalize_decl_name): New.
+	(rs6000_xcoff_asm_output_aligned_decl_common): New.
+	(rs6000_asm_weaken_decl): New.
+	(rs6000_code_end): Disable HIDDEN_LINKONCE on XCOFF.
+	config/rs6000/rs6000.h (ASM_WEAKEN_DECL): Change definition to
+	reference function.
+
+2016-11-07  Jack Howarth  <howarth.at.gcc@gmail.com>
+
+	PR driver/78206
+	* incpath.c (remove_dup): Also silently ignore EPERM.
+
+2016-11-07  Martin Jambor  <mjambor@suse.cz>
+
+	* tree.c (verify_type_variant): Use pointer comparison to check that
+	TYPE_SIZE_UNIT match.
+
+2016-11-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/77834
+	* dse.c (dse_step5): Call scan_reads even if just
+	insn_info->frame_read.  Improve and fix dump file messages.
+
+	PR target/78227
+	* config/i386/i386.c (ix86_expand_sse_cmp): Force dest into
+	cmp_mode argument even for -O0 if cmp_mode != mode and maskcmp.
+
+2016-11-07  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR middle-end/35691
+	* match.pd: Add following two patterns:
+	(x == 0 & y == 0) -> (x | typeof(x)(y)) == 0.
+	(x != 0 | y != 0) -> (x | typeof(x)(y)) != 0.
+
+2016-11-07  Bernd Schmidt  <bschmidt@redhat.com>
+
+	* emit-rtl.c (emit_copy_of_insn_after): Duplicate notes in order.
+	* sel-sched-ir.c (create_copy_of_insn_rtx): Likewise.
+	* rtl.h (duplicate_reg_notes): Declare.
+	* rtlanal.c (duplicate_reg_note): New function.
+
+	PR rtl-optimization/77309
+	* combine.c (make_compound_operation): Allow EQ for IN_CODE, and
+	don't assume an equality comparison for plain COMPARE.
+	(simplify_comparison): Pass a more accurate code to
+	make_compound_operation.
+
+2016-11-07  Pat Haugen  <pthaugen@us.ibm.com>
+
+	* target.def (compute_pressure_classes): New target hook.
+	* doc/tm.texi.in: Document it.
+	* doc/tm.texi: Regenerate.
+	* ira.c (setup_pressure_classes): Call target hook if defined.
+
+2016-11-07  David Malcolm  <dmalcolm@redhat.com>
+
+	* print-rtl.c (rtx_writer::operand_has_default_value_p): New
+	method.
+	(rtx_writer::print_rtx): In compact mode, omit trailing operands
+	that have the default values.
+	* print-rtl.h (rtx_writer::operand_has_default_value_p): New
+	method.
+	* rtl-tests.c (selftest::test_dumping_insns): Remove empty
+	label string from expected dump.
+	(seltest::test_uncond_jump): Remove trailing "(nil)" for REG_NOTES
+	from expected dump.
+
+2016-11-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/77834
+	* alias.c (nonoverlapping_memrefs_p): If one decl is
+	FUNCTION_DECL or LABEL_DECL and the other is not, return 1.
+
+2016-11-07  Richard Biener  <rguenther@suse.de>
+
+	PR target/78229
+	* config/i386/i386.c (ix86_gimple_fold_builtin): Do not adjust
+	EH info.
+
+2016-11-07  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78218
+	* gimple-ssa-store-merging.c
+	(pass_store_merging::terminate_all_aliasing_chains):
+	Drop unused argument, fix alias check to also consider uses.
+	(pass_store_merging::execute): Adjust.
+
+2016-11-07  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78228
+	* tree-ssa-phiopt.c (abs_replacement): Avoid introducing
+	undefined behavior.
+
+2016-11-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/77822
+	* config/aarch64/aarch64.md (*tb<optab><mode>1): Use
+	aarch64_simd_shift_imm_<mode> predicate for operand 1.
+	(<optab>, ANY_EXTRACT): Use tighter predicates on operands 2 and 3
+	to restrict them to an appropriate range and add FAIL check if the
+	region they specify is out of range.  Delete useless constraint
+	strings.
+	(*<optab><mode>, ANY_EXTRACT): Add appropriate predicates on operands
+	2 and 3 to restrict their range and add pattern predicate.
+
+2016-11-07  Martin Liska  <mliska@suse.cz>
+
+	* asan.c (enum asan_check_flags): Move the enum to header file.
+	(asan_init_shadow_ptr_types): Make type creation more generic.
+	(shadow_mem_size): New function.
+	(asan_emit_stack_protection): Use newly added ASAN_SHADOW_GRANULARITY.
+	Rewritten stack unpoisoning code.
+	(build_shadow_mem_access): Add new argument return_address.
+	(instrument_derefs): Instrument local variables if use after scope
+	sanitization is enabled.
+	(asan_store_shadow_bytes): New function.
+	(asan_expand_mark_ifn): Likewise.
+	(asan_sanitize_stack_p): Moved from asan_sanitize_stack_p.
+	* asan.h (enum asan_mark_flags): Moved here from asan.c
+	(asan_protect_stack_decl): Protect all declaration that need
+	to live in memory.
+	(asan_sanitize_use_after_scope): New function.
+	(asan_no_sanitize_address_p): Likewise.
+	* cfgexpand.c (partition_stack_vars): Consider
+	asan_sanitize_use_after_scope in condition.
+	(expand_stack_vars): Likewise.
+	* common.opt (-fsanitize-address-use-after-scope): New option.
+	* doc/invoke.texi (use-after-scope-direct-emission-threshold):
+	Explain the parameter.
+	* flag-types.h (enum sanitize_code): Define SANITIZE_USE_AFTER_SCOPE.
+	* gimplify.c (build_asan_poison_call_expr): New function.
+	(asan_poison_variable): Likewise.
+	(gimplify_bind_expr): Generate poisoning/unpoisoning for local
+	variables that have address taken.
+	(gimplify_decl_expr): Likewise.
+	(gimplify_target_expr): Likewise for C++ temporaries.
+	(sort_by_decl_uid): New function.
+	(gimplify_expr): Unpoison all variables for a label we can jump
+	from outside of a scope.
+	(gimplify_switch_expr): Unpoison variables defined in the switch
+	context.
+	(gimplify_function_tree): Clear asan_poisoned_variables.
+	(asan_poison_variables): New function.
+	(warn_switch_unreachable_r): Handle IFN_ASAN_MARK.
+	* internal-fn.c (expand_ASAN_MARK): New function.
+	* internal-fn.def (ASAN_MARK): Declare.
+	* opts.c (finish_options): Handle -fstack-reuse if
+	-fsanitize-address-use-after-scope is enabled.
+	(common_handle_option): Enable address sanitization if
+	-fsanitize-address-use-after-scope is enabled.
+	* params.def (PARAM_USE_AFTER_SCOPE_DIRECT_EMISSION_THRESHOLD):
+	New parameter.
+	* params.h: Likewise.
+	* sancov.c (pass_sanopt::execute): Handle IFN_ASAN_MARK.
+	* sanitizer.def: Define __asan_poison_stack_memory and
+	__asan_unpoison_stack_memory functions.
+	* asan.c (asan_mark_poison_p): New function.
+	(transform_statements): Handle asan_mark_poison_p calls.
+	* gimple.c (nonfreeing_call_p): Handle IFN_ASAN_MARK.
+
+2016-11-07  Tamar Christina  <tamar.christina@arm.com>
+
+	PR driver/78196
+	* Makefile.in (SELFTEST_FLAGS): Added -o /dev/null.
+
+2016-11-07  Martin Liska  <mliska@suse.cz>
+
+	* tree-profile.c (gimple_gen_time_profiler): Set proper type
+	to time_profiler_counter_ptr.
+
+2016-11-07  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/37150
+	* tree-vectorizer.h (vect_transform_slp_perm_load): Add n_perms
+	parameter.
+	* tree-vect-slp.c (vect_supported_load_permutation_p): Adjust.
+	(vect_analyze_slp_cost_1): Account for the real number of
+	permutations emitted and for dead loads.
+	(vect_transform_slp_perm_load): Add n_perms parameter counting
+	the number of emitted permutations.
+	* tree-vect-stmts.c (vectorizable_load): Adjust.
+
+2016-11-07  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78189
+	* tree-vect-data-refs.c (vect_compute_data_ref_alignment): Fix
+	alignment computation.
+
+2016-11-06  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* ipa-cp.c (ipcp_bits_lattice::meet_with): Remove unreachable code.
+
+2016-11-05  Martin Sebor  <msebor@redhat.com>
+
+	* doc/invoke.texi (Warning Options): Correct typos in -Walloca
+	documentation.
+
+2016-11-05  David Edelsohn  <dje.gcc@gmail.com>
+
+	PR bootstrap/78188
+	PR c++/71848
+	* ipa-comdats.c (pass_ipa_comdats::gate): Require HAVE_COMDAT_GROUP.
+
+2016-11-04  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/77834
+	* alias.c (nonoverlapping_memrefs_p): Return 0 if exprx or expry
+	doesn't have rtl set.
+
+2016-11-04  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000.c (gimple-ssa.h): New #include.
+	(TARGET_GIMPLE_FOLD_BUILTIN): Define as
+	rs6000_gimple_fold_builtin.
+	(rs6000_gimple_fold_builtin): New function.  Add handling for
+	early expansion of vector addition builtins.
+
+2016-11-04  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* expr.h (copy_blkmode_from_reg): Delete.
+	* expr.c (copy_blkmode_from_reg): Make static.
+
+2016-11-04  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* defaults.h (LOAD_EXTEND_OP): Define if not already defined.
+	* combine.c (LOAD_EXTEND_OP): Delete.
+	(simplify_comparison): Fix comment about LOAD_EXTEND_OP.
+	* cse.c (LOAD_EXTEND_OP): Delete.
+	* fold-const.c (LOAD_EXTEND_OP): Likewise.
+	* fwprop.c (free_load_extend): Remove #ifdef LOAD_EXTEND_OP/#endif.
+	* postreload.c (LOAD_EXTEND_OP): Delete.
+	* reload.c (push_reload): Remove #ifdef LOAD_EXTEND_OP/#endif.
+	Convert conditional compilation based on WORD_REGISTER_OPERATIONS.
+	(find_reloads): Likewise.
+	* reload1.c (eliminate_regs_1): Likewise.
+	* rtlanal.c (nonzero_bits1): Remove #ifdef LOAD_EXTEND_OP/#endif.
+	(num_sign_bit_copies1): Likewise.
+
+2016-11-04  David Malcolm  <dmalcolm@redhat.com>
+
+	* config/i386/i386.c: Include "selftest.h" and "selftest-rtl.h".
+	(selftest::ix86_test_dumping_hard_regs): New function.
+	(selftest::ix86_run_selftests): New function.
+	(TARGET_RUN_TARGET_SELFTESTS): When CHECKING_P, wire this up to
+	selftest::ix86_run_selftests.
+	* doc/tm.texi.in (TARGET_RUN_TARGET_SELFTESTS): New.
+	* doc/tm.texi: Regenerate
+	* selftest-rtl.h: New file.
+	* rtl-tests.c: Include "selftest-rtl.h".
+	(selftest::assert_rtl_dump_eq): Make non-static.
+	(ASSERT_RTL_DUMP_EQ): Move to selftest-rtl.h.
+	(selftest::test_dumping_regs): Update comment.
+	* selftest-run-tests.c: Include "target.h".
+	(selftest::run_tests): If non-NULL, call
+	targetm.run_target_selftests.
+	* target.def (run_target_selftests): New hook.
+
+2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm-arches.def (armv8-m.main+dsp): Set Cortex-M33 as
+	representative core for this architecture.
+	* config/arm/arm-cores.def (cortex-m33): Define new processor.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Likewise.
+	* config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex-M33 to the list of
+	valid -mcpu options.
+	* doc/invoke.texi (ARM Options): Document new Cortex-M33 processor.
+
+2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm-arches.def (armv8-m.base): Set Cortex-M23 as
+	representative core for this architecture.
+	* config/arm/arm-cores.def (cortex-m23): Define new processor.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Likewise.
+	* config/arm/arm.c (arm_v6m_tune): Add Cortex-M23 to the list of cores
+	this tuning parameters apply to in the comment.
+	* config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex-M23 to the list of
+	valid -mcpu options.
+	* doc/invoke.texi (ARM Options): Document new Cortex-M23 processor.
+
+2016-11-04  Bin Cheng  <bin.cheng@arm.com>
+
+	* fold-const.c (fold_cond_expr_with_comparison): Remove call
+	to pedantic_non_lvalue_loc.  Remove useless code for lvalue
+	where cond_expr can't be a lvalue.
+
+2016-11-04  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.c (arc_process_double_reg_moves): Use
+	gen_dexcl_2op call.
+	* config/arc/arc.md (movsi_insn): Disable unsupported move
+	instructions for ARCv2 cores.
+	(movdi): Use prepare_move_operands.
+	(movsf, movdf): Use move_dest_operand predicate.
+	* config/arc/constraints.md (Chs): Enable when barrel shifter is
+	present.
+	* config/arc/fpu.md (divsf3): Change to divsf3_fpu.
+	* config/arc/fpx.md (dexcl_3op_peep2_insn): Dx data register is
+	also a destination.
+	(dexcl_3op_peep2_insn_nores): Likewise.
+	* config/arc/arc.h (SHIFT_COUNT_TRUNCATED): Define to one.
+	(LINK_COMMAND_SPEC): Remove.
+
+2016-11-04  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/78185
+	* loop-invariant.c (find_exits): Record entering inner
+	loops as possibly exiting to handle infinite sub-loops.
+	* tree-ssa-loop-im.c: Include tree-ssa-loop-niter.h.
+	(fill_always_executed_in_1): Honor infinite child loops.
+
+2016-11-03  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/78192
+	* config/rs6000/vsx.md (vsx_extract_<mode>_di): The element number
+	has already been adjusted for endianness, so don't adjust it any
+	further.
+
+	PR target/77993
+	* config/rs6000/rs6000.h (FLOAT128_IBM_P): Do not allow IFmode or
+	ICmode unless we have standard PowerPC floating point.
+	* config/rs6000/rs6000.md (FP iterator): Likewise.
+	(FMOVE128 iterator): Likewise.
+
+2016-11-03  Jakub Jelinek  <jakub@redhat.com>
+	    Alexandre Oliva  <aoliva@redhat.com>
+	    Jason Merrill  <jason@redhat.com>
+
+	PR debug/28767
+	PR debug/56974
+	* langhooks.h (struct lang_hooks_for_types): Add type_dwarf_attribute
+	langhook.
+	* langhooks.c (lhd_type_dwarf_attribute): New function.
+	* langhooks-def.h (lhd_type_dwarf_attribute): Declare.
+	(LANG_HOOKS_TYPE_DWARF_ATTRIBUTE): Define.
+	(LANG_HOOKS_FOR_TYPES_INITIALIZER): Add
+	LANG_HOOKS_TYPE_DWARF_ATTRIBUTE.
+	(check_qualified_type, check_aligned_type): Call it.
+	* dwarf2out.c (modified_type_die): Don't use type_main_variant
+	for FUNCTION_TYPE or METHOD_TYPE, instead walk over variants with
+	check_base_type and check_lang_type.
+	(gen_ptr_to_mbr_type_die): If lookup_type_die is already non-NULL,
+	return early.  For pointer-to-data-member add DW_AT_use_location
+	attribute.
+	(gen_subroutine_type_die): Add DW_AT_{,rvalue_}reference attribute
+	if needed.
+	(gen_type_die_with_usage): Don't use type_main_variant
+	for FUNCTION_TYPE or METHOD_TYPE, instead walk over variants with
+	check_base_type and check_lang_type.  Formatting fixes. Call
+	get_debug_type langhook.
+
+2016-11-03  Jason Merrill  <jason@redhat.com>
+
+	* tree.c (check_lang_type): New.
+	(check_qualified_type): Use it.
+	(check_aligned_type): Use it.
+	* tree.h: Declare it.
+
+2016-11-03  Richard Earnshaw  <rearnsha@arm.com>
+
+	* config.gcc (arm-wrs-vxworks): Set target_cpu_cname.
+	(arm*-freebsd*): Likewise.
+	(arm*-*-netbsdelf*): Likewise.
+	(arm*-*-linux*): Likewise.
+	(arm*-*-uclinux*eabi*): Likewise.
+	(arm*-*-phoenix*): Likewise.
+	(arm*-*-eabi*, arm*-*-symbianelf*, arm*-*-rtems*): Likewise.
+	(arm*-*-*): Don't clobber target_cpu_cname when --with-cpu is not
+	specified.  Default to arm6 if target_cpu_cname is not set.
+	* arm/arm.c (arm_option_override): Simplify logic.  Assert that the
+	default cpu has been correctly configured.
+	* arm/arm.h (TARGET_CPU_DEFAULT): Delete.
+	(target_cpus): Delete TARGET_CPU_generic, add TARGET_CPU_num_cores.
+	* arm/freebsd.h (SUBTARGET_CPU_DEFAULT): Delete.
+	* arm/linux-eabi.h (SUBTARGET_CPU_DEFAULT): Delete.
+	* arm/linux-elf.h (SUBTARGET_CPU_DEFAULT): Delete.
+	* arm/symbian.h (SUBTARGET_CPU_DEFAULT): Delete.
+	* arm/unknown-elf.h (SUBTARGET_CPU_DEFAULT): Delete.
+
+2016-11-03  Jiong Wang  <jiong.wang@arm.com>
+
+	* reg-notes.def (CFA_VAL_EXPRESSION): New entry.
+	* dwarf2cfi.c (dwarf2out_frame_debug_cfa_val_expression): New function.
+	(dwarf2out_frame_debug): Support REG_CFA_VAL_EXPRESSION.
+	(output_cfa_loc): Support DW_CFA_val_expression.
+	(output_cfa_loc_raw): Likewise.
+	(output_cfi): Likewise.
+	(output_cfi_directive): Likewise.
+	* dwarf2out.c (dw_cfi_oprnd1_desc): Support DW_CFA_val_expression.
+	(dw_cfi_oprnd2_desc): Likewise.
+	(mem_loc_descriptor): Recognize new pattern generated for value
+	expression.
+
+2016-11-03  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78186
+	* combine.c (change_zero_ext): Mask the RHS of a zero_extract as
+	well, when converting to IOR.
+
+2016-11-03  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc.md (vec_interleave_lowv8qi): Delete.
+	(vec_interleave_highv8qi): Likewise.
+
+2016-11-03  Martin Liska  <mliska@suse.cz>
+
+	* profile.c (instrument_values): Fix coding style.
+	(branch_prob): Use renamed function.
+	* tree-profile.c (init_ic_make_global_vars): Likewise.
+	(gimple_init_edge_profiler): Rename to
+	gimple_init_gcov_profiler.
+	tree_time_profiler_counter variable declaration.
+	(gimple_gen_time_profiler): Rewrite to do a direct gimple code
+	emission.
+	* value-prof.h: Remove an argument.
+
+2016-11-03  Richard Biener  <rguenther@suse.de>
+
+	* config/rs6000/rs6000.c (rs6000_xcoff_declare_object_name): Use
+	symtab_node::get_create.
+
+2016-11-03  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* rtlanal.c (nonzero_bits1): Fix WORD_REGISTER_OPERATIONS condition.
+	Move comments into more natural position.
+
+2016-11-03  Vineet Gupta  <vgupta@synopsys.com>
+
+	* config/arc/arc.h (SIZE_TYPE): Define as unsigned int.
+	(PTRDIFF_TYPE): Define as int.
+
+2016-11-03  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* ccmp.c (expand_ccmp_expr_1): Adjust.
+	(expand_ccmp_expr): Likewise.
+	(expand_ccmp_next): Likewise.
+	* config/aarch64/aarch64.c (aarch64_gen_ccmp_next): Likewise.
+	(aarch64_gen_ccmp_first): Likewise.
+	* doc/tm.texi: Regenerate.
+	* target.def (gen_ccmp_first): Change argument types to rtx_insn *.
+	(gen_ccmp_next): Likewise.
+
+2016-11-03  Bin Cheng  <bin.cheng@arm.com>
+
+	* tree-vect-loop.c (destroy_loop_vec_info): Handle cond_expr.
+	(vect_is_simple_reduction): Swap cond_reduction by inversion.
+
+2016-11-02  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.c (ix86_init_libfuncs): New.  Call
+	darwin_rename_builtins here.
+	(ix86_expand_divmod_libfunc): New.
+	(TARGET_INIT_LIBFUNCS): Unconditionally define to ix86_init_libfuncs.
+	(TARGET_EXPAND_DIVMOD_LIBFUNC): Define.
+
+2016-11-02  Cesar Philippidis  <cesar@codesourcery.com>
+	    Nathan Sidwell  <nathan@acm.org>
+
+	* config/nvptx/nvptx.c (PTX_GANG_DEFAULT): Set to zero.
+
+2016-11-02  Max Filippov  <jcmvbkbc@gmail.com>
+
+	* config/xtensa/xtensa.c (xtensa_output_integer_literal_parts):
+	New function.
+	(xtensa_output_literal): Use xtensa_output_integer_literal_parts
+	to format MODE_INT and MODE_PARTIAL_INT literals.
+
+2016-11-02  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/78168
+	* config/r6000/rs6000.c (rs6000_get_separate_components): Return
+	NULL if TARGET_SPE_ABI.
+
+2016-11-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gimple-ssa-store-merging.c (encode_tree_to_bitpos): Don't forget to
+	clear padding bits even when they're less than a byte.
+
+2016-11-02  Richard Biener  <rguenther@suse.de>
+
+	* gimple-ssa-store-merging.c: Include gimplify-me.h.
+	(imm_store_chain_info::output_merged_stores): Force base_addr
+	to be proper GIMPLE for a MEM_REF address.
+	(pass_store_merging::execute): Restrict negative bitpos
+	handling to non-MEM_REF bases.  Remove TREE_THIS_VOLATILE
+	check.  Take into account non-NULL_TREE offset if the base
+	is already addressable.
+
+2016-11-26  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hv4si):
+	New pattern.
+	(aarch64_be_crypto_sha1hv4si): New pattern.
+
+2016-11-02  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64.md (add<mode>3): Remove
+	redundant code.  Don't split frame based additions.
+
+2016-11-02  Richard Biener  <rguenther@suse.de>
+
+	* gimple-ssa-store-merging.c (struct store_immediate_info): Remove
+	redundant val and dest members.
+	(store_immediate_info::store_immediate_info): Adjust.
+	(merged_store_group::merged_store_group): Adjust.
+	(merged_store_group::apply_stores): Likewise.
+	(struct imm_store_chain_info): Add base_addr field.
+	(imm_store_chain_info::imm_store_chain_info): New constructor.
+	(imm_store_chain_info::terminate_and_process_chain): Do not pass base.
+	(imm_store_chain_info::output_merged_store): Likewise.  Use
+	addr_base which is already the address.
+	(imm_store_chain_info::output_merged_stores): Likewise.
+	(pass_tree_store_merging::terminate_all_aliasing_chains): Take
+	imm_store_chain_info instead of base.  Fix alias check.
+	(pass_tree_store_merging::terminate_and_release_chain): Likewise.
+	(imm_store_chain_info::coalesce_immediate_stores): Adjust.
+	(pass_store_merging::execute): Refuse to operate on TARGET_MEM_REF.
+	use the address of the base and adjust for other changes.
+
+2016-11-02  Martin Liska  <mliska@suse.cz>
+
+	* fold-const-call.c (host_size_t_cst_p): Test whether
+	t is convertible to size_t.
+
+2016-11-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR tree-optimization/78170
+	* gimple-ssa-store-merging.c (encode_tree_to_bitpos): Truncate padding
+	introduced by native_encode_expr on little-endian as well.
+
+2016-11-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR tree-optimization/78162
+	* gimple-ssa-store-merging.c (execute): Mark stores with bitpos < 0
+	as invalid.
+
+2016-11-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_register_saved_on_entry): Add
+	function comment.
+	(aarch64_next_callee_save): Likewise.
+	(aarch64_pushwb_single_reg): Likewise.
+	(aarch64_gen_storewb_pair): Likewise.
+	(aarch64_push_regs): Likewise.
+	(aarch64_gen_loadwb_pair): Likewise.
+	(aarch64_pop_regs): Likewise.
+	(aarch64_gen_store_pair): Likewise.
+	(aarch64_gen_load_pair): Likewise.
+	(aarch64_save_callee_saves): Likewise.
+	(aarch64_restore_callee_saves): Likewise.
+
+2016-11-02  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78035
+	PR tree-optimization/77964
+	* gimple-pretty-print.c (pp_points_to_solution): Print
+	vars_contains_interposable.
+	* tree-ssa-alias.c: Include varasm.h.
+	(ptrs_compare_unequal): Check vars_contains_interposable and
+	decl_binds_to_current_def_p.
+	(dump_points_to_solution): Dump vars_contains_interposable.
+	* tree-ssa-alias.h (struct pt_solution): Add vars_contains_interposable
+	flag.
+	* tree-ssa-structalias.c: Include varasm.h.
+	(set_uids_in_ptset): Record whether vars contains a
+	not decl_binds_to_current_def_p variable in vars_contains_interposable.
+	(ipa_escaped_pt): Update initializer.
+
+2016-11-02  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78047
+	* tree-ssa-structalias.c (push_fields_onto_fieldstack): Initialize
+	fake field at offset zero conservatively regarding to may_have_pointers.
+
+2016-11-02  Richard Biener  <rguenther@suse.de>
+
+	* tree-vrp.c (evrp_dom_walker::before_dom_children): Call
+	infer_value_range on stmt ops and update value-ranges.
+	Dump visited stmts and blocks.
+	(evrp_dom_walker::push_value_range): Dump changes.
+	(evrp_dom_walker::pop_value_range): Likewise.
+	(evrp_dom_walker::try_find_new_range): Avoid noop changes.
+
+2016-11-01  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* emit-rtl.c (prev_nonnote_insn_bb): Change argument type to
+	rtx_insn *.
+	* rtl.h (prev_nonnote_insn_bb): Adjust prototype.
+
+2016-11-01  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* cfgrtl.c (delete_insn_chain): Change argument type to rtx_insn *
+	and adjust for that.
+	* cfgrtl.h (delete_insn_chain): Adjust prototype.
+
+2016-11-01  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* config/rl78/rl78.c (gen-and_emit_move): Change argument type
+	to rtx_insn *.
+	(transcode_memory_rtx): Likewise.
+	(move_to_acc): Likewise.
+	(move_from_acc): Likewise.
+	(move_acc_to_reg): Likewise.
+	(move_to_x): Likewise.
+	(move_to_hl): Likewise.
+	(move_to_de): Likewise.
+	* config/rs6000/rs6000.c (emit_frame_save): Likewise.
+	(rs6000_emit_savres_rtx): Likewise.
+	(rs6000_emit_prologue): Likewise.
+	* reorg.c (update_reg_unused_notes): Likewise.
+	* rtl.h (remove_note): Adjust prototype.
+	* rtlanal.c (remove_note): Make argument type rtx_insn *.
+
+2016-11-01  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* config/alpha/alpha.c (alpha_legitimize_address_1): Split up
+	variables so some can be rtx_insn *.
+	(alpha_emit_xfloating_libcall): Likewise.
+	* config/mips/mips.c (mips_call_tls_get_addr): Likewise.
+	(mips_legitimize_tls_address): Likewise.
+	* optabs.c (expand_binop): Likewise.
+	* reload1.c (gen_reload): Likewise.
+
+2016-11-01  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* reorg.c (relax_delay_slots): Split up the trial variable.
+
+2016-11-01  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* config/arc/arc.c (arc_emit_call_tls_get_addr): Make the type
+	of variables rtx_insn *.
+	* config/arm/arm.c (arm_call_tls_get_addr): Likewise.
+	(legitimize_tls_address): Likewise.
+	* config/bfin/bfin.c (hwloop_optimize): Likewise.
+	(bfin_gen_bundles): Likewise.
+	* config/c6x/c6x.c (reorg_split_calls): Likewise.
+	(c6x_reorg): Likewise.
+	* config/frv/frv.c (frv_reorder_packet): Likewise.
+	* config/i386/i386.c (ix86_split_idivmod): Likewise.
+	* config/ia64/ia64.c (ia64_expand_compare): Likewise.
+	* config/m32c/m32c.c (m32c_prepare_shift): Likewise.
+	* config/mn10300/mn10300.c: Likewise.
+	* config/rl78/rl78.c: Likewise.
+	* config/s390/s390.c (s390_fix_long_loop_prediction): Likewise.
+	* config/sh/sh-mem.cc (sh_expand_cmpstr): Likewise.
+	(sh_expand_cmpnstr): Likewise.
+	(sh_expand_strlen): Likewise.
+	(sh_expand_setmem): Likewise.
+	* config/sh/sh.md: Likewise.
+	* emit-rtl.c (emit_pattern_before): Likewise.
+	* except.c: Likewise.
+	* final.c: Likewise.
+	* jump.c: Likewise.
+
+2016-11-01  Jason Merrill  <jason@redhat.com>
+
+	* tree-inline.c (copy_tree_body_r): Only copy the taken branch of
+	a COND_EXPR with constant condition.
+
+2016-11-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2out.c (gen_variable_die): Remove again origin_die variable
+	and its initialization.
+
+2016-11-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* dwarf2out.c (output_rnglists): Wrap basebuf, len in
+	HAVE_AS_LEB128.
+
+2016-11-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2out.c (add_name_and_src_coords_attributes): Add NO_LINKAGE_NAME
+	argument, don't call add_linkage_name if it is true.
+	(gen_variable_die): For C++ inline static data members, consider the
+	initial call when old_die is NULL to be declaration and call
+	add_name_and_src_coords_attributes in that case with true as
+	NO_LINKAGE_NAME.  Add DW_AT_inline attribute if needed.
+	(gen_member_die): For C++ inline static data members, emit a
+	definition DIE right away in DW_TAG_compile_unit context.
+
+2016-11-01  John David Anglin  <danglin@gcc.gnu.org>
+
+	PR target/78166
+	* config/pa/pa.md: Add new shift/add patterns to handle
+	(plus (mult (reg) (mem_shadd_operand)) (reg)) source operand.
+
+2016-11-01  Max Filippov  <jcmvbkbc@gmail.com>
+
+	* config/xtensa/xtensa-protos.h
+	(xtensa_use_return_instruction_p): New prototype.
+	* config/xtensa/xtensa.c (xtensa_current_frame_size,
+	xtensa_callee_save_size): Remove.
+	(struct machine_function): Add new fields: current_frame_size,
+	callee_save_size, frame_laid_out and epilogue_done.
+	(compute_frame_size, xtensa_expand_prologue,
+	xtensa_expand_epilogue): Replace xtensa_callee_save_size with
+	cfun->machine->callee_save_size and xtensa_current_frame_size
+	with cfun->machine->current_frame_size.
+	(compute_frame_size): Update cfun->machine->frame_laid_out and
+	don't update frame layout after reload completion.
+	(xtensa_expand_epilogue): Set cfun->machine->epilogue_done
+	instead of zeroing xtensa_current_frame_size.
+	(xtensa_use_return_instruction_p): New function.
+	* config/xtensa/xtensa.h (xtensa_current_frame_size): Remove
+	declaration.
+	(INITIAL_ELIMINATION_OFFSET): Use return value of
+	compute_frame_size instead of xtensa_current_frame_size value.
+	* config/xtensa/xtensa.md ("return" pattern): Use new predicate
+	function xtensa_use_return_instruction_p instead of inline code.
+
+2016-11-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* tree.h (BLOCK_IN_COLD_SECTION_P): Define.
+	* final.c (final_scan_insn): Set BLOCK_IN_COLD_SECTION_P.
+	* dwarf2out.c (rnglist_idx): New variable.
+	(struct dw_ranges): Add label, idx and maybe_new_sec fields.
+	(DEBUG_RNGLISTS_SECTION): Define.
+	(ranges_base_label): New variable.
+	(size_of_die) <case dw_val_class_range_list>: If using
+	DW_FORM_rnglistx, count size of uleb128 of range list index.
+	(value_format) <case dw_val_class_range_list>: For
+	-gdwarf-5 -gsplit-dwarf return DW_FORM_rnglistx.
+	(output_range_list_offset): Handle -gdwarf-5 .debug_rnglists
+	offsets.  Multiply dwarf < 5 offsets by 2 * DWARF_ADDR_SIZE.
+	(add_ranges_num): Remove useless prototype.  Don't multiply
+	by 2 * DWARF2_ADDR_SIZE.  Add maybe_new_sec argument, adjust
+	for new fields added to dw_ranges struct.
+	(add_ranges): Add maybe_new_sec argument and pass it
+	through to add_ranges_num.
+	(note_rnglist_head): New function.
+	(add_ranges_by_labels): Pass true as maybe_new_sec to
+	add_ranges_num, call note_rnglist_head on the head of the list.
+	(output_ranges): Add function comment.  Switch to
+	.debug_ranges section here and emit .Ldebug_ranges0 label.
+	(index_rnglists, output_rnglists): New functions.
+	(gen_subprogram_die): Formatting fixes.
+	(add_high_low_attributes): Don't divide offsets
+	by 2 * DWARF2_ADDR_SIZE.  Call note_rnglist_head on the
+	first list element or when pointing into the middle of
+	a list.  Pass true as second argument to add_ranges on the
+	first block fragment after cold/hot section switch.
+	(init_sections_and_labels): For -gdwarf-5 use .debug_rnglists
+	section instead of .debug_ranges.  Initialize
+	ranges_base_label if -gdwarf-5 -gsplit-dwarf.
+	(dwarf2out_finish): For -gdwarf-5 -gsplit-dwarf call
+	index_rnglists and add DW_AT_rnglists_base attr.  Don't switch
+	to dwarf_ranges_section here or emit .Ldebug_ranges0 label.
+	Call output_rnglists for -gdwarf-5.
+	(dwarf2out_c_finalize): Clear rnglist_idx.
+
+2016-11-01  Fritz Reese  <fritzoreese@gmail.com>
+
+	* combine.c (simplify_compare_const): Add gcc_fallthrough.
+
+2016-11-01  Bilyan Borisov  <bilyan.borisov@arm.com>
+	    Tamar Christina <tamar.christina@arm.com>
+
+	* config/arm/arm-c.c (arm_cpu_builtins): New macro definition.
+	* config/arm/arm_neon.h (vmaxnm_f32): New intrinsinc.
+	(vmaxnmq_f32): Likewise.
+	(vminnm_f32): Likewise.
+	(vminnmq_f32): Likewise.
+	* config/arm/arm_neon_builtins.def (vmaxnm): New builtin.
+	(vminnm): Likewise.
+	* config/arm/neon.md (neon_<fmaxmin_op><mode>, VCVTF): New
+	expander.
+
+2016-10-31  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/vsx.md (VSX_EXTRACT_FL): New iterator for all
+	binary floating point types supported by the hardware except for
+	double.
+	(vsx_xvcvsxwdp_df): Provide scalar result alternative to the
+	vector instruction for optimizing extracting a SImode from a
+	V4SImode vector and converting it to floating point.
+	(vsx_xvcvuxwdp_df): Likewise.
+	(vsx_extract_si): On ISA 3.0, allow extract target and temporary
+	registers to be any VSX register.  Move stores to the end of the
+	constraints.
+	(vsx_extract_si_<uns>float_df): New combiner pattern and splitter
+	to optimize extracting a SImode from a V4SImode vector and
+	converting it to a binary floating point type supported by the
+	hardware.  Use the vector converts instead of extracting the
+	element, sign extending it, and then converting it to double.
+	Other floating point types  than double first convert to double,
+	then the double is converted to that type.
+	(vsx_extract_si_<uns>float_<mode>): Likewise.
+
+2016-10-31  Andrew Pinski  <apinski@cavium.com>
+
+	* config/aarch64/driver-aarch64.c (host_detect_local_cpu):
+	Rewrite handling of part num to handle the case where
+	multiple implementers share the same part num.
+
+2016-10-31  Jan Kratochvil  <jan.kratochvil@redhat.com>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2out.c (DWARF_COMPILE_UNIT_HEADER_SIZE): Adjust for -gdwarf-5.
+	(DWARF_COMDAT_TYPE_UNIT_HEADER_SIZE): Likewise.
+
+2016-10-31  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2out.c (dwarf_AT): Handle DW_AT_dwo_name.
+	(use_debug_types): Adjust comment for DWARF5 DW_UT_type units.
+	(new_die): Handle DW_TAG_skeleton_unit like DW_TAG_compile_unit.
+	(is_cu_die, is_unit_die): Likewise.
+	(should_move_die_to_comdat, break_out_comdat_types): Adjust
+	comments for DWARF5 DW_UT_type units.
+	(output_compilation_unit_header): Add UT argument, output
+	start of DWARF5 .debug_info section header.
+	(output_comp_unit): Add dwo_id argument.  Adjust
+	output_compilation_unit_header caller, for DW_UT_split_compile
+	emit dwo_id field, otherwise padding1.  Emit padding2 field.
+	(add_top_level_skeleton_die_attrs): Add DW_AT_dwo_name
+	rather than DW_AT_GNU_dwo_name attr for -gdwarf-5.
+	(output_skeleton_debug_sections): Add dwo_id argument, for
+	-gdwarf-5 emit DWARF 5 DW_UT_skeleton header.
+	(output_comdat_type_unit): For -gdwarf-5 emit .debug_info
+	DW_UT_type or DW_UT_split_type units rather than .debug_types.
+	(dwarf2out_finish): Use DW_TAG_skeleton_unit rather than
+	DW_TAG_compile_unit for skeleton unit die.  Don't add
+	DW_AT_GNU_dwo_id attributes for -gdwarf-5, instead pass checksum
+	address to output_comp_unit and output_skeleton_debug_sections.
+
+	* dwarf2out.c (debug_line_str_section): New variable.
+	(debug_line_str_hash): Likewise.
+	(DEBUG_LINE_STR_SECTION): Define.
+	(set_indirect_string): Handle DW_FORM_line_strp like
+	DW_FORM_strp.
+	(find_string_form): Fix up formatting.
+	(size_of_die): Handle DW_FORM_line_strp like DW_FORM_strp.
+	Fix up indentation.
+	(output_die): Handle DW_FORM_line_strp.
+	(DWARF5_USE_DEBUG_LINE_STR): Define.
+	(output_line_string): New function.
+	(output_file_names): Add -gdwarf-5 support.
+	(output_line_info): Likewise.
+	(init_sections_and_labels): Initialize debug_line_str_section.
+	(output_indirect_string): Change 2nd argument from void *
+	to enum dwarf_form form, compare with form rather than
+	DW_FORM_strp.
+	(output_indirect_strings): Pass DW_FORM_strp to
+	output_indirect_string traversion.
+	(dwarf2out_finish): Output .debug_line_str strings.
+	(dwarf2out_c_finalize): Clear debug_line_str_section and
+	debug_line_str_hash.
+
+2016-10-31  Tom Tromey  <tom@tromey.com>
+
+	PR debug/77315
+	* dwarf2out.c (mem_loc_descriptor): Use DW_OP_form_tls_address.
+	(resolve_args_picking_1): Move DW_OP_form_tls_address case next to
+	DW_OP_GNU_push_tls_address case.
+	(loc_list_from_tree_1): Use DW_OP_form_tls_address.
+
+2016-10-31  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2out.h (struct dw_loc_descr_node): Adjust comment
+	for frame_offset_rel bit.
+	(struct array_descr_info): Add rank field.
+	* dwarf2out.c (struct loc_descr_context): Add placeholder_arg
+	and placeholder_seen fields.
+	(resolve_args_picking_1): Handle also frame_offset_rel DW_OP_dup
+	and DW_OP_over.  Optimize DW_OP_pick 0 into DW_OP_dup and
+	DW_OP_pick 1 into DW_OP_over.
+	(function_to_dwarf_procedure, type_byte_size, field_byte_offset,
+	gen_variant_part): Clear placeholder_{arg,seen}.
+	(loc_list_from_tree_1): Drop const from context argument.
+	Handle integral PLACEHOLDER_EXPR if context->placeholder_arg.
+	(loc_list_for_address_of_addr_expr_of_indirect_ref,
+	loc_list_from_tree, loc_descriptor_from_tree): Drop const from
+	context argument.
+	(add_scalar_info): Drop const from context argument.  Handle
+	context->placeholder_arg.
+	(add_bound_info): Drop const from context argument.
+	(gen_descr_array_type_die): Drop const from ctx variable.
+	Initialize placeholder_arg and placeholder_seen.  Add DW_AT_rank
+	attribute and use a single DW_TAG_generic_subrange instead of
+	7 DW_TAG_subrange_type for assumed rank arrays.
+
+	* dwarf2out.h (enum dw_val_class): Add dw_val_class_loclistsptr.
+	* dwarf2out.c (struct dw_loc_list_struct): Change emitted field
+	from bool to 1-bit uchar bitfield.  Add num_assigned and
+	offset_emitted bitfields.
+	(dw_val_equal_p): Compare v.val_lbl_id rather than v.val_unsigned
+	for dw_val_class_lineptr and dw_val_class_macptr.  Handle
+	dw_val_class_loclistsptr.
+	(new_addr_loc_descr): Fix up formatting.
+	(DEBUG_LOCLISTS_SECTION, DEBUG_DWO_LOCLISTS_SECTION): Define.
+	(add_AT_low_high_pc): Fix up formatting.
+	(add_AT_loclistsptr): New function.
+	(AT_lbl): Allow dw_val_class_loclistsptr.
+	(print_dw_val, attr_checksum, attr_checksum_ordered, same_dw_val_p):
+	Handle dw_val_class_loclistsptr.
+	(loc_list_idx): New variable.
+	(output_loclists_offsets, assign_location_list_indexes): New
+	functions.
+	(size_of_die): For dw_val_class_loc_list -gsplit-dwarf -gdwarf-5
+	add size_of_uleb128 of the index.  Drop never used
+	dwarf_split_debug_info AT_index handling.  Handle
+	dw_val_class_loclistsptr.
+	(value_format): Return DW_FORM_loclistsx for dw_val_class_loc_list
+	if -gsplit-dwarf -gdwarf-5.  Handle dw_val_class_loclistsptr.
+	(output_loc_list): Handle DWARF 5 .debug_loclists* format.
+	(output_loc_list_offset): Handle -gsplit-dwarf -gdwarf-5
+	DW_FORM_loclistx indexes.
+	(output_attr_index_or_value): Fix up formatting.  Don't handle
+	dw_val_class_loc_list here.
+	(output_die): Formatting fixes.  Handle dw_val_class_loclistsptr.
+	For dw_val_class_loc_list call output_loc_list_offset rather than
+	output_attr_index_or_value.
+	(init_sections_and_labels): For -gdwarf-5 use .debug_loclists
+	or .debug_loclists.dwo section name for debug_loc_section.
+	(resolve_addr_in_expr): Formatting fix.
+	(index_location_lists): Likewise.
+	(dwarf2out_finish): If there are any location lists, for
+	-gsplit-dwarf -gdwarf-5 add DW_AT_loclists_base attribute.  Call
+	index_location_lists only if have_location_lists.  Call
+	assign_location_list_indexes for -gsplit-dwarf -gdwarf-5.  Emit
+	.debug_loclists{,.dwo} section header for -gdwarf-5, for -gdwarf-5
+	-gsplit-dwarf also emit offset table.
+
+	* dwarf2out.c (DWARF_LARGEST_DATA_FORM_BITS): Define.
+	(size_of_die, value_format, output_die): Use
+	DW_FORM_data16 for 128-bit dw_val_class_const_double or
+	dw_val_class_wide_int.
+
+	* dwarf2out.c (dwarf_op): Renamed to ...
+	(dwarf_OP): ... this.
+	(convert_descriptor_to_mode, scompare_loc_descriptor,
+	minmax_loc_descriptor, typed_binop, mem_loc_descriptor,
+	implicit_ptr_descriptor, optimize_one_addr_into_implicit_ptr): Adjust
+	callers.
+	(dwarf_AT, dwarf_TAG): New functions.
+	(check_die): Disallow DW_AT_call_all_calls next to
+	DW_AT_GNU_all_call_sites.
+	(gen_call_site_die): Use dwarf_TAG and dwarf_AT with DWARF 5 tag
+	and attributes instead of the corresponding GNU tag and attributes.
+	(gen_subprogram_die): Likewise.  Emit call site information even
+	for -gdwarf-5 -gstrict-dwarf.  Replace DW_AT_GNU_defaulted with
+	DW_AT_defaulted in comment.
+	(resolve_addr): Handle DW_AT_call_origin attribute on
+	DW_TAG_call_site DIE like DW_AT_abstract_origin on
+	DW_TAG_GNU_call_site DIE.
+
+	* dwarf2out.c (dwarf_op): New function.
+	(size_of_loc_descr): Handle DW_OP_{implicit_pointer,entry_value},
+	DW_OP_{const,regval,deref}_type and DW_OP_{convert,reinterpret}.
+	(output_loc_operands, output_loc_operands_raw): Likewise.
+	(resolve_args_picking_1, prune_unused_types_walk_loc_descr,
+	mark_base_types, hash_loc_operands, compare_loc_operands): Likewise.
+	(resolve_addr_in_expr): Likewise.  Only punt for !dwarf_strict
+	if dwarf_version < 5.
+	(convert_descriptor_to_mode): Use dwarf_op (DW_OP_xxx) instead of
+	DW_OP_GNU_xxx.
+	(scompare_loc_descriptor, ucompare_loc_descriptor,
+	minmax_loc_descriptor, typed_binop, mem_loc_descriptor,
+	implicit_ptr_descriptor, optimize_one_addr_into_implicit_ptr,
+	optimize_location_into_implicit_ptr): Likewise.  Only punt for
+	!dwarf_strict if dwarf_version < 5.
+	(string_cst_pool_decl): Adjust comment.
+	(non_dwarf_expression): Handle DW_OP_implicit_pointer.
+
+	* dwarf2out.h (enum dw_val_class): Add dw_val_class_const_implicit,
+	dw_val_class_unsigned_const_implicit and dw_val_class_file_implicit.
+	(struct dw_val_node): Add val_file_implicit field.
+	* dwarf2out.c (dw_val_equal_p, print_dw_val, attr_checksum,
+	attr_checksum_ordered, same_dw_val_p, size_of_die, value_format,
+	output_die): Handle dw_val_class_const_implicit,
+	dw_val_class_unsigned_const_implicit and dw_val_class_file_implicit.
+	(abbrev_die_table): Change into va_gc vec.
+	(abbrev_die_table_allocated, abbrev_die_table_in_use,
+	ABBREV_DIE_TABLE_INCREMENT): Remove.
+	(AT_int, AT_unsigned, AT_file): Allow dw_val_class_*_implicit.
+	(abbrev_opt_start, abbrev_usage_count, sorted_abbrev_dies): New
+	variables.
+	(build_abbrev_table): Adjust for abbrev_die_table being a va_gc vec.
+	If abbrev_opt_start, fill in abbrev_usage_count and abbrev_dies
+	vectors.
+	(die_abbrev_cmp, optimize_implicit_const, optimize_abbrev_table): New
+	functions.
+	(output_die_abbrevs): For DW_FORM_implicit_const emit sleb128 with
+	the implicit value.
+	(output_abbrev_section): Adjust for abbrev_die_table being a va_gc
+	vec.
+	(output_comp_unit): Initialize abbrev_opt_start if emitting the main
+	unit.  Call optimize_abbrev_table.
+	(dwarf2out_init, dwarf2out_finish, dwarf2out_c_finalize): Adjust for
+	abbrev_die_table being a va_gc vec.
+
+	PR tree-optimization/77860
+	* tree-ssa-reassoc.c (eliminate_using_constants): Handle
+	also integral complex and vector constants.
+
+	* dwarf2out.c (dwarf2out_define, dwarf2out_undef, output_macinfo_op,
+	optimize_macinfo_range, save_macinfo_strings): Replace
+	DW_MACRO_GNU_* constants with corresponding DW_MACRO_* constants.
+	(output_macinfo): Likewise.  Emit .debug_macro* rather than
+	.debug_macinfo* even for -gstrict-dwarf -gdwarf-5.
+	(init_sections_and_labels): Use .debug_macro* labels rather than
+	.debug_macinfo* labels even for -gstrict-dwarf -gdwarf-5.
+	(dwarf2out_finish): Use DW_AT_macros instead of DW_AT_macro_info
+	or DW_AT_GNU_macros for -gdwarf-5.
+
+2016-10-31  Waldemar Brodkorb  <wbx@openadk.org>
+
+	* config/microblaze/linux.h (UCLIBC_DYNAMIC_LINKER): Define.
+
+2016-09-11  Le-Chun Wu  <lcwu@google.com>
+	    Mark Wielaard  <mjw@redhat.com>
+
+	* common.opt (Wshadow=global): New option. Default for -Wshadow.
+	(Wshadow=local): New option.
+	(Wshadow-local): Hidden alias for -Wshadow=local.
+	(Wshadow=compatible-local): New option.
+	(Wshadow-compatible-local): Hidden alias for
+	-Wshadow=compatible-local.
+	* doc/invoke.texi: Document Wshadow=global, Wshadow=local and
+	Wshadow=compatible-local.
+
+2016-10-31  Bin Cheng  <bin.cheng@arm.com>
+
+	* tree-vect-slp.c (vect_get_and_check_slp_defs): New parameter SWAP.
+	Check slp defs for COND_EXPR by swapping/inverting operands if the
+	new parameter SWAP indicates so.
+	(vect_build_slp_tree_1): New parameter SWAP.  Check COND_EXPR stmt
+	is isomorphic to the first stmt via swapping/inverting.  Store swap
+	information in the new parameter SWAP.
+	(vect_build_slp_tree): New local array SWAP and pass it to function
+	vect_build_slp_tree_1.  Cleanup result handling code for function
+	call to vect_get_and_check_slp_defs.  Skip operand swapping if the
+	order of operands has been fixed as indicated by SWAP[i].
+
+2016-10-31  Bin Cheng  <bin.cheng@arm.com>
+
+	* tree-vect-data-refs.c (vect_slp_analyze_node_dependences): Skip
+	unnecessary data dependence check after visited store stmt.
+
+2016-10-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	PR tree-optimization/71915
+	PR tree-optimization/71490
+	* gimple-ssa-strength-reduction.c (struct slsr_cand_d): Add
+	stride_type field.
+	(find_basis_for_base_expr): Require stride types to match when
+	seeking a basis.
+	(alloc_cand_and_find_basis): Record the stride type.
+	(slsr_process_phi): Pass stride type to alloc_cand_and_find_basis.
+	(backtrace_base_for_ref): Pass types to legal_cast_p_1 rather than
+	the expressions having those types.
+	(slsr_process_ref): Pass stride type to alloc_cand_and_find_basis.
+	(create_mul_ssa_cand): Likewise.
+	(create_mul_imm_cand): Likewise.
+	(create_add_ssa_cand): Likewise.
+	(create_add_imm_cand): Likewise.
+	(legal_cast_p_1): Change interface to accept types rather than the
+	expressions having those types.
+	(legal_cast_p): Pass types to legal_cast_p_1.
+	(slsr_process_cast): Pass stride type to
+	alloc_cand_and_find_basis.
+	(slsr_process_copy): Likewise.
+	(dump_candidate): Display stride type when a cast exists.
+	(create_add_on_incoming_edge): Introduce a cast when necessary for
+	the stride type.
+	(analyze_increments): Change the code checking for invalid casts
+	to rely on the stride type, and update the documentation and
+	example.  Change the code checking for pointer multiplies to rely
+	on the stride type.
+	(insert_initializers): Introduce a cast when necessary for the
+	stride type.  Use the stride type for the type of the initializer.
+
+2016-10-30  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	* config/arm/arm.c (arm_const_not_ok_for_debug_p): Use VAR_P.
+
+2016-10-29  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/77919
+	* expr.c (expand_expr_real_1) <normal_inner_ref>: Only avoid forcing
+	into memory if both modes are complex and their inner modes have the
+	same precision.  If the two modes are different complex modes, convert
+	each part separately and generate a new CONCAT.
+
+2016-10-29  John David Anglin  <danglin@gcc.gnu.org>
+
+	* config/pa/pa64-hpux.h (FINI_SECTION_ASM_OP): Define to null string.
+
+2016-10-29  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/78148
+	* gimple-ssa-store-merging.c
+	(imm_store_chain_info::output_merged_store): Use build_aligned_type
+	instead of SET_TYPE_ALIGN on shared integral type.
+
+2016-10-29  John David Anglin  <danglin@gcc.gnu.org>
+
+	* config/pa/pa.h (BIGGEST_ALIGNMENT): Adjust comment.
+	(MALLOC_ABI_ALIGNMENT): Define to 128 on all targets except SOM.
+	Adjust comment.
+
+2016-10-28  Jeff Law  <law@redhat.com>
+
+	* config/vax/vax.h (REGNO_REG_CLASS): Access the REGNO argument.
+	* config/spu/spu.h (REGNO_REG_CLASS): Likewise.
+
+2016-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* doc/sourcebuild.texi (Ada Tests): Remove mention of gcc chapter.
+
+2016-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* target.def (min_arithmetic_precision): New hook.
+	* doc/tm.texi.in (Misc): Add TARGET_MIN_ARITHMETIC_PRECISION.
+	* doc/tm.texi: Regenerate.
+	* internal-fn.c (expand_arith_overflow): Adjust handling of target
+	dependent support by means of TARGET_MIN_ARITHMETIC_PRECISION.
+	* targhooks.c (default_min_arithmetic_precision): New function.
+	* targhooks.h (default_min_arithmetic_precision): Declare.
+	* config/sparc/sparc.c (TARGET_MIN_ARITHMETIC_PRECISION): Define.
+	(sparc_min_arithmetic_precision): New function.
+
+2016-10-28  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/71847
+	* combine.c (change_zero_ext): Handle zero_ext of hard registers.
+	Swap commutative operands in new RTL if needed.  Handle zero_ext
+	in the set_dest.
+	(recog_for_combine): Pass *pnewpat to change_zero_ext instead of
+	PATTERN (insn).
+
+2016-10-28  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+	    Kugan Vivekanandarajah  <kuganv@linaro.org>
+	    Jim Wilson  <jim.wilson@linaro.org>
+
+	PR tree-optimization/43721
+	* target.def: New hook expand_divmod_libfunc.
+	* doc/tm.texi.in: Add hook for TARGET_EXPAND_DIVMOD_LIBFUNC.
+	* doc/tm.texi: Regenerate.
+	* internal-fn.def: Add new entry for DIVMOD ifn.
+	* internal-fn.c (expand_DIVMOD): New.
+	* tree-ssa-math-opts.c: Include optabs-libfuncs.h, tree-eh.h,
+	targhooks.h.
+	(widen_mul_stats): Add new field divmod_calls_inserted.
+	(target_supports_divmod_p): New.
+	(divmod_candidate_p): Likewise.
+	(convert_to_divmod): Likewise.
+	(pass_optimize_widening_mul::execute): Call calculate_dominance_info,
+	renumber_gimple_stmt_uids at beginning of function. Call
+	convert_to_divmod and record stats for divmod.
+	* config/arm/arm.c (arm_expand_divmod_libfunc): Override hook
+	TARGET_EXPAND_DIVMOD_LIBFUNC.
+	* doc/sourcebuild.texi: Add items for arm_divmod_simode, divmod,
+	divmod_simode.
+
+2016-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+	    Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* dojump.c (do_jump_by_parts_greater_rtx): Invert probability when
+	swapping the arms of the branch.
+	* internal-fn.c (expand_addsub_overflow): Use a straight-line code
+	sequence for the generic signed-signed-signed case.
+
+2016-10-28  Jeff Law  <law@redhat.com>
+
+	* config/bfin/bfin.c (bfin_legitimate_address_p): Add missing
+	fallthru comment.
+	* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Likewise.
+
+2016-10-28  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/78029
+	* function.c (prologue_contains, epilogue_contains): New functions.
+	(record_prologue_seq, record_epilogue_seq): New functions.
+	* function.h (prologue_contains, epilogue_contains,
+	record_prologue_seq, record_epilogue_seq): New declarations.
+	* sched-deps.c (sched_analyze_insn): Make dependencies to prevent
+	mixing prologue and epilogue insns.
+	(init_deps): Initialize the new fields in struct deps_desc.
+	* sched-int.h (struct deps_desc): New fields last_prologue,
+	last_epilogue, and last_logue_was_epilogue.
+	* shrink-wrap.c (emit_common_heads_for_components): Record all
+	emitted prologue and epilogue insns.
+	(emit_common_tails_for_components): Ditto.
+	(insert_prologue_epilogue_for_components): Ditto.
+
+2016-10-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR middle-end/22141
+	* Makefile.in (OBJS): Add gimple-ssa-store-merging.o.
+	* common.opt (fstore-merging): New Optimization option.
+	* opts.c (default_options_table): Add entry for
+	OPT_ftree_store_merging.
+	* fold-const.h (can_native_encode_type_p): Declare prototype.
+	* fold-const.c (can_native_encode_type_p): Define.
+	* params.def (PARAM_STORE_MERGING_ALLOW_UNALIGNED): Define.
+	(PARAM_MAX_STORES_TO_MERGE): Likewise.
+	* timevar.def (TV_GIMPLE_STORE_MERGING): New timevar.
+	* passes.def: Insert pass_tree_store_merging.
+	* tree-pass.h (make_pass_store_merging): Declare extern
+	prototype.
+	* gimple-ssa-store-merging.c: New file.
+	* doc/invoke.texi (Optimization Options): Document
+	-fstore-merging.
+	(--param documentation): Document store-merging-allow-unaligned
+	and max-stores-to-merge.
+
+2016-10-28  Will Schmidt <will_schmidt@vnet.ibm.com>
+
+	PR middle-end/72747
+	* gimplify.c (gimplify_init_constructor): Move emit of constructor
+	assignment to earlier in the if/else logic.
+
+2016-10-28  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/78128
+	PR middle-end/71002
+	* fold-const.c (make_bit_field_ref): Only adjust alias set
+	when the original alias set was zero.
+
+2016-10-28  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* config/s390/s390.c (s390_adjust_loop_scan_osc): New function.
+	(s390_adjust_loops): New function.
+	(s390_reorg): Invoke s390_adjust_loops.
+	* config/s390/s390.md (UNSPEC_OSC_BREAK): New constant.
+	("osc_break"): New insn definition.
+
+2016-10-28  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* config/s390/s390.opt: Support alternate cpu level naming (archXX).
+	* config.gcc: Support alternate archXX cpu levels with
+	--with-arch= and --with-tune=.
+	* config/s390/linux.h: Translate new archXX cpu levels to the
+	original names when calling GAS.
+	* config/s390/tpf.h: Likewise.
+	* doc/invoke.texi: Document the alternate cpu level names.
+
+2016-10-28  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/77919
+	* expr.c (expand_expr_real_1) <normal_inner_ref>: Force CONCAT into
+	MEM if mode1 is not a complex mode.
+
+	PR rtl-optimization/78132
+	* ree.c (combine_reaching_defs): Give up if copy_needed and
+	!HARD_REGNO_MODE_OK (REGNO (src_reg), dst_mode).
+
+2016-10-27  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc.md (<*vlop:code><VL:mode>3): Remove leading '*'.
+
+2016-10-27  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/constraints.md (wH constraint): Add new
+	constraints for allowing 32-bit integers (and eventually 8/16-bit
+	integers) into the vector registers.
+	(wI constraint): Likewise.
+	(wJ constraint): Likewise.
+	(wK constraint): Likewise.
+	* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
+	-mvsx-small-integer as a default option for ISA 2.07
+	(i.e. power8).
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.opt (-mvsx-small-integer): Add new debug
+	switch to turn off small integer support in vector registers.
+	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Eliminate
+	test for -mupper-regs-di, since it is already done with the
+	reg_add[mode].scalar_in_vsx_p.  Add support for the switch
+	-mvsx-small-integer.
+	(rs6000_debug_reg_global): Add support for wH, wI, wJ, and wK
+	constraints.
+	(rs6000_setup_reg_addr_masks): Likewise.
+	(rs6000_init_hard_regno_mode_ok): Likewise.
+	(rs6000_option_override_internal): Add consistency checks for
+	-mvsx-small-integer.
+	(rs6000_secondary_reload_simple_move): SImode is a simple move if
+	-mvsx-small-integer.
+	(rs6000_secondary_reload): Use std::swap.
+	(rs6000_preferred_reload_class): Don't prefer FLOAT_REGS over
+	VSX_REGS for small integers in vector registers, since there is no
+	D-FORM address mode for such types.
+	(rs6000_register_move_cost): Use FIRST_FPR_REGNO instead of 32.
+	(rs6000_opt_masks): Add -mvsx-small-integer.
+	* config/rs6000/vsx.md (VSINT_84): Add SImode for small integer
+	support.
+	(VSX_EXTRACT_I2): Clone VSX_EXTRACT_I, but drop V4SI since SImode
+	extracts can be done on ISA 2.07.
+	(vsx_extract_<mode>): Add support for small integers in vsx
+	registers.
+	(vsx_extract_<mode>_p9): Use 'v' instead of VSX_EX, since we no
+	longer support V4SImode in this pattern.
+	(vsx_extract_si): New insn to support extraction of SImode in ISA
+	2.07 using either xxextractuw or vspltw.
+	(vsx_extract_<mode>_p8): Use 'v' instead of VSX_EX, since we no
+	longer support V4SImode in this pattern.
+	* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wH, wI,
+	wJ, and wK constraints.
+	* config/rs6000/rs6000.md (f32_sv): Use correct instruction for
+	storing SDmode with VSX instructions.
+	(zero_extendsi<mode>2): Reorder pattern, so RLDICL comes after the
+	GPR load and before the FPR and VSX loads.  Remove ??, ! from the
+	constraints.  Add MFVSRWZ and XXEXTRACTUW instructions to support
+	small integers in vector registers.
+	(extendsi<mode>2): Reorder pattern, so EXTSW comes after the GPR
+	load and before the FPR and VSX loads.  Remove ??, ! from the
+	constraints.  Add VEXTSW2D support for small integers in vector
+	registers.
+	(lfiwax): Remove ! constraint.  Add VEXTSW2D support for small
+	integers in vector registers.
+	(floatsi<mode>2_lfiwax): If -mvsx-small-integer issue a normal
+	move instead of using an UNSPEC.
+	(lfiwzx): Remove ! constraint.  Add XXEXTRACTUW support for small
+	integers in vector registers.
+	(floatunssi<mode>2_lfiwzx): If -mvsx-small-integer issue a normal
+	move instead of using an UNSPEC.
+	(movsi_internal1): Add support for -mvsx-small-integer.  Align
+	columns so that it is more readable.
+	(SImode splitter for ISA 3.0 constants): Add splitter for
+	-128..127 constants that can easily be constructed on ISA 3.0.
+	* doc/md.texi (PowerPC Constraints): Document wH, wI, wJ, and wK
+	constraints.
+
+2016-10-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/78025
+	* omp-simd-clone.c (simd_clone_adjust): Handle noreturn declare simd
+	functions.
+
+2016-10-27  Aldy Hernandez  <aldyh@redhat.com>
+
+	* builtins.c (expand_builtin_nonlocal_goto): Avoid evaluating
+	PIC_OFFSET_TABLE_REGNUM twice.
+
+2016-10-27  Bin Cheng  <bin.cheng@arm.com>
+
+	* match.pd ((convert (op:s (convert@2 @0) (convert?@3 @1)))): Add
+	support for constant operand for OP.
+
+2016-10-27  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2out.c (gen_member_die): Only reparent_child instead of
+	splice_child_die if child doesn't have DW_AT_specification attribute.
+
+2016-10-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline.
+	(TARGET_HAVE_LDREXBH): Likewise.
+	(TARGET_HAVE_LDACQ): Likewise.
+
+2016-10-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.c (arm_split_atomic_op): Add function comment.  Add
+	logic to to decide whether to copy over old value to register for new
+	value.
+	* config/arm/sync.md: Add comments explaning why mode and code
+	attribute are not defined in iterators.md
+	(thumb1_atomic_op_str): New code attribute.
+	(thumb1_atomic_newop_str): Likewise.
+	(thumb1_atomic_fetch_op_str): Likewise.
+	(thumb1_atomic_fetch_newop_str): Likewise.
+	(thumb1_atomic_fetch_oldop_str): Likewise.
+	(atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to
+	mirror the more restrictive constraints of the Thumb-1 insns after
+	split compared to Thumb-2 counterpart insns.
+	(atomic_<sync_optab><mode>): Likewise.  Add comment to keep constraints
+	in sync with non atomic version.
+	(atomic_nand<mode>): Likewise.
+	(atomic_fetch_<sync_optab><mode>): Likewise.
+	(atomic_fetch_nand<mode>): Likewise.
+	(atomic_<sync_optab>_fetch<mode>): Likewise.
+	(atomic_nand_fetch<mode>): Likewise.
+	* config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint
+	in sync with atomic version.
+	(thumb1_subsi3_insn): Likewise.
+	(thumb1_andsi3_insn): Likewise.
+	(thumb1_iorsi3_insn): Likewise.
+	(thumb1_xorsi3_insn): Likewise.
+
+2016-10-27  Nick Clifton  <nickc@redhat.com>
+
+	* plugin.c (register_plugin_info): Produce an error message if the
+	plugin is not found in the hash table.
+
+2016-10-27  Bin Cheng  <bin.cheng@arm.com>
+
+	* match.pd ((convert1 (minmax ((convert2 (x) c)))) -> minmax (x c)):
+	New pattern.
+
+2016-10-26  Kelvin Nilsen  <kelvin@gcc.gnu.org>
+
+	PR target/78056
+	* config/rs6000/rs6000.c (spe_init_builtins): Modify loops to not
+	define builtin functions from the bdesc_spe_predicates or
+	bdesc_spe_evsel arrays if the builtin mask is not compatible with
+	the current compiler configuration.
+	(paired_init_builtins): Modify loop to not define define builtin
+	functions from the bdesc_paried_preds array if the builtin mask is
+	not compatible with the current compiler configuration.
+	(altivec_init_builtins): Modify loops to not define the
+	__builtin_altivec_stxvl function nor the builtin functions from
+	the bdesc_dst or bdesc_altivec_preds, or bdesc_abs arrays if the
+	builtin mask is not compatible with the current compiler
+	configuration.
+
+2016-10-26  Jeff Law  <law@redhat.com>
+
+	* config/sh/sh.c (output_branch): Add missing fallthru comments.
+	(gen_shl_and): Likewise.
+	* config/sh/sh.md (movsicc): Add missing fallthru comments.
+
+	* config/mips/mips.c (mips16_constant_cost): Add missing
+	fallthru comments.
+	(mips16_build_call_stub): Increase buffer size.  Adjust
+	fallthru comment.
+
+2016-10-26  David Malcolm  <dmalcolm@redhat.com>
+
+	* print-rtl.c (rtx_writer::print_rtx_operand_code_u): Print
+	INSN_UIDs for all insns in compact mode.
+	(rtx_writer::print_rtx): Likewise.
+	* print-rtl.h (rtx_writer::flag_compact): Update comment.
+	* rtl-tests.c (selftest::test_dumping_insns): Update expected
+	output to include INSN_UID.
+	(selftest::test_uncond_jump): Likewise.
+
+2016-10-26  Pat Haugen  <pthaugen@us.ibm.com>
+
+	* haifa-sched.c (call_used_regs_num): Rename to...
+	(call_saved_regs_num): ...this.
+	(fixed_regs_num): New variable.
+	(sched_pressure_start_bb): Subtract out fixed_regs. Scale call_saved
+	regs not call_used.
+	(alloc_global_sched_pressure_data): Compute call_saved and fixed regs.
+
+2016-10-26  David Malcolm  <dmalcolm@redhat.com>
+
+	* print-rtl-function.c (print_rtx_function): Rewrite in terms of
+	class rtx_writer.
+	* print-rtl.c (outfile): Delete global.
+	(sawclose): Likewise.
+	(indent): Likewise.
+	(in_call_function_usage): Likewise.
+	(flag_compact): Likewise.
+	(flag_simple): Likewise.
+	(rtx_writer::rtx_writer): New ctor.
+	(print_rtx_operand_code_0): Convert to...
+	(rtx_writer::print_rtx_operand_code_0): ...this.
+	(print_rtx_operand_code_e): Convert to...
+	(rtx_writer::print_rtx_operand_code_e): ...this.
+	(print_rtx_operand_codes_E_and_V): Convert to...
+	(rtx_writer::print_rtx_operand_codes_E_and_V): ...this.
+	(print_rtx_operand_code_i): Convert to...
+	(rtx_writer::print_rtx_operand_code_i): ...this.
+	(print_rtx_operand_code_r): Convert to...
+	(rtx_writer::print_rtx_operand_code_r): ...this.
+	(print_rtx_operand_code_u): Convert to...
+	(rtx_writer::print_rtx_operand_code_u): ...this.
+	(print_rtx_operand): Convert to...
+	(rtx_writer::print_rtx_operand): ...this.
+	(print_rtx): Convert to...
+	(rtx_writer::print_rtx): ...this.
+	(print_inline_rtx): Rewrite in terms of class rtx_writer.
+	(debug_rtx): Likewise.
+	(print_rtl): Convert to...
+	(rtx_writer::print_rtl): ...this.
+	(print_rtl): Reimplement in terms of class rtx_writer.
+	(print_rtl_single): Rewrite in terms of class rtx_writer.
+	(print_rtl_single_with_indent): Convert to..
+	(rtx_writer::print_rtl_single_with_indent): ...this.
+	(print_simple_rtl): Rewrite in terms of class rtx_writer.
+	* print-rtl.h (flag_compact): Delete decl.
+	(class rtx_writer): New class.
+	* rtl-tests.c (selftest::assert_rtl_dump_eq): Rewrite in terms of
+	class rtx_writer.
+
+2016-10-26  Jeff Law  <law@redhat.com>
+
+	* config/microblaze/microblaze.c (tls_mentioned_p): Avoid
+	fallthru.
+
+	* config/arc/arc.c (acr_print_operand): Adjust fallthru comment.
+	(check_if_valid_sleep_operand): Add missing fallthru comment.
+	(arc_register_move_cost): Increase buffer size.
+	* config/arc/arc.md (cbranch4si_scratch): Add missing fallthru
+	comment.
+	* config/arc/predicates.md (move_str_operand): Avoid fallthru.
+
+	* config/cr16/cr16.c (cr16_print_operand): Add missing fallthru
+	comment.  Add gcc_unreachable for path that should never happen.
+
+	* config/epiphany/epiphany.c (epiphany_print_operand): Adjust
+	fallthru comment.
+
+2016-10-26  Jakub Jelinek  <jakub@redhat.com>
+	    Martin Liska  <mliska@suse.cz>
+
+	PR fortran/77973
+	* gimplify.c (gimplify_adjust_omp_clauses_1): For all added map
+	clauses with OMP_CLAUSE_SIZE being a decl, call omp_notice_variable
+	on outer context if any.
+
+2016-10-26  Jakub Jelinek  <jakub@redhat.com>
+
+	* gen-pass-instances.awk (adjust_linenos): Increment pass_lines[p]
+	by increment rather than double it.
+	(insert_remove_pass): Strip leading whitespace from args[3].  Don't
+	emit a space before args[4].
+	(END): Don't emit a space before with_arg.
+
+2016-10-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/sync.md (atomic_compare_and_swap<mode>_1): Add new ARMv8-M
+	Baseline only alternatives to (i) hold store atomic success value in a
+	return register rather than a scratch register, (ii) use a low register
+	for it and to (iii) ensure the cbranchsi insn generated by the split
+	respect the constraints of Thumb-1 cbranchsi4_insn and
+	cbranchsi4_scratch.
+	* config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate
+	constraints must match those in atomic_compare_and_swap.
+	(cbranchsi4_scratch): Likewise.
+
+2016-10-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm.c (arm_expand_compare_and_swap): Add new bdst local
+	variable.  Add the new parameter to the insn generator.  Set that
+	parameter to be CC flag for 32-bit targets, bval otherwise.  Set the
+	return value from the negation of that parameter for Thumb-1, keeping
+	the logic unchanged otherwise except for using bdst as the destination
+	register of the compare_and_swap insn.
+	(arm_split_compare_and_swap): Add explanation about how is the value
+	returned to the function comment.  Rename scratch variable to
+	neg_bval.  Adapt initialization of variables holding operands to the
+	new operand numbers.  Use return register to hold result of store
+	exclusive for Thumb-1, scratch register otherwise.  Construct the
+	appropriate cbranch for Thumb-1 targets, keeping the logic unchanged
+	for 32-bit targets.  Guard Z flag setting to restrict to 32bit targets.
+	Use gen_cbranchsi4 rather than hand-written conditional branch to loop
+	for strongly ordered compare_and_swap.
+	* config/arm/predicates.md (cc_register_operand): New predicate.
+	* config/arm/sync.md (atomic_compare_and_swap<mode>_1): Use a
+	match_operand with the new predicate to accept either the CC flag or a
+	destination register for the boolean return value, restricting it to
+	CC flag only via constraint.  Adapt operand numbers accordingly.
+
+2016-10-26  Jeff Law  <law@redhat.com>
+
+	* config/fr30/fr30.c (fr30_print_operand): Adjust fallthru comment.
+
+	* config/frv/frv.c (comparison_string): Do not fall through after
+	an error.
+
+	* config/iq2000/iq2000.c (iq2000_function_arg): Adjust fallthru
+	comment.
+	(expand_one_builtin): Add missing break.
+
+	* config/m32c/m32c.c (encode_pattern_1): Add fallthru comment.
+	(m32c_legitimate_address_p): Likewise.
+
+	* config/m32r/m32r.c (m32r_print_operand): Adjust fallthru comment.
+
+	* config/mcore/mcore.c (mcore_gen_compare): Adjust fallthru comments.
+
+	* config/microblaze/microblaze.c (microblaze_function_arg): Adjust
+	fallthru comment.
+
+	* config/msp430/msp430.c (msp430_legitimate_address_p): Adjust
+	fallthru comment.
+
+	* config/nios2/nios2.c (nios2_rtx_costs): Avoid fallthru.
+
+	* config/rl78/rl78.c (rl78_calculate_death_notes): Add fallthru
+	comment.
+	(rl78_asm_ctor_dtor): Increase buffer size.
+
+	* config/stormy16/stormy16.c (xstormy16_asm_output_destrutor): Increase
+	buffer size.
+	(xstormy16_asm_output_constructor): Likewise.
+
+	* config/pa/pa.c (pa_asm_output_mi_thunk): Increase buffer
+	size.
+
+	* config/h8300/h8300.c (h8300_print_operand): Adjust FALLTHRU
+	comment to silence warning.
+
+	* config/spu/spu.c (spu_sched_reorder): Add missing fallthru comment.
+	(spu_legitimate_address_p): Fix logic error and add missing fallthru
+	comment.
+
+2016-10-26  Michael Matz  <matz@suse.de>
+
+	PR tree-optimization/78060
+	PR tree-optimization/78061
+	PR tree-optimization/78088
+	* tree-ssa-loop-split.c (easy_exit_values): New function.
+	(tree_ssa_split_loops): Use it.
+	(compute_new_first_bound): Change order of operations,
+	fix invalid use of types.
+
+2016-10-26  Georg-Johann Lay  <avr@gjlay.de>
+
+	gen-pass-instances.awk is sensitive to the order in which
+	passes are added; passes that appear later have to be added first.
+
+	PR target/71676
+	PR target/71678
+	* config/avr/avr-passes.def: Swap order of directives for
+	gen-pass-instances.awk.
+
+2016-10-25  Jeff Law  <law@redhat.com>
+
+	* config/vax/vax.c (vad_address_cost_1): Add missing FALLTHRU comment.
+	(vax_notice_update_cc): Likewise.
+
+2016-10-25  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config.gcc (sparc*-*-solaris2*): Adjust.
+	(sparc64-*-linux*): Likewise.
+	* config/sparc/default-64.h: Rename to...
+	* config/sparc/default64.h: ...this.
+	* config/sparc/sparc.c (sparc_option_override): Replace TARGET_64BIT
+	with TARGET_ARCH64.
+	(sparc_mangle_type): Replace !TARGET_64BIT with TARGET_ARCH32.
+	* config/sparc/sparc.h: Minor tweaks.
+	* config/sparc/sparc.md: Replace !TARGET_64BIT and !TARGET_ARCH64 with
+	TARGET_ARCH32 throughout.  Minor various tweaks throughout.
+
+2016-10-25  David Malcolm  <dmalcolm@redhat.com>
+
+	* input.c (fcache::file_patch): Add comment about lifetime.
+	(selftest::cpp_reader_ptr): New class.
+	(selftest::lexer_test): Convert m_parser from cpp_reader *
+	to a cpp_reader_ptr, and move m_tempfile to after it.
+	(selftest::lexer_test::lexer_test): Update for above reordering.
+	(lexer_test::~lexer_test): Move cleanup of m_parser to
+	cpp_reader_ptr's dtor.
+
+2016-10-25  David Malcolm  <dmalcolm@redhat.com>
+
+	* toplev.c (toplev::main): Remove call to
+	location_adhoc_data_fini.
+
+2016-10-25  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* tree.h (wi::fits_to_tree_p): Accept only 0 and 1 for boolean types.
+	* tree.c (int_fits_type_p): Likewise.  Adjust head comment.
+
+2016-10-25  David Malcolm  <dmalcolm@redhat.com>
+
+	* ggc-tests.c (forcibly_ggc_collect): Rename to...
+	(selftest::forcibly_ggc_collect): ...this, and remove "static".
+	(test_basic_struct): Update for above renaming.
+	(test_length): Likewise.
+	(test_union): Likewise.
+	(test_finalization): Likewise.
+	(test_deletable_global): Likewise.
+	(test_inheritance): Likewise.
+	(test_chain_next): Likewise.
+	(test_user_struct): Likewise.
+	(test_tree_marking): Likewise.
+	* selftest-run-tests.c (selftest::run_tests): Call
+	selftest::forcibly_ggc_collect at the end of the selftests.
+	* selftest.h (selftest::forcibly_ggc_collect): New decl.
+
+2016-10-25  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/78102
+	* optabs.def (vcondeq_optab, vec_cmpeq_optab): New optabs.
+	* optabs.c (expand_vec_cond_expr): For comparison codes
+	EQ_EXPR and NE_EXPR, attempt vcondeq_optab as fallback.
+	(expand_vec_cmp_expr): For comparison codes
+	EQ_EXPR and NE_EXPR, attempt vec_cmpeq_optab as fallback.
+	* optabs-tree.h (expand_vec_cmp_expr_p, expand_vec_cond_expr_p):
+	Add enum tree_code argument.
+	* optabs-query.h (get_vec_cmp_eq_icode, get_vcond_eq_icode): New
+	inline functions.
+	* optabs-tree.c (expand_vec_cmp_expr_p): Add CODE argument.  For
+	CODE EQ_EXPR or NE_EXPR, attempt to use vec_cmpeq_optab as
+	fallback.
+	(expand_vec_cond_expr_p): Add CODE argument.  For CODE EQ_EXPR or
+	NE_EXPR, attempt to use vcondeq_optab as fallback.
+	* tree-vect-generic.c (expand_vector_comparison,
+	expand_vector_divmod, expand_vector_condition): Adjust
+	expand_vec_cmp_expr_p and expand_vec_cond_expr_p callers.
+	* tree-vect-stmts.c (vectorizable_condition,
+	vectorizable_comparison): Likewise.
+	* tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern,
+	check_bool_pattern, search_type_for_mask_1): Likewise.
+	* expr.c (do_store_flag): Likewise.
+	* doc/md.texi (@code{vec_cmpeq@var{m}@var{n}},
+	@code{vcondeq@var{m}@var{n}}): Document.
+	* config/i386/sse.md (vec_cmpeqv2div2di, vcondeq<VI8F_128:mode>v2di):
+	New expanders.
+
+2016-10-25  Jeff Law  <law@redhat.com>
+
+	* config/v850/v850.c (v850_handle_data_area_attribute): Fix fallthru
+	comment.
+	(v850_output_aligned_bss): Add missing break.
+
+	* config/m68k/m68k.c (m68k_get_reloc_decoration): Add gcc_unreachable.
+
+2016-10-25  Martin Liska  <mliska@suse.cz>
+
+	PR sanitizer/78106
+	* sanopt.c (imm_dom_path_with_freeing_call): Handle gasm
+	statements as they can also contain possibly a freeing call.
+
+2016-10-25  H.J. Lu  <hongjiu.lu@intel.com>
+	    Martin Liska  <mliska@suse.cz>
+
+	PR ipa/78099
+	* common.opt: Mark flag_ipa_icf_variables as Optimization flag.
+	* ipa-icf.c (sem_function::get_hash): Add target optimization
+	node to hash.
+
+2016-10-25  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	PR target/78041
+	* config/arm/neon.md (ashldi3_neon): Add "r 0 i" and "&r r i" variants.
+	Remove partial overlap check for shift by 1.
+	(ashldi3_neon): Likewise.
+
+2016-10-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/constraints.md (Q constraint): Document its use for
+	Thumb-1.
+	(Pf constraint): New constraint for relaxed, consume or relaxed memory
+	models.
+	* config/arm/sync.md (atomic_load<mode>): Add new ARMv8-M Baseline only
+	alternatives to allow any register when memory model matches Pf and
+	thus lda is used, but only low registers otherwise.  Use unpredicated
+	output template for Thumb-1 targets.
+	(atomic_store<mode>): Likewise for stl.
+	(arm_load_exclusive<mode>): Add new ARMv8-M Baseline only alternative
+	whose output template does not have predication.
+	(arm_load_acquire_exclusive<mode>): Likewise.
+	(arm_load_exclusivesi): Likewise.
+	(arm_load_acquire_exclusivesi): Likewise.
+	(arm_store_release_exclusive<mode>): Likewise.
+	(arm_store_exclusive<mode>): Use unpredicated output template for
+	Thumb-1 targets.
+
+2016-10-25  Jakub Jelinek  <jakub@redhat.com>
+
+	* internal-fn.def (LAUNDER): New internal function.
+	* internal-fn.c (expand_LAUNDER): New function.
+
+2016-10-25  Georg-Johann Lay  <avr@gjlay.de>
+	    Pitchumani Sivanupandi  <pitchumani.sivanupandi@microchip.com>
+
+	New avr target pass to work around performance loss by PR fix.
+
+	PR target/71676
+	PR target/71678
+	* config/avr/avr.md (casesi_<mode>_sequence) [qi,hi]: New insn.
+	(*cmp<mode>) [qi,qq,uqq,hi,hq,uhq,ha,uha]: Rename to cmp<mode>3.
+	* config/avr/predicates.md (extend_operator): New.
+	* config/avr/avr-passes.def (avr_pass_casesi): Register new pass.
+	* config/avr/avr-protos.h (avr_casei_sequence_check_operands)
+	(make_avr_pass_casesi): New prototypes.
+	* config/avr/avr.c (print-rtl.h): Include it.
+	(pass_data avr_pass_data_casesi): Data for new pass.
+	(avr_pass_casesi): New class implementing rtl_opt_pass .avr-casesi.
+	(make_avr_pass_casesi, avr_parallel_insn_from_insns)
+	(avr_is_casesi_sequence, avr_casei_sequence_check_operands)
+	(avr_optimize_casesi): New functions.
+
+2016-10-25  Georg-Johann Lay  <avr@gjlay.de>
+	    Pitchumani Sivanupandi  <pitchumani.sivanupandi@microchip.com>
+
+	PR target/71676
+	PR target/71678
+	* config/avr/avr.md (casesi): Rewrite avoiding subregs of SI.
+
+2016-10-24  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2out.c (gen_subprogram_die): Add DW_AT_reference or
+	DW_AT_rvalue_reference attributes.
+
+2016-10-24  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	* doc/invoke.text (Wint-in-bool-context): Update documentation.
+	* value-prof.c (stringop_block_profile): Fix a warning.
+
+2016-10-24  Martin Sebor  <msebor@redhat.com>
+
+	PR middle-end/77735
+	* builtins.c (string_length): New function.
+	(c_strlen): Use string_length.  Correctly handle wide strings.
+	* gimple-ssa-sprintf.c (target_max_value, target_size_max): New
+	functions.
+	(target_int_max): Call target_max_value.
+	(format_result::knownrange): New data member.
+	(fmtresult::fmtresult): Define default constructor.
+	(format_integer): Use it and set format_result::knownrange.
+	Handle global constants.
+	(format_floating_max): Add third argument.
+	(format_floating): Recompute maximum value for %a for each argument.
+	(get_string_length): Use fmtresult default ctor.
+	(format_string): Set format_result::knownrange.
+	(format_directive): Check format_result::knownrange.
+	(add_bytes): Same.  Correct caret placement in diagnostics.
+	(pass_sprintf_length::compute_format_length): Set
+	format_result::knownrange.
+	(pass_sprintf_length::handle_gimple_call): Use target_size_max.
+
+2016-10-24  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/i386.c (ix86_in_large_data_p, ix86_expand_builtin): Use
+	VAR_P (x) instead of TREE_CODE (x) == VAR_DECL.
+
+2016-10-24  Ximin Luo  <infinity0@pwned.gg>
+
+	PR debug/77985
+	* dwarf2out.c (file_table_relative_p): Remove.
+	(gen_compile_unit_die, dwarf2out_early_finish): Emit DW_AT_comp_dir
+	also for absolute paths.
+	* doc/tm.texi: Update.
+	* doc/tm.texi.in (SDB and DWARF) <TARGET_FORCE_AT_COMP_DIR>: Remove.
+	* target.def (force_at_comp_dir): Remove hook.
+	* config/darwin.h (TARGET_FORCE_AT_COMP_DIR): Remove define.
+
+2016-10-24  Richard Biener  <rguenther@suse.de>
+
+	* tree-vrp.c (evrp_dom_walker::before_dom_children): Ignore
+	backedges when identifying the single predecessor to take
+	conditional info from.  Use SCEV to get at ranges for loop IVs.
+	* lto-streamer-out.c (lto_write_mode_table): CSE inner mode to
+	avoid false warning.
+
+2016-10-24  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/78093
+	* doc/extend.texi (AVR Variable Attributes) [absdata]: Document it.
+	* config/avr/avr.c (AVR_SYMBOL_FLAG_TINY_ABSDATA): New macro.
+	(avr_address_tiny_absdata_p): New static function.
+	(avr_legitimate_address_p, avr_legitimize_address) [AVR_TINY]: Use
+	it to determine validity of constant addresses.
+	(avr_attribute_table) [absdata]: New variable attribute...
+	(avr_handle_absdata_attribute): ...and handler.
+	(avr_decl_absdata_p): New static function.
+	(avr_encode_section_info) [AVR_TINY]: Use it to add flag
+	AVR_SYMBOL_FLAG_TINY_ABSDATA to respective symbols_refs.
+	(avr_address_cost) [AVR_TINY]: absdata addresses cost 2.
+
+2016-10-24  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78076
+	* tree-ssa-loop-split.c (tree_ssa_split_loops): Reset aux
+	also on the loop tree root.
+
+2016-10-24  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/i386.c (ix86_fold_builtin): Handle
+	IX86_BUILTIN_BEXTR{,I}{32,64}, IX86_BUILTIN_BZHI{32,64},
+	IX86_BUILTIN_PDEP{32,64} and IX86_BUILTIN_PEXT{32,64}.
+	(ix86_gimple_fold_builtin): Handle IX86_BUILTIN_BZHI{32,64},
+	IX86_BUILTIN_PDEP{32,64} and IX86_BUILTIN_PEXT{32,64}.
+
+2016-10-24  Martin Liska  <mliska@suse.cz>
+
+	PR sanitizer/77966
+	* opts.c (finish_options): Skip conditionally.
+
+2016-10-23  Martin Sebor  <msebor@redhat.com>
+
+	PR target/77837
+	* config/rs6000/linux.h (TARGET_PRINTF_POINTER_FORMAT): Define.
+	* config/rs6000/linux64.h (TARGET_PRINTF_POINTER_FORMAT): Likewise.
+
+2016-10-23  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc.md (cpu_feature): Minor tweak.
+	(enabled): Likewise.
+	(movsi_insn, movdi_insn_sp32, movdi_insn_sp64, movsf_insn,
+	movdf_insn_sp32, movdf_insn_sp64, zero_extendsidi2_insn_sp64,
+	sign_extendsidi2_insn, mov<VM32:mode>_insn, mov<VM64:mode>_insn_sp64,
+	mov<VM64:mode>_insn_sp32, not_<code><mode>, nand<mode>_vis,
+	<code>_not1<mode>_vi, <code>_not2<mode>_vis, one_cmpl<mode>2,
+	fcmp<code><GCM:gcm_name>, pdistn<mode>_vis): Likewise.
+
+2016-10-23  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc-c.c (sparc_target_macros): Replace TARGET_64BIT
+	with TARGET_ARCH64.  Define __VIS to 0x400 if TARGET_VIS4.
+
+2016-10-21  Andrew Pinski  <apinski@cavium.com>
+
+	* config/aarch64/aarch64-cores.def: Rewrite so IMP and PART are
+	integer constants.
+	* config/aarch64/driver-aarch64.c (struct aarch64_core_data): Change
+	implementer_id to unsigned char.
+	Change part_no to unsigned int.
+	(AARCH64_BIG_LITTLE): New define.
+	(INVALID_IMP): New define.
+	(INVALID_CORE): New define.
+	(cpu_data): Change the last element's implementer_id and part_no to
+	integers.
+	(valid_bL_string_p): Rewrite to ..
+	(valid_bL_core_p): this for integers instead of strings.
+	(parse_field): New function.
+	(contains_string_p): Rewrite to ...
+	(contains_core_p): this for integers and only for the part_no.
+	(host_detect_local_cpu): Rewrite handling of implementation and
+	par num to be integers; simplifying the code.
+
+2016-10-21  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* ipa-prop.c (ipa_compute_jump_functions_for_edge): Create nonzero
+	value range for pointers in more cases.
+
+2016-10-21  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_add_constant_internal):
+	Add extra argument to allow emitting the move immediate.
+	Use add/sub with positive immediate.
+	(aarch64_add_constant): Add inline function.
+	(aarch64_add_sp): Likewise.
+	(aarch64_sub_sp): Likewise.
+	(aarch64_expand_prologue): Call aarch64_sub_sp.
+	(aarch64_expand_epilogue): Call aarch64_add_sp.
+	Decide when to leave out move.
+	(aarch64_output_mi_thunk): Call aarch64_add_constant.
+
+2016-10-21  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_layout_frame):
+	Align FP callee-saves.
+
+2016-10-21  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/adxintrin.h (_subborrow_u32, _addcarry_u32,
+	_addcarryx_u32, _subborrow_u64, _addcarry_u64, _addcarryx_u64):
+	Formatting fixes.
+	* config/i386/rdseedintrin.h (_rdseed16_step, _rdseed32_step,
+	_rdseed64_step): Likewise.
+	* config/i386/tbmintrin.h (__bextri_u32): Likewise.
+
+	PR target/78057
+	* config/i386/i386.c: Include fold-const-call.h, tree-vrp.h
+	and tree-ssanames.h.
+	(ix86_fold_builtin): Fold IX86_BUILTIN_[LT]ZCNT{16,32,64}
+	with INTEGER_CST argument.
+	(ix86_gimple_fold_builtin): New function.
+	(TARGET_GIMPLE_FOLD_BUILTIN): Define.
+
+	* dwarf2out.c (ranges_table): Change into vec<dw_ranges, va_gc> *.
+	(ranges_by_label): Change into vec<dw_ranges_by_label, va_gc> *.
+	(ranges_table_allocated, ranges_table_in_use,
+	ranges_by_label_allocated, ranges_by_label_in_use,
+	RANGES_TABLE_INCREMENT): Removed.
+	(add_ranges_num): Use vec_safe_push into ranges_table.
+	(add_ranges_by_labels): Use vec_safe_push into ranges_by_label.
+	(output_ranges): Adjust for ranges_table and ranges_by_label
+	conversion from arrays to vec.
+	(add_high_low_attributes, dwarf2out_finish): Adjust for range_table
+	conversion from arrays to vec.
+	(dwarf2out_c_finalize): Don't clear ranges_table_allocated,
+	ranges_table_in_use, ranges_by_label_allocated and
+	ranges_by_label_in_use.  Set ranges_by_label to NULL instead of 0.
+
+	* dwarf2out.c (gen_variable_die): Emit DW_AT_const_expr attribute
+	if needed.  Re-add origin_die variable and its initialization.
+
+	* gimplify.c (gimplify_bind_expr): Handle oacc_declare_returns
+	even for -fstack-reuse=none, or for volatile vars etc.
+
+2016-10-21  David Malcolm  <dmalcolm@redhat.com>
+
+	* print-rtl-function.c (flag_compact): Move extern decl to...
+	* print-rtl.h (flag_compact): ...here.
+	* rtl-tests.c (selftests::assert_rtl_dump_eq): New function.
+	(ASSERT_RTL_DUMP_EQ): New macro.
+	(selftest::test_dumping_regs): New function.
+	(selftest::test_dumping_insns): New function.
+	(selftest::test_uncond_jump): Add uses of ASSERT_RTL_DUMP_EQ on
+	the insns.
+	(selftest::rtl_tests_c_tests): Call the new test functions.
+
+2016-10-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* cfgcleanup.c (merge_blocks_move_successor_nojumps): Adjust.
+	(outgoing_edges_match): Likewise.
+	(try_crossjump_to_edge): Likewise.
+	* cfgrtl.c (try_redirect_by_replacing_jump): Likewise.
+	(rtl_tidy_fallthru_edge): Likewise.
+	* rtl.h (tablejump_p): Adjust prototype.
+	* rtlanal.c (tablejump_p): Return the label as a rtx_insn *.
+
+2016-10-21  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
+	* rtl.h (label_ref_label): New function.
+	(set_label_ref_label): New function.
+	(LABEL_REF_LABEL): Delete.
+	* alias.c (rtx_equal_for_memref_p): Adjust.
+	* cfgbuild.c (make_edges): Likewise.
+	(purge_dead_tablejump_edges): Likewise.
+	* cfgexpand.c (convert_debug_memory_address): Likewise.
+	* cfgrtl.c (patch_jump_insn): Likewise.
+	* combine.c (distribute_notes): Likewise.
+	* cse.c (hash_rtx_cb): Likewise.
+	(exp_equiv_p): Likewise.
+	(fold_rtx): Likewise.
+	(check_for_label_ref): Likewise.
+	* cselib.c (rtx_equal_for_cselib_1): Likewise.
+	(cselib_hash_rtx): Likewise.
+	* emit-rtl.c (mark_label_nuses): Likewise.
+	* explow.c (convert_memory_address_addr_space_1): Likewise.
+	* final.c (output_asm_label): Likewise.
+	(output_addr_const): Likewise.
+	* gcse.c (add_label_notes): Likewise.
+	* genconfig.c (walk_insn_part): Likewise.
+	* genrecog.c (validate_pattern): Likewise.
+	* ifcvt.c (cond_exec_get_condition): Likewise.
+	(noce_emit_store_flag): Likewise.
+	(noce_get_alt_condition): Likewise.
+	(noce_get_condition): Likewise.
+	* jump.c (maybe_propagate_label_ref): Likewise.
+	(mark_jump_label_1): Likewise.
+	(redirect_exp_1): Likewise.
+	(rtx_renumbered_equal_p): Likewise.
+	* lra-constraints.c (operands_match_p): Likewise.
+	* print-rtl.c (print_value): Likewise.
+	* reload.c (find_reloads): Likewise.
+	* reload1.c (set_label_offsets): Likewise.
+	* reorg.c (get_branch_condition): Likewise.
+	* rtl-tests.c (test_uncond_jump): Likewise.
+	* rtl.c (rtx_equal_p_cb): Likewise.
+	(rtx_equal_p): Likewise.
+	* rtlanal.c (reg_mentioned_p): Likewise.
+	(rtx_referenced_p): Likewise.
+	(get_condition): Likewise.
+	* varasm.c (const_hash_1): Likewise.
+	(compare_constant): Likewise.
+	(const_rtx_hash_1): Likewise.
+	(output_constant_pool_1): Likewise.
+
+2016-10-21  Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
+
+	PR target/71627
+	* reload.c (find_valid_class_1): Allow regclass if atleast one
+	regno in regclass is ok. Compute and use rclass size based on
+	actually available regnos for mode in rclass.
+
+2016-10-21  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc-modes.def (CCV): New.
+	(CCXV): Likewise.
+	* config/sparc/predicates.md (v_comparison_operator): New.
+	(icc_comparison_operator): Add support for CCV/CCXV.
+	(xcc_comparison_operator): Likewise.
+	* config/sparc/sparc.c (output_cbranch): Likewise.
+	(sparc_print_operand): Likewise.
+	* config/sparc/sparc.md (UNSPEC_{ADD,SUB,NEG}V): New constants.
+	(uaddvdi4): New expander.
+	(addvdi4): Likewise.
+	(uaddvdi4_sp32): New instruction.
+	(addvdi4_sp32): Likewise.
+	(uaddvsi4): New expander.
+	(addvsi4): Likewise.
+	(cmp_ccc_plus_sltu_set): New instruction.
+	(cmp_ccv_plus): Likewise.
+	(cmp_ccxv_plus): Likewise.
+	(cmp_ccv_plus_set): Likewise.
+	(cmp_ccxv_plus_set): Likewise.
+	(cmp_ccv_plus_sltu_set): Likewise.
+	(uaddvdi4): New expander.
+	(subvdi4): Likewise.
+	(usubdi4_sp32): New instruction.
+	(subvdi4_sp32): Likewise.
+	(usubvsi4): New expander.
+	(subvsi4): Likewise.
+	(cmpsi_minus_sltu_set): New instruction.
+	(cmp_ccv_minus): Likewise.
+	(cmp_ccxv_minus): Likewise.
+	(cmp_ccv_minus_set): Likewise.
+	(cmp_ccxv_minus_set): Likewise.
+	(cmp_ccv_minus_sltu_set): Likewise.
+	(unegvdi3): New expander.
+	(negvdi3): Likewise.
+	(unegdi3_sp32): New instruction.
+	(negvdi3_sp32): Likewise.
+	(unegvsi3): New expander.
+	(negvsi3): Likewise.
+	(cmp_ccc_neg_sltu_set): New instruction.
+	(cmp_ccv_neg): Likewise.
+	(cmp_ccxv_neg): Likewise.
+	(cmp_ccv_neg_set): Likewise.
+	(cmp_ccxv_neg_set): Likewise.
+	(cmp_ccv_neg_sltu_set): Likewise.
+
+	* tree-ssa-loop-split.c: Remove trailing spaces.
+	* match.pd: Likewise.
+
+2016-10-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR rtl-optimization/78038
+	* ree.c (get_defs): Return NULL if a defining insn for REG cannot
+	be deduced to set REG through the RTL structure.
+	(make_defs_and_copies_lists): Return false on a failing get_defs call.
+
+2016-10-21  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/78051
+	* tree-vrp.c (evrp_dom_walker::before_dom_children): Update stmt
+	and mark replaced if folding did something.
+
+2016-10-21  David Edelsohn  <dje.gcc@gmail.com>
+
+	* config/rs6000/rs6000.c (rs6000_assemble_visibility): Swap "internal"
+	and "protected" in visibility types.
+	(rs6000_xcoff_declare_function_name): Fix formatting.
+	(rs6000_xcoff_declare_object_name): Fix formatting.
+
+2016-10-21  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.c (ix86_fold_builtin): Handle IX86_BUILTIN_INFQ
+	and IX86_BUILTIN_HUGE_VALQ here ...
+	(ix86_expand_builtin): ... not here.
+
+2016-10-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* doc/gty.texi (for_user): Use @item next to @findex.
+
+2016-10-20  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/78037
+	* config/i386/bmiintrin.h (__tzcnt_u16): Call __builtin_ia32_tzcnt_u16.
+	(__tzcnt_u32, _tzcnt_u32): Call __builtin_ia32_tzcnt_u32.
+	(__tzcnt_u64, _tzcnt_u64): Call __builtin_ia32_tzcnt_u64.
+	* config/i386/lzcntintrin.h (__lzcnt_u16): Call
+	__builtin_ia32_lzcnt_u16.
+	(__lzcnt_u32, _lzcnt_u32): Call __builtin_ia32_lzcnt_u32.
+	(__lzcnt_u64, _lzcnt_u64): Call __builtin_ia32_lzcnt_u64.
+	* config/i386/i386.md (UNSPEC_LZCNT, UNSPEC_TZCNT): New unspecs.
+	(ctz<mode>2, *ctz<mode>2): Use SWI48 mode iterator.
+	(bmi_tzcnt_<mode>): New expander.
+	(*bmi_tzcnt_<mode>_falsedep_1): New define_insn_and_split pattern.
+	(*bmi_tzcnt_<mode>_falsedep, *bmi_tzcnt_<mode>): New insn patterns.
+	(clz<mode>2_lzcnt, *clz<mode>2_lzcnt): Use SWI48 mode iterator.
+	(lzcnt_<mode>): New expander.
+	(*lzcnt_<mode>_falsedep_1): New define_insn_and_split pattern.
+	(*lzcnt_<mode>_falsedep, *lzcnt_<mode>): New insn patterns.
+	* config/i386/i386-builtin-types.def (UINT_FTYPE_UINT): New.
+	(UINT64_FTYPE_UINT64): New.
+	* config/i386/i386-builtin.def (__builtin_clzs): Remove description.
+	(__builtin_ia32_lzcnt_u16): New description.
+	(__builtin_ia32_lzcnt_u32): Ditto.
+	(__builtin_ia32_lzcnt_u64): Ditto.
+	(__builtin_ctzs): Remove description.
+	(__builtin_ia32_tzcnt_u16): New description.
+	(__builtin_ia32_tzcnt_u32): Ditto.
+	(__builtin_ia32_tzcnt_u64): Ditto.
+	* config/i386/i386.c (ix86_expand_args_builtin): Handle
+	UINT_FTYPE_UINT and UINT64_FTYPE_UINT64.
+
+2016-10-20  Martin Liska  <mliska@suse.cz>
+
+	PR lto/78049
+	* lto-streamer-in.c (fixup_call_stmt_edges_1): Replace value
+	comparison with STMT_UID_NOT_IN_RANGE.
+	(fixup_call_stmt_edges): Do not fixup edges of a thunk in
+	LTRANS.
+
+2016-10-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* compare-elim.c (conforming_compare): Accept UNSPECs.
+	(find_comparison_dom_walker::before_dom_children): Deal with
+	instructions both using and killing the flags register.
+	(equivalent_reg_at_start): New function extracted from...
+	(try_eliminate_compare): ...here.  Use it and add support for
+	registers and UNSPECs as second operand of the compare.
+	* config/visium/visium-modes.def (CCV): New.
+	* config/visium/predicates.md (visium_v_comparison_operator): New.
+	(visium_branch_operator): Deal with CCV mode.
+	* config/visium/visium.c (visium_select_cc_mode): Likewise.
+	(output_cbranch): Likewise.
+	* config/visium/visium.md (UNSPEC_{ADD,SUB,NEG}V): New constants.
+	(uaddv<mode>4): New expander.
+	(addv<mode>4): Likewise.
+	(add<mode>3_insn_set_carry): New instruction.
+	(add<mode>3_insn_set_overflow): Likewise.
+	(addsi3_insn_set_overflow): Likewise.
+	(usubv<mode>4): New expander.
+	(subv<mode>4): Likewise.
+	(sub<mode>3_insn_set_carry): New instruction.
+	(sub<mode>3_insn_set_overflow): Likewise.
+	(subsi3_insn_set_overflow): Likewise.
+	(unegv<mode>3): New expander.
+	(negv<mode>3): Likewise.
+	(neg<mode>2_insn_set_overflow): New instruction.
+	(addv_tst<mode>): Likewise.
+	(subv_tst<mode>): Likewise.
+	(negv_tst<mode>): Likewise.
+	(cbranch<mode>4_addv_insn): New splitter and instruction.
+	(cbranch<mode>4_subv_insn): Likewise.
+	(cbranch<mode>4_negv_insn): Likewise.
+
+2016-10-20  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-alias.c (ptrs_compare_unequal): Remove code duplication.
+	Handle decls possibly not bound.
+	* tree-ssa-structalias.c (get_constraint_for_ssa_var): Add
+	nothing_id for decls that might not be bound if we are interested
+	for the address.
+	(get_constraint_for_component_ref): Deal with that.
+
+2016-10-20  Michael Matz  <matz@suse.de>
+
+	Loop splitting.
+	* common.opt (-fsplit-loops): New flag.
+	* passes.def (pass_loop_split): Add.
+	* opts.c (default_options_table): Add OPT_fsplit_loops entry at -O3.
+	(enable_fdo_optimizations): Add loop splitting.
+	* timevar.def (TV_LOOP_SPLIT): Add.
+	* tree-pass.h (make_pass_loop_split): Declare.
+	* tree-ssa-loop-manip.h (rewrite_into_loop_closed_ssa_1): Declare.
+	* tree-ssa-loop-unswitch.c: Include tree-ssa-loop-manip.h,
+	* tree-ssa-loop-split.c: New file.
+	* Makefile.in (OBJS): Add tree-ssa-loop-split.o.
+	* doc/invoke.texi (fsplit-loops): Document.
+	* doc/passes.texi (Loop optimization): Add paragraph about loop
+	splitting.
+
+2016-10-20  Richard Biener  <rguenther@suse.de>
+
+	* cgraphunit.c (analyze_functions): Set node->definition to
+	false to signal symbol removal to debug_hooks->late_global_decl.
+	* ipa.c (symbol_table::remove_unreachable_nodes): When not in
+	WPA signal symbol removal to the debuginfo machinery.
+	* dwarf2out.c (dwarf2out_late_global_decl): Instead of
+	using early_finised to guard the we're called for symbol
+	removal case look at the symtabs definition flag.
+	(gen_variable_die): Remove redundant check.
+
+2016-10-20  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* config/s390/s390.md ("prefetch"): Add fallthrough comment.
+
+2016-10-20  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR tree-optimization/53979
+	* match.pd ((a ^ b) | a -> a | b): New pattern.
+
+2016-10-19  John David Anglin  <danglin@gcc.gnu.org>
+
+	* config/pa/pa64-hpux.h (PA_INIT_FRAME_DUMMY_ASM_OP): Move to
+	config/pa/pa64-hpux-lib.h.
+	(PA_CRTBEGIN_HACK): Likewise.
+	(DTOR_LIST_BEGIN): Likewise.
+
+2016-10-19  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result
+	register only if "in" and "out" are different registers.
+
+2016-10-19  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* omp-low.c (pass_oacc_device_lower::gate): New method.
+	(execute): Always call execute_oacc_device_lower.
+
+2016-10-19  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	PR tree-optimization/77916
+	PR tree-optimization/77937
+	* gimple-ssa-strength-reduction.c (analyze_increments): Remove
+	stopgap fix.
+	(insert_initializers): Requirement of initializer for -1 should be
+	based on pointer-typedness of the candidate basis.
+
+2016-10-19  Bin Cheng  <bin.cheng@arm.com>
+
+	PR tree-optimization/78005
+	* tree-vect-loop-manip.c (vect_gen_prolog_loop_niters): Compute
+	upper (included) bound for niters of prolog loop.
+	(vect_gen_scalar_loop_niters): Change parameter VF to VFM1.
+	Compute niters of scalar loop above which vectorized loop is
+	preferred, as well as the upper (included) bound for the niters.
+	(vect_do_peeling): Record niter bound for loops accordingly.
+
+2016-10-19  Thomas Schwinge  <thomas@codesourcery.com>
+
+	PR lto/77458
+	* tree-core.h (enum tree_index): Put the complex types after their
+	component types.
+	* tree-streamer.c (verify_common_node_recorded): New function.
+	(preload_common_nodes) <TREE_CODE (node) == COMPLEX_TYPE>: Use it.
+
+2016-10-19  Martin Liska  <mliska@suse.cz>
+
+	* cgraph.h (cgraph_edge::binds_to_current_def_p):
+	Replace NULL with false as a return value.
+
+2016-10-19  Thomas Schwinge  <thomas@codesourcery.com>
+
+	PR tree-optimization/78024
+	* omp-low.c (oacc_loop_discovery): Call clear_bb_flags before, and
+	don't clear BB_VISITED after processing.
+
+2016-10-19  Richard Biener  <rguenther@suse.de>
+
+	* domwalk.c (dom_walker::walk): Use RPO order.
+
+2016-10-19  Richard Biener  <rguenther@suse.de>
+
+	* tree-vrp.c (evrp_dom_walker::evrp_dom_walker): Initialize
+	stmts_to_remove.
+	(evrp_dom_walker::~evrp_dom_walker): Free it.
+	(evrp_dom_walker::stmts_to_remove): Add.
+	(evrp_dom_walker::before_dom_children): Mark PHIs and stmts
+	whose output we fully propagate for removal.  Propagate
+	into BB destination PHI arguments.
+	(execute_early_vrp): Remove queued stmts.  Dump value ranges
+	before stmt removal.
+
+2016-10-18  Aldy Hernandez  <aldyh@redhat.com>
+
+	* Makefile.in (OBJS): Add gimple-ssa-warn-alloca.o.
+	* passes.def: Add two instances of pass_walloca.
+	* tree-pass.h (make_pass_walloca): New.
+	* gimple-ssa-warn-alloca.c: New file.
+	* doc/invoke.texi: Document -Walloca, -Walloca-larger-than=, and
+	-Wvla-larger-than= options.
+
+2016-10-18  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* cfg.c (clear_bb_flags): Use FOR_ALL_BB_FN.
+	* config/nvptx/nvptx.c (nvptx_find_sese): Likewise.
+
+2016-10-18  Kelvin Nilsen  <kelvin@gcc.gnu.org>
+
+	* config/rs6000/altivec.h (vec_xl_len): New macro.
+	(vec_xst_len): New macro.
+	(vec_cmpnez): New macro.
+	(vec_cntlz_lsbb): New macro.
+	(vec_cnttz_lsbb): New macro.
+	(vec_xlx): New macro.
+	(vec_xrx): New macro.
+	(vec_all_nez): New C++ predicate template.
+	(vec_any_eqz): New C++ predicate template.
+	(vec_all_ne): Revised C++ predicate template under _ARCH_PWR9
+	conditional compilation.
+	(vec_any_eq): Revised C++ predicate template under _ARCH_PWR9
+	conditional compilation.
+	(vec_all_nez): New macro.
+	(vec_any_eqz): New macro.
+	(vec_all_ne): Revised macro under _ARCH_PWR9 conditional
+	compilation.
+	(vec_any_eq): Revised macro under _ARCH_PWR9 conditional
+	compilation.
+	* config/rs6000/vector.md (VI): Moved this mode iterator
+	definition from altivec.md to vector.md.
+	(UNSPEC_NEZ_P): New value.
+	(vector_ne_<mode>_p): New expansion for implementation of
+	vec_all_ne and vec_any_eq built-in functions.
+	(vector_nez_<mode>_p): New expansion for implementation of
+	vec_all_nez and vec_any_eqz built-in functions.
+	(vector_ne_v2di_p): New expansion for implementation of vec_all_ne
+	and vec_any_eq built-in function.
+	(cr6_test_for_zero): New commentary to explain this expansion.
+	(cr6_test_for_zero_reverse): New commentary to explain this expansion.
+	(cr6_test_for_lt): New commentary to explain this expansion.
+	(cr6_test_for_lt_reverse): New commentary to explain this
+	expansion.
+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+	overloaded function prototypes for vec_all_ne, vec_all_nez,
+	vec_any_eq, vec_any_eqz, vec_cmpnez, vec_cntlz_lsbb,
+	vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx, and vec_xrx
+	built-in functions.
+	(altivec_resolve_overloaded_builtin): Modify the handling of
+	ALTIVEC_BUILTIN_VEC_CMPNE to use the Power9 instructions when
+	the compiler is configured to support TARGET_P9_VECTOR.
+	* config/rs6000/rs6000-builtin.def (BU_ALTIVEC_P): Add commentary
+	to explain the special processing that is given to predicate
+	built-ins introduced using this macro.
+	(BU_ALTIVEC_OVERLOAD_P): Add commentary to alert maintainers to
+	the special processing given to predicate built-ins introduced
+	using this macro.
+	(BU_VSX_P): Likewise.
+	(BU_P8V_AV_P): Likewise.
+	(BU_P9V_AV_P): Likewise.
+	(BU_P9V_AV_X): New macro.
+	(BU_P9V_64BIT_AV_X): New macro.
+	(BU_P9V_VSX_3): New macro.
+	(BU_P9V_OVERLOAD_P): New macro.
+	(LXVL): New BU_P9V_64BIT_VSX_2.
+	(VEXTUBLX): New BU_P9V_AV_2.
+	(VEXTUBRX): Likewise.
+	(VEXTUHLX): Likewise.
+	(VEXTUHRX): Likewise.
+	(VEXTUWLX): Likewise.
+	(VEXTUWRX): Likewise.
+	(STXVL): New BU_P9V_64BIT_AV_X.
+	(VCLZLSBB): New BU_P9V_AV_1.
+	(VCTZLSBB): Likewise.
+	(CMPNEB): New BU_P9V_AV_2.
+	(CMPNEH): Likewise.
+	(CMPNEW): Likewise.
+	(CMPNEF): Likewise.
+	(CMPNED): Likewise.
+	(VCMPNEB_P): New BU_P9V_AV_P.
+	(VCMPNEH_P): Likewise.
+	(VCMPNEW_P): Likewise.
+	(VCMPNED_P): Likewise.
+	(VCMPNEFP_P): Likewise.
+	(VCMPNEDP_P): Likewise.
+	(CMPNEZB): New BU_P9V_AV_2.
+	(CMPNEZH): Likewise.
+	(CMPNEZW): Likewise.
+	(VCMPNEZB_P): New BU_P9V_AV_P.
+	(VCMPNEZH_P): Likewise.
+	(VCMPNEZW_P): Likewise.
+	(LXVL): New BU_P9V_OVERLOAD_2.
+	(STXVL): New BU_P9V_OVERLOAD_3.
+	(VEXTULX): New BU_P9V_OVERLOAD_2.
+	(VEXTURX): Likewise.
+	(CMPNEZ): Likewise.
+	(VCMPNEZ_P): New BU_P9V_OVERLOAD_P.
+	(VCMPNE_P): Likewise.
+	(VCLZLSBB): New BU_P9V_OVERLOAD_1.
+	(VCTZLSBB): Likewise.
+	* config/rs6000/rs6000.c (altivec_expand_predicate_builtin): Add
+	comment to explain mode used for scratch register.
+	(altivec_expand_stxvl_builtin): New function.
+	(altivec_expand_builtin): Add case for new constant P9V_BUILTIN_STXVL.
+	(altivec_init_builtins): Add initialized variable
+	void_ftype_v16qi_pvoid_long and use this type to define the
+	built-in function __builtin_altivec_stxvl.
+	* config/rs6000/vsx.md (UNSPEC_LXVL): New value.
+	(UNSPEC_STXVL): New value.
+	(UNSPEC_VCLZLSBB): New value.
+	(UNSPEC_VCTZLSBB): New value.
+	(UNSPEC_VEXTUBLX): New value.
+	(UNSPEC_VEXTUHLX): New value.
+	(UNSPEC_VEXTUWLX): New value.
+	(UNSPEC_VEXTUBRX): New value.
+	(UNSPEC_VEXTUHRX): New value.
+	(UNSPEC_VEXTUWRX): New value.
+	(UNSPEC_VCMPNEB): New value.
+	(UNSPEC_VCMPNEZB): New value.
+	(UNSPEC_VCMPNEH): New value.
+	(UNSPEC_VCMPNEZH): New value.
+	(UNSPEC_VCMPNEW): New value.
+	(UNSPEC_VCMPNEZW): New value.
+	(*vsx_ne_<mode>_p): New insn for vector test all not equal with
+	vector of integer modes.
+	(*vsx_ne_<mode>_p): New insn for vector test all not equal with
+	vector of float or double modes.
+	(*vector_nez_<mode>_p): New insn for vector test all not equal or
+	zero.
+	(lxvl): New expand for load VSX vector with length.
+	(*lxvl): New insn for load VSX vector with length.
+	(stxvl): New expand for store VSX vector with length.
+	(*stxvl): New insn for store VSX vector with length.
+	(vcmpneb): New insn for vector of byte compare not equal.
+	(vcmpnezb): New insn for vector of byte compare not equal or zero.
+	(vcmpneh): New insn for vector of half word compare not equal.
+	(vcmpnezh): New insn for vector of half word compare not equal or
+	zero.
+	(vcmpnew): New insn for vector of word compare not equal.
+	(vcmpne<VSs>): New insn for vector of float or double compare not
+	equal.
+	(vcmpnezw): New insn for vector of word compare not equal or zero.
+	(vclzlsbb): New insn for vector count leading zero
+	least-significant bits byte.
+	(vctzlsbb): New insn for vector count trailing zero least
+	signficant bits byte.
+	(vextublx): New insn for vector extract unsigned byte left
+	indexed.
+	(vextubrx): New insn for vector extract unsigned byte right
+	indexed.
+	(vextuhlx): New insn for vector extract unsigned half word left
+	indexed.
+	(vextuhrx): New insn for vector extract unsigned half word right
+	indexed.
+	(vextuwlx): New insn for vector extract unsigned word left
+	indexed.
+	(vextuwrx): New insn for vector extract unsigned word right
+	indexed.
+	* config/rs6000/rs6000.h (RS6000_BTC_CONST): Enhance comment to
+	clarify intent of this constant.
+	* config/rs6000/altivec.md (VI): Move this mode iterator to vsx.md.
+	* doc/extend.texi (PowerPC Altivec Built-in Functions): Add
+	documentation for vec_all_nez, vec_any_eqz, vec_cmpnez,
+	vec_cntlz_lsbb, vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx,
+	and vec_xrx functions.
+
+2016-10-18  Andrew Pinski  <apinski@cavium.com>
+
+	PR tree-opt/65950
+	* predict.c (is_exit_with_zero_arg): New function.
+	(tree_bb_level_predictions): Don't consider paths leading to exit(0)
+	as nottaken.
+
+2016-10-18  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/77991
+	* config/i386/i386.c (legitimize_tls_address)
+	<case TLS_MODEL_INITIAL_EXEC>: For TARGET_64BIT || TARGET_ANY_GNU_TLS
+	convert dest to Pmode if different than Pmode.
+
+2016-10-18  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	PR tree-optimization/77916
+	* gimple-ssa-strength-reduction.c (analyze_increments): Reinstate
+	stopgap fix, as pointers with -1 increment are still broken.
+
+2016-10-18  David Edelsohn  <dje.gcc@gmail.com>
+
+	* config/rs6000/rs6000.c (rs6000_output_symbol_ref): Move storage
+	mapping class decoration from here...
+	(rs6000_xcoff_encode_section): ...to here.
+
+	(rs6000_savres_strategy) [AIX,ELFv2]: Inline FPR save and restore
+	if shrink-wrapping and optimizing for speed.
+
+2016-10-18  Richard Biener  <rguenther@suse.de>
+
+	* tree-vrp.c (evrp_dom_walker::before_dom_children): Handle
+	not visited but non-executable predecessors.  Return taken edge.
+	Simplify conditions and refactor propagation vs. folding step.
+
+2016-10-18  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/rs6000.c (rs6000_savres_strategy): Do not select
+	{SAVE,REST}_MULTIPLE if shrink-wrapping separate components.
+	(rs6000_get_separate_components): Assert we do not have those
+	strategies selected.
+
+2016-10-18  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-propagate.h (substitute_and_fold): Adjust prototype.
+	* tree-ssa-propagate.c (ssa_prop_fini): Remove final BB_VISITED
+	clearing.
+	(substitute_and_fold_dom_walker): Adjust constructor.
+	(substitute_and_fold_dom_walker::before_dom_children): Remove
+	do_dce flag and handling (always true).
+	(substitute_and_fold): Likewise.
+	* tree-vrp.c (vrp_finalize): Adjust.
+	(execute_early_vrp): Remove final BB_VISITED clearing.
+	* tree-ssa-ccp.c (ccp_finalize): Adjust.
+	* tree-ssa-copy.c (fini_copy_prop): Likewise.
+	* ira.c (ira): Call clear_bb_flags.
+
+2016-10-18  Richard Biener  <rguenther@suse.de>
+
+	* genmatch.c (dt_operand::gen_gimple_expr): Use get_name to
+	get at the operand to look at with TREE_OPERAND for generic
+	sub-nodes.
+
+2016-10-18  David Malcolm  <dmalcolm@redhat.com>
+
+	* genattrtab.c (attr_string): Use rtx_reader_ptr for call to
+	copy_md_ptr_loc.
+	(gen_attr): Use rtx_reader_ptr for lookup_enum_type call.
+	(write_test_expr): Use rtx_reader_ptr for calls to
+	fprint_c_condition.
+	(write_attr_value): Likewise.
+	* genconditions.c (write_one_condition): Use rtx_reader_ptr for
+	call to print_md_ptr_loc.
+	(write_one_condition): Likewise for calls to print_c_condition.
+	* genconstants.c: Include "statistics.h" and "vec.h".
+	(main): Update for conversion to member functions.
+	* genemit.c (emit_c_code): Use rtx_reader_ptr for
+	call to print_md_ptr_loc.
+	* genenums.c: Include "statistics.h" and "vec.h".
+	(main): Update for conversion of traverse_enum_types to a method.
+	* genmddeps.c: Include "statistics.h" and "vec.h".
+	* genoutput.c (process_template): Use rtx_reader_ptr for call to
+	print_md_ptr_loc.
+	* genpreds.c (write_predicate_subfunction): Likewise.
+	(write_predicate_expr): Likewise for calls to print_c_condition.
+	* genrecog.c (print_test): Likewise.
+	* gensupport.c (process_rtx): Likewise for calls to
+	copy_md_ptr_loc and join_c_conditions.
+	(alter_test_for_insn): Likewise for call to join_c_conditions.
+	(process_substs_on_one_elem): Likewise.
+	(gen_mnemonic_setattr): Update for move of string_obstack to a
+	field of rtx_reader.
+	(mnemonic_htab_callback): Likewise.  Fix formatting.
+	(gen_mnemonic_attr): Likewise.
+	* gentarget-def.c (def_target_insn): Use rtx_reader_ptr for calls
+	to print_c_condition.
+	* read-md.c: Include "statistics.h" and "vec.h".
+	(string_obstack): Convert this global to field "m_string_obstack"
+	of class rtx_reader.
+	(ptr_locs): Likewise, as "m_ptr_locs".
+	(ptr_loc_obstack): Likewise, as "m_ptr_loc_obstack".
+	(joined_conditions): Likewise, as "m_joined_conditions".
+	(joined_conditions_obstack): Likewise, as "m_joined_conditions_obstack".
+	(md_constants): Likewise, as "m_md_constants".
+	(enum_types): Likewise, as "m_enum_types".
+	(set_md_ptr_loc): Convert to...
+	(rtx_reader::set_md_ptr_loc): ...member function.
+	(get_md_ptr_loc): Convert to...
+	(rtx_reader::get_md_ptr_loc): ...member function.
+	(copy_md_ptr_loc): Convert to...
+	(rtx_reader::copy_md_ptr_loc): ...member function.
+	(fprint_md_ptr_loc): Convert to...
+	(rtx_reader::fprint_md_ptr_loc): ...member function.
+	(print_md_ptr_loc): Convert to...
+	(rtx_reader::print_md_ptr_loc): ...member function.
+	(join_c_conditions): Convert to...
+	(rtx_reader::join_c_conditions): ...member function.
+	(fprint_c_condition): Convert to...
+	(rtx_reader::fprint_c_condition): ...member function.
+	(print_c_condition): Convert to...
+	(rtx_reader::print_c_condition): ...member function.
+	(read_name): Convert to...
+	(rtx_reader::read_name): ...member function.
+	(read_escape): Convert to...
+	(rtx_reader::read_escape): ...member function.
+	(read_quoted_string): Convert to...
+	(rtx_reader::read_quoted_string): ...member function.
+	(read_braced_string): Convert to...
+	(rtx_reader::read_braced_string): ...member function.
+	(read_string): Convert to...
+	(rtx_reader::read_string): ...member function.
+	(read_skip_construct): Convert to...
+	(rtx_reader::read_skip_construct): ...member function.
+	(handle_constants): Convert to...
+	(rtx_reader::handle_constants): ...member function.
+	(traverse_md_constants): Convert to...
+	(rtx_reader::traverse_md_constants): ...member function.
+	(handle_enum): Convert to...
+	(rtx_reader::handle_enum): ...member function.
+	(lookup_enum_type): Convert to...
+	(rtx_reader::lookup_enum_type): ...member function.
+	(traverse_enum_types): Convert to...
+	(rtx_reader::traverse_enum_types): ...member function.
+	(rtx_reader::rtx_reader): Move initializations
+	of various former global data from rtx_reader::read_md_files to
+	here, as fields, along with the call to unlock_std_streams.
+	(rtx_reader::~rtx_reader): Clean up m_base_dir, and clean up
+	the new fields.
+	(rtx_reader::read_md_files): Move initializations of various
+	global data from here to the ctor.
+	* read-md.h (read_name): Convert to...
+	(rtx_reader::read_name): ...member function.
+	(rtx_reader::read_escape): New method decl.
+	(read_quoted_string): Convert to...
+	(rtx_reader::read_quoted_string): ...member function.
+	(rtx_reader::read_braced_string): New method decl.
+	(read_string): Convert to...
+	(rtx_reader::read_string): ...member function.
+	(rtx_reader::read_skip_construct): New method decl.
+	(rtx_reader::set_md_ptr_loc): New method decl.
+	(rtx_reader::get_md_ptr_loc): New method decl.
+	(copy_md_ptr_loc): Convert to...
+	(rtx_reader::copy_md_ptr_loc): ...member function.
+	(fprint_md_ptr_loc): Convert to...
+	(rtx_reader::fprint_md_ptr_loc): ...member function.
+	(print_md_ptr_loc): Convert to...
+	(rtx_reader::print_md_ptr_loc): ...member function.
+	(rtx_reader::lookup_enum_type): New method decl.
+	(rtx_reader::traverse_enum_types): New method decl.
+	(rtx_reader::handle_constants): New method decl.
+	(traverse_md_constants): Convert to...
+	(rtx_reader::traverse_md_constants): ...member function.
+	(rtx_reader::handle_enum): New method decl.
+	(rtx_reader::join_c_conditions): New method decl.
+	(fprint_c_condition): Convert to...
+	(rtx_reader::fprint_c_condition): ...member function.
+	(print_c_condition): Convert to...
+	(rtx_reader::print_c_condition): ...member function.
+	(rtx_reader::apply_iterator_to_string): New method decl.
+	(rtx_reader::copy_rtx_for_iterators): New method decl.
+	(rtx_reader::read_conditions): New method decl.
+	(rtx_reader::record_potential_iterator_use): New method decl.
+	(rtx_reader::read_mapping): New method decl.
+	(rtx_reader::read_rtx): New method decl.
+	(rtx_reader::read_rtx_code): New method decl.
+	(rtx_reader::read_rtx_operand): New method decl.
+	(rtx_reader::read_nested_rtx): New method decl.
+	(rtx_reader::read_rtx_variadic): New method decl.
+	(rtx_reader::get_string_obstack): New method.
+	(rtx_reader::get_md_constants): New method.
+	(string_obstack): Convert global variable decl to...
+	(rtx_reader::m_string_obstack): ...this new field.
+	(rtx_reader::m_ptr_locs): New field.
+	(rtx_reader::m_ptr_loc_obstack): New field.
+	(rtx_reader::m_joined_conditions): New field.
+	(rtx_reader::m_joined_conditions_obstack): New field.
+	(rtx_reader::m_md_constants): New field.
+	(rtx_reader::m_enum_types): New field.
+	* read-rtl.c (apply_iterator_to_string): Convert to...
+	(rtx_reader::apply_iterator_to_string): ...member function.
+	(copy_rtx_for_iterators): Convert to...
+	(rtx_reader::copy_rtx_for_iterators): ...member function.
+	(add_condition_to_string): Use rtx_reader_ptr for
+	calls join_c_conditions.
+	(apply_iterators): Use rtx_reader_ptr for calls to
+	join_c_conditions and copy_rtx_for_iterators.
+	(read_conditions): Convert to...
+	(rtx_reader::read_conditions): ...member function.
+	(record_potential_iterator_use): Convert to...
+	(rtx_reader::record_potential_iterator_use): ...member function.
+	(read_mapping): Convert to...
+	(rtx_reader::read_mapping): ...member function.
+	(read_subst_mapping): Use rtx_reader_ptr for read_string call.
+	(read_rtx): Convert to...
+	(rtx_reader::read_rtx): ...member function.
+	(read_rtx_code): Convert to...
+	(rtx_reader::read_rtx_code): ...member function.
+	(read_rtx_operand): Convert to...
+	(rtx_reader::read_rtx_operand): ...member function.  Update for move
+	of string_obstack to a field.
+	(read_nested_rtx): Convert to..
+	(rtx_reader::read_nested_rtx): ...member function.
+	(read_rtx_variadic): Convert to..
+	(rtx_reader::read_rtx_variadic): ...member function.
+
+2016-10-18  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* tree-vrp.c (get_value_range): Check get_ptr_nonnull.
+
+2016-10-18  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* ipa-prop.c (ipa_compute_jump_functions_for_edge): Set value range
+	for pointer type too.
+	(ipcp_update_vr): set_ptr_nonnull for pointer.
+
+2016-10-18  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* tree-ssa-alias.h (pt_solution_singleton_or_null_p): Renamed from
+	pt_solution_singleton_p.
+	* tree-ssa-ccp.c (fold_builtin_alloca_with_align): Use renamed
+	pt_solution_singleton_or_null_p from pt_solution_singleton_p.
+	* tree-ssa-structalias.c (find_what_p_points_to): Preserve
+	pointer nonnull computed by VRP.
+	Also Conservatively set pt.null to 1.
+	(pt_solution_reset): Conservatively set pt.null to 1.
+	(pt_solution_singleton_or_null_p): Renamed from
+	pt_solution_singleton_p.
+	* tree-ssanames.h (set_ptr_nonnull): Declare.
+	(get_ptr_nonnull): Likewise.
+	* tree-ssanames.c (set_ptr_nonnull): New.
+	(get_ptr_nonnull): Likewise.
+	* tree-vrp.c (vrp_finalize): Set ptr that are nonnull.
+	(evrp_dom_walker::before_dom_children): Likewise.
+
+2016-10-17  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/i386/i386.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Move to...
+	* config/i386/i386.c (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): ...here.
+	* config/ia64/ia64.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Move to...
+	* config/ia64/ia64.c (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): ...here.
+	* config/rs6000/rs6000.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Move to.
+	* config/rs6000/rs6000.c (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): ...here.
+	(rs6000_option_override_internal): Clear it if ABI_AIX.
+	* config/sparc/sparc.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Move to...
+	* config/sparc/sparc.c (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): ... here.
+
+2016-10-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* gimple-ssa-strength-reduction.c (record_increment): Remove
+	garbage comment.
+
+2016-10-17  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* expmed.c (expand_shift_1): Add MAY_FAIL parameter and do not assert
+	that the result is non-zero if it is true.
+	(maybe_expand_shift): New wrapper around expand_shift_1.
+	(emit_store_flag): Call maybe_expand_shift in lieu of expand_shift.
+
+2016-10-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	PR tree-optimization/77916
+	* gimple-ssa-strength-reduction.c (create_add_on_incoming_edge):
+	Don't allow a MINUS_EXPR for pointer arithmetic for either known
+	or unknown strides.
+	(record_increment): Increments of -1 for unknown strides just use
+	a multiply initializer like other negative values.
+	(analyze_increments): Remove stopgap solution for -1 increment
+	applied to pointer arithmetic.
+
+2016-10-17  Yuri Rumyantsev  <ysrumyan@gmail.com>
+
+	* dominance.c (dom_info::dom_info): Add new constructor for region
+	which is vector of basic blocks.
+	(dom_init): New method to initialize members common for both
+	constructors.
+	(dom_info::dom_info): Invoke dom_init for partial initialization.
+	(dom_info::get_idom): Add check to corner cases on basic blocks which
+	are not in region.
+	(dom_info::calc_dfs_tree): Check M_FAKE_EXIT_EDGE instead of M_REVERSE
+	to detect unreachable bbs.
+	(dom_info::calc_idoms): Likewise.
+	(compute_dom_fast_query_in_region): New function.
+	(calculate_dominance_info_for_region): Likewise.
+	(free_dominance_info_for_region): Likewise.
+	* dominance.h: Add prototypes for introduced region-based functions
+	* tree-if-conv.c (build_region): New function.
+	(if_convertible_loop_p_1): Invoke local version of post-dominators
+	calculation before basic block predication with subsequent freeing
+	post-dominator info.
+	(tree_if_conversion): Remove free of post-dominator info
+	(pass_if_conversion::execute): Delete detection of infinite loops
+	and fake edges to exit block since post-dominator calculation is
+	performed per if-converted loop only.
+
+2016-10-17  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	PR target/77308
+	* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result
+	register explicitly.
+	* config/arm/arm.md (ashldi3, ashrdi3, lshrdi3): Don't FAIL if
+	optimizing for size.
+
+2016-10-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.c: Delete inclusion of
+	cortex-a57-fma-steering.h.
+	(aarch64_override_options): Delete call
+	to aarch64_register_fma_steering.
+	* config/aarch64/aarch64-protos.h (make_pass_fma_steering): Declare.
+	* config/aarch64/cortex-a57-fma-steering.h: Delete.
+	* config/aarch64/aarch64-passes.def: New file.
+	* config/aarch64/cortex-a57-fma-steering.c
+	(aarch64_register_fma_steering): Delete definition.
+	(make_pass_fma_steering): Remove static qualifier.
+	* config/aarch64/t-aarch64 (PASSES_EXTRA): New directive.
+	(cortex-a57-fma-steering.o): Remove dependency on
+	cortex-a57-fma-steering.h.
+
+2016-10-17  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* explow.c (validize_mem): Do not modify the argument in-place.
+
+2016-10-17  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* tree-streamer.c (record_common_node): Explicitly list expected
+	tree codes.
+
+2016-10-17  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/77988
+	* tree-vrp.c (remove_range_assertions): Use replace_uses_by.
+
+2016-10-17  Marek Polacek  <polacek@redhat.com>
+
+	* Makefile.in (C_COMMON_OBJS): Add c-family/c-attribs.o.
+
+2016-10-17  Richard Biener  <rguenther@suse.de>
+
+	* bb-reorder.c (reorder_basic_blocks_simple): Clear BB_VISITED
+	before using it.
+
+2016-10-17  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR tree-optimization/71636
+	* match.pd (x & ((1 << b) - 1) -> x & ~(~0 << b)): New pattern.
+
+2016-10-17  Richard Biener  <rguenther@suse.de>
+
+	* gimplify.c (gimplify_function_tree): Do not move the outer
+	binds block.
+
+2016-10-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* langhooks.h (struct lang_hooks_for_decls): Remove
+	function_decl_explicit_p, function_decl_deleted_p and
+	function_decl_defaulted hooks.  Add decl_dwarf_attribute hook.
+	* langhooks-def.h (lhd_decl_dwarf_attribute): Declare.
+	(LANG_HOOKS_FUNCTION_DECL_EXPLICIT_P,
+	LANG_HOOKS_FUNCTION_DECL_DELETED_P,
+	LANG_HOOKS_FUNCTION_DECL_DEFAULTED): Remove.
+	(LANG_HOOKS_DECL_DWARF_ATTRIBUTE): Define.
+	(LANG_HOOKS_DECLS): Remove LANG_HOOKS_FUNCTION_DECL_EXPLICIT_P,
+	LANG_HOOKS_FUNCTION_DECL_DELETED_P and
+	LANG_HOOKS_FUNCTION_DECL_DEFAULTED.  Add
+	LANG_HOOKS_DECL_DWARF_ATTRIBUTE.
+	* langhooks.c (lhd_decl_dwarf_attribute): New function.
+	* dwarf2out.c (gen_subprogram_die): Use
+	lang_hooks.decls.decl_dwarf_attribute instead of
+	lang_hooks.decls.function_decl_*.
+
+2016-10-16  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR ada/37139
+	PR ada/67205
+	* common.opt (-ftrampolines): New option.
+	* doc/invoke.texi (Code Gen Options): Document it.
+	* doc/tm.texi.in (Trampolines): Add TARGET_CUSTOM_FUNCTION_DESCRIPTORS.
+	* doc/tm.texi: Regenerate.
+	* builtins.def: Add init_descriptor and adjust_descriptor.
+	* builtins.c (expand_builtin_init_trampoline): Do not issue a warning
+	on platforms with descriptors.
+	(expand_builtin_init_descriptor): New function.
+	(expand_builtin_adjust_descriptor): Likewise.
+	(expand_builtin) <BUILT_IN_INIT_DESCRIPTOR>: New case.
+	<BUILT_IN_ADJUST_DESCRIPTOR>: Likewise.
+	* calls.c (prepare_call_address): Remove SIBCALLP parameter and add
+	FLAGS parameter.  Deal with indirect calls by descriptor and adjust.
+	Set STATIC_CHAIN_REG_P on the static chain register, if any.
+	(call_expr_flags): Set ECF_BY_DESCRIPTOR for calls by descriptor.
+	(expand_call): Likewise.  Move around call to prepare_call_address
+	and pass all flags to it.
+	* cfgexpand.c (expand_call_stmt): Reinstate CALL_EXPR_BY_DESCRIPTOR.
+	* gimple.h (enum gf_mask): New GF_CALL_BY_DESCRIPTOR value.
+	(gimple_call_set_by_descriptor): New setter.
+	(gimple_call_by_descriptor_p): New getter.
+	* gimple.c (gimple_build_call_from_tree): SetCALL_EXPR_BY_DESCRIPTOR.
+	(gimple_call_flags): Deal with GF_CALL_BY_DESCRIPTOR.
+	* langhooks.h (struct lang_hooks): Add custom_function_descriptors.
+	* langhooks-def.h (LANG_HOOKS_CUSTOM_FUNCTION_DESCRIPTORS): Define.
+	(LANG_HOOKS_INITIALIZER): Add LANG_HOOKS_CUSTOM_FUNCTION_DESCRIPTORS.
+	* rtl.h (STATIC_CHAIN_REG_P): New macro.
+	* rtlanal.c (find_first_parameter_load): Skip static chain registers.
+	* target.def (custom_function_descriptors): New POD hook.
+	* tree.h (FUNC_ADDR_BY_DESCRIPTOR): New flag on ADDR_EXPR.
+	(CALL_EXPR_BY_DESCRIPTOR): New flag on CALL_EXPR.
+	* tree-core.h (ECF_BY_DESCRIPTOR): New mask.
+	Document FUNC_ADDR_BY_DESCRIPTOR and CALL_EXPR_BY_DESCRIPTOR.
+	* tree.c (make_node_stat) <tcc_declaration>: Use FUNCTION_ALIGNMENT.
+	(build_common_builtin_nodes): Initialize init_descriptor and
+	adjust_descriptor.
+	* tree-nested.c: Include target.h.
+	(struct nesting_info): Add 'any_descr_created' field.
+	(get_descriptor_type): New function.
+	(lookup_element_for_decl): New function extracted from...
+	(create_field_for_decl): Likewise.
+	(lookup_tramp_for_decl): ...here.  Adjust.
+	(lookup_descr_for_decl): New function.
+	(convert_tramp_reference_op): Deal with descriptors.
+	(build_init_call_stmt): New function extracted from...
+	(finalize_nesting_tree_1): ...here.  Adjust and deal with descriptors.
+	* defaults.h (FUNCTION_ALIGNMENT): Define.
+	(TRAMPOLINE_ALIGNMENT): Set to above instead of FUNCTION_BOUNDARY.
+	* config/i386/i386.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Define.
+	* config/ia64/ia64.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Likewise.
+	* config/rs6000/rs6000.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS):Likewise.
+	* config/sparc/sparc.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Likewise.
+
+2016-10-16  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc.c (sparc_expand_vector_init): Only accept literal
+	constants in CONST_VECTORs.
+
+2016-10-15  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use a scratch
+	register as destination of bmask.
+	(vector_init_bshuffle): Likewise.
+	* config/sparc/sparc.md (vec_perm_constv8qi): Likewise.
+	(bmaskdi_vis): Enable only in 64-bit mode.
+
+2016-10-15  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/rs6000.c (rs6000_get_separate_components): Do not
+	make LR a separately shrink-wrapped component unless savres_strategy
+	contains all of {SAVE,REST}_INLINE_{GPRS,FPRS,VRS}.  Do not wrap
+	GPRs unless both {SAVE,REST}_INLINE_GPRS.  Do not disallow all
+	wrapping when not both {SAVE,REST}_INLINE_GPRS.
+
+2016-10-15  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* optabs.c (expand_parity): Fix mode mismatch, add final conversion
+	and keep looping on failure.
+
+2016-10-14  David Malcolm  <dmalcolm@redhat.com>
+
+	* print-rtl-function.c (print_edge): Omit "(flags)" when none are
+	set.
+	(print_rtx_function): Update example in comment for...
+	* print-rtl.c (print_rtx_operand_code_r): In compact mode, print
+	non-virtual pseudos with a '%' sigil followed by the regno, offset
+	by (LAST_VIRTUAL_REGISTER + 1), so that the first non-virtual
+	pseudo is dumped as "%0".
+
+2016-10-14  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/77959
+	* expr.c (expand_expr_real_1) <case CONST_DECL>: For EXPAND_WRITE
+	return a MEM.
+
+2016-10-14  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc-passes.def: New file.
+	* config/sparc/t-sparc (PASSES_EXTRA): Add sparc-passes.def.
+	* config/sparc/sparc-protos.h (make_pass_work_around_errata): New.
+	* config/sparc/sparc.c (sparc_option_override): Don't register passes.
+
+2016-10-14  Pat Haugen  <pthaugen@us.ibm.com>
+
+	* loop-unroll.c (unroll_loop_runtime_iterations): Condition initial
+	loop peel to loops with exit test at the beginning.
+
+2016-10-14  Pat Haugen  <pthaugen@us.ibm.com>
+
+	PR rtl-optimization/68212
+	* cfgloopmanip.c (duplicate_loop_to_header_edge): Use preheader edge
+	frequency when computing scale factor for peeled copies.
+	* loop-unroll.c (unroll_loop_runtime_iterations): Fix freq/count
+	values for switch/peel blocks/edges.
+
+2016-10-14  Pedro Alves  <palves@redhat.com>
+
+	* coretypes.h (OVERRIDE, FINAL): Delete, moved to include/ansidecl.h.
+
+2016-10-14  Catherine Moore  <clm@codesourcery.com>
+
+	* config/mips/mips.c (mips_prepare_pch_save): Initialize
+	micromips_globals to zero.
+
+2016-10-14  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/77979
+	* tree-vrp.c (compare_name_with_value): Handle released SSA names
+	in the equivalency sets.
+	(compare_names): Likewise.
+
+2016-10-14  Martin Liska  <mliska@suse.cz>
+
+	* builtins.h(target_char_cst_p): Declare the function.
+	* builtins.c (fold_builtin_memchr): Remove.
+	(target_char_cst_p): Move the function from gimple-fold.c.
+	(fold_builtin_3): Do not call the function.
+	* gimple-fold.c (gimple_fold_builtin_memchr): New function.
+	(gimple_fold_builtin): Call the function.
+	* fold-const-call.c (fold_const_call_1): Handle CFN_BUILT_IN_MEMCHR.
+