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1 // Mutual exclusion spin locks.
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2
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3 #include "types.h"
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4 #include "defs.h"
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5 #include "param.h"
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6 #include "arm.h"
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7 #include "memlayout.h"
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8 #include "mmu.h"
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9 #include "proc.h"
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10 #include "spinlock.h"
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11
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12 void initlock(struct spinlock *lk, char *name)
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13 {
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14 lk->name = name;
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15 lk->locked = 0;
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16 lk->cpu = 0;
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17 }
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18
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19 // For single CPU systems, there is no need for spinlock.
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20 // Add the support when multi-processor is supported.
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21
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22
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23 // Acquire the lock.
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24 // Loops (spins) until the lock is acquired.
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25 // Holding a lock for a long time may cause
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26 // other CPUs to waste time spinning to acquire it.
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27 void acquire(struct spinlock *lk)
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28 {
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29 pushcli(); // disable interrupts to avoid deadlock.
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30 lk->locked = 1; // set the lock status to make the kernel happy
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31
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32 #if 0
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33 if(holding(lk))
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34 panic("acquire");
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35
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36 // The xchg is atomic.
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37 // It also serializes, so that reads after acquire are not
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38 // reordered before it.
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39 while(xchg(&lk->locked, 1) != 0)
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40 ;
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41
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42 // Record info about lock acquisition for debugging.
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43 lk->cpu = cpu;
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44 getcallerpcs(get_fp(), lk->pcs);
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45
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46 #endif
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47 }
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48
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49 void cbc_acquire(struct spinlock *lk, __code (*next)(int ret))
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50 {
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51 pushcli(); // disable interrupts to avoid deadlock.
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52 lk->locked = 1; // set the lock status to make the kernel happy
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53
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54 #if 0
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55 if(holding(lk))
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56 panic("acquire");
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57
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58 // The xchg is atomic.
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59 // It also serializes, so that reads after acquire are not
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60 // reordered before it.
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61 while(xchg(&lk->locked, 1) != 0)
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62 ;
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63
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64 // Record info about lock acquisition for debugging.
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65 lk->cpu = cpu;
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66 getcallerpcs(get_fp(), lk->pcs);
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67
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68 #endif
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69 goto next();
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70 }
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71
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72 // Release the lock.
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73 void cbc_release(struct spinlock *lk, __code (*next)(int ret))
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74 {
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75 #if 0
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76 if(!holding(lk))
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77 panic("release");
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78
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79 lk->pcs[0] = 0;
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80 lk->cpu = 0;
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81
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82 // The xchg serializes, so that reads before release are
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83 // not reordered after it. The 1996 PentiumPro manual (Volume 3,
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84 // 7.2) says reads can be carried out speculatively and in
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85 // any order, which implies we need to serialize here.
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86 // But the 2007 Intel 64 Architecture Memory Ordering White
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87 // Paper says that Intel 64 and IA-32 will not move a load
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88 // after a store. So lock->locked = 0 would work here.
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89 // The xchg being asm volatile ensures gcc emits it after
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90 // the above assignments (and after the critical section).
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91 xchg(&lk->locked, 0);
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92 #endif
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93
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94 lk->locked = 0; // set the lock state to keep the kernel happy
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95 popcli();
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96 goto next();
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97 }
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98
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99 void release(struct spinlock *lk)
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100 {
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101 #if 0
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102 if(!holding(lk))
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103 panic("release");
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104
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105 lk->pcs[0] = 0;
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106 lk->cpu = 0;
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107
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108 // The xchg serializes, so that reads before release are
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109 // not reordered after it. The 1996 PentiumPro manual (Volume 3,
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110 // 7.2) says reads can be carried out speculatively and in
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111 // any order, which implies we need to serialize here.
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112 // But the 2007 Intel 64 Architecture Memory Ordering White
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113 // Paper says that Intel 64 and IA-32 will not move a load
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114 // after a store. So lock->locked = 0 would work here.
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115 // The xchg being asm volatile ensures gcc emits it after
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116 // the above assignments (and after the critical section).
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117 xchg(&lk->locked, 0);
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118 #endif
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119
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120 lk->locked = 0; // set the lock state to keep the kernel happy
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121 popcli();
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122 }
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123
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124
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125 // Check whether this cpu is holding the lock.
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126 int holding(struct spinlock *lock)
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127 {
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128 return lock->locked; // && lock->cpu == cpus;
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129 }
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130
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