|
0
|
1 #ifndef ARM_INCLUDE
|
|
|
2 #define ARM_INCLUDE
|
|
|
3
|
|
|
4 #include "device/versatile_pb.h"
|
|
|
5
|
|
|
6 // trap frame: in ARM, there are seven modes. Among the 16 regular registers,
|
|
|
7 // r13 (sp), r14(lr), r15(pc) are banked in all modes.
|
|
|
8 // 1. In xv6_a, all kernel level activities (e.g., Syscall and IRQ) happens
|
|
|
9 // in the SVC mode. CPU is put in different modes by different events. We
|
|
|
10 // switch them to the SVC mode, by shoving the trapframe to the kernel stack.
|
|
|
11 // 2. during the context switched, the banked user space registers should also
|
|
|
12 // be saved/restored.
|
|
|
13 //
|
|
|
14 // Here is an example:
|
|
|
15 // 1. a user app issues a syscall (via SWI), its user-space registers are
|
|
|
16 // saved on its kernel stack, syscall is being served.
|
|
|
17 // 2. an interrupt happens, it preempted the syscall. the app's kernel-space
|
|
|
18 // registers are again saved on its stack.
|
|
|
19 // 3. interrupt service ended, and execution returns to the syscall.
|
|
|
20 // 4. kernel decides to reschedule (context switch), it saves the kernel states
|
|
|
21 // and switches to a new process (including user-space banked registers)
|
|
|
22 #ifndef __ASSEMBLER__
|
|
|
23 struct trapframe {
|
|
|
24 uint sp_usr; // user mode sp
|
|
|
25 uint lr_usr; // user mode lr
|
|
|
26 uint r14_svc; // r14_svc (r14_svc == pc if SWI)
|
|
|
27 uint spsr;
|
|
|
28 uint r0;
|
|
|
29 uint r1;
|
|
|
30 uint r2;
|
|
|
31 uint r3;
|
|
|
32 uint r4;
|
|
|
33 uint r5;
|
|
|
34 uint r6;
|
|
|
35 uint r7;
|
|
|
36 uint r8;
|
|
|
37 uint r9;
|
|
|
38 uint r10;
|
|
|
39 uint r11;
|
|
|
40 uint r12;
|
|
|
41 uint pc; // (lr on entry) instruction to resume execution
|
|
|
42 };
|
|
|
43 #endif
|
|
|
44
|
|
|
45 // cpsr/spsr bits
|
|
|
46 #define NO_INT 0xc0
|
|
|
47 #define DIS_INT 0x80
|
|
|
48
|
|
|
49 // ARM has 7 modes and banked registers
|
|
|
50 #define MODE_MASK 0x1f
|
|
|
51 #define USR_MODE 0x10
|
|
|
52 #define FIQ_MODE 0x11
|
|
|
53 #define IRQ_MODE 0x12
|
|
|
54 #define SVC_MODE 0x13
|
|
|
55 #define ABT_MODE 0x17
|
|
|
56 #define UND_MODE 0x1b
|
|
|
57 #define SYS_MODE 0x1f
|
|
|
58
|
|
|
59 // vector table
|
|
|
60 #define TRAP_RESET 0
|
|
|
61 #define TRAP_UND 1
|
|
|
62 #define TRAP_SWI 2
|
|
|
63 #define TRAP_IABT 3
|
|
|
64 #define TRAP_DABT 4
|
|
|
65 #define TRAP_NA 5
|
|
|
66 #define TRAP_IRQ 6
|
|
|
67 #define TRAP_FIQ 7
|
|
|
68
|
|
|
69 #endif
|
