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1 // Support of ARM PrimeCell Vectored Interrrupt Controller (PL190)
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2 #include "types.h"
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3 #include "defs.h"
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4 #include "param.h"
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5 #include "arm.h"
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6 #include "memlayout.h"
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7 #include "mmu.h"
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8
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9 // PL190 supports the vectored interrupts and non-vectored interrupts.
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10 // In this code, we use non-vected interrupts (aka. simple interrupt).
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11 // The flow to handle simple interrupts is as the following:
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12 // 1. an interrupt (IRQ) occurs, trap.c branches to our IRQ handler
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13 // 2. read the VICIRQStatus register, for each source generating
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14 // the interrrupt:
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15 // 2.1 locate the correct ISR
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16 // 2.2 execute the ISR
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17 // 2.3 clear the interrupt
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18 // 3 return to trap.c, which will resume interrupted routines
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19 // Note: must not read VICVectorAddr
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20
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21
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22 // define the register offsets (in the unit of 4 bytes). The base address
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23 // of the VIC depends on the board
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24 static volatile uint* vic_base;
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25
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26 #define VIC_IRQSTATUS 0 // status of interrupts after masking by ENABLE and SEL
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27 #define VIC_FIQSTATUS 1 // status of interrupts after masking
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28 #define VIC_RAWINTR 2 // status of interrupts before masking
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29 #define VIC_INTSEL 3 // interrupt select (IRQ or FIQ), by default IRQ
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30 #define VIC_INTENABLE 4 // enable interrupts (1 - enabled, 0 - disabled)
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31 #define VIC_INTCLEAR 5 // clear bits in ENABLE register (1 - clear it)
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32 #define VIC_PROTECTIOIN 8 // who can access: user or privileged
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33
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34 #define NUM_INTSRC 32 // numbers of interrupt source supported
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35
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36 static ISR isrs[NUM_INTSRC];
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37
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38 static void default_isr (struct trapframe *tf, int n)
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39 {
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40 cprintf ("unhandled interrupt: %d\n", n);
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41 }
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42
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43 // initialize the PL190 VIC
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44 void pic_init (void * base)
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45 {
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46 int i;
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47
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48 // set the base for the controller and disable all interrupts
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49 vic_base = base;
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50 vic_base[VIC_INTCLEAR] = 0xFFFFFFFF;
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51
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52 for (i = 0; i < NUM_INTSRC; i++) {
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53 isrs[i] = default_isr;
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54 }
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55 }
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56
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57 // enable an interrupt (with the ISR)
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58 void pic_enable (int n, ISR isr)
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59 {
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60 if ((n<0) || (n >= NUM_INTSRC)) {
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61 panic ("invalid interrupt source");
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62 }
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63
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64 // write 1 bit enable the interrupt, 0 bit has no effect
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65 isrs[n] = isr;
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66 vic_base[VIC_INTENABLE] = (1 << n);
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67 }
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68
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69 // disable an interrupt
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70 void pic_disable (int n)
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71 {
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72 if ((n<0) || (n >= NUM_INTSRC)) {
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73 panic ("invalid interrupt source");
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74 }
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75
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76 vic_base[VIC_INTCLEAR] = (1 << n);
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77 isrs[n] = default_isr;
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78 }
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79
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80 // dispatch the interrupt
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81 void pic_dispatch (struct trapframe *tp)
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82 {
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83 uint intstatus;
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84 int i;
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85
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86 intstatus = vic_base[VIC_IRQSTATUS];
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87
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88 for (i = 0; i < NUM_INTSRC; i++) {
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89 if (intstatus & (1<<i)) {
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90 isrs[i](tp, i);
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91 }
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92 }
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93
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94 intstatus = vic_base[VIC_IRQSTATUS];
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95 }
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96
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