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1 // Definition for ARM MMU
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2 #ifndef MMU_INCLUDE
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3 #define MMU_INCLUDE
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4
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5 // align_up/down: al must be of power of 2
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6 #define align_up(sz, al) (((uint)(sz)+ (uint)(al)-1) & ~((uint)(al)-1))
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7 #define align_dn(sz, al) ((uint)(sz) & ~((uint)(al)-1))
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8 //
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9 // Since ARMv6, you may use two page tables, one for kernel pages (TTBR1),
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10 // and one for user pages (TTBR0). We use this architecture. Memory address
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11 // lower than UVIR_BITS^2 is translated by TTBR0, while higher memory is
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12 // translated by TTBR1.
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13 // Kernel pages are create statically during system initialization. It use
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14 // 1MB page mapping. User pages use 4K pages.
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15 //
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16
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17
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18 // access permission for page directory/page table entries.
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19 #define AP_NA 0x00 // no access
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20 #define AP_KO 0x01 // privilaged access, kernel: RW, user: no access
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21 #define AP_KUR 0x02 // no write access from user, read allowed
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22 #define AP_KU 0x03 // full access
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23
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24 // domain definition for page table entries
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25 #define DM_NA 0x00 // any access causing a domain fault
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26 #define DM_CLIENT 0x01 // any access checked against TLB (page table)
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27 #define DM_RESRVED 0x02 // reserved
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28 #define DM_MANAGER 0x03 // no access check
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29
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30 #define PE_CACHE (1 << 3)// cachable
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31 #define PE_BUF (1 << 2)// bufferable
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32
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33 #define PE_TYPES 0x03 // mask for page type
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34 #define KPDE_TYPE 0x02 // use "section" type for kernel page directory
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35 #define UPDE_TYPE 0x01 // use "coarse page table" for user page directory
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36 #define PTE_TYPE 0x02 // executable user page(subpage disable)
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37
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38 // 1st-level or large (1MB) page directory (always maps 1MB memory)
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39 #define PDE_SHIFT 20 // shift how many bits to get PDE index
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40 #define PDE_SZ (1 << PDE_SHIFT)
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41 #define PDE_MASK (PDE_SZ - 1) // offset for page directory entries
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42 #define PDE_IDX(v) ((uint)(v) >> PDE_SHIFT) // index for page table entry
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43
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44 // 2nd-level page table
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45 #define PTE_SHIFT 12 // shift how many bits to get PTE index
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46 #define PTE_IDX(v) (((uint)(v) >> PTE_SHIFT) & (NUM_PTE - 1))
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47 #define PTE_SZ (1 << PTE_SHIFT)
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48 #define PTE_ADDR(v) align_dn (v, PTE_SZ)
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49 #define PTE_AP(pte) (((pte) >> 4) & 0x03)
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50
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51 // size of two-level page tables
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52 #define UADDR_BITS 28 // maximum user-application memory, 256MB
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53 #define UADDR_SZ (1 << UADDR_BITS) // maximum user address space size
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54
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55 // must have NUM_UPDE == NUM_PTE
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56 #define NUM_UPDE (1 << (UADDR_BITS - PDE_SHIFT)) // # of PDE for user space
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57 #define NUM_PTE (1 << (PDE_SHIFT - PTE_SHIFT)) // how many PTE in a PT
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58
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59 #define PT_SZ (NUM_PTE << 2) // user page table size (1K)
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60 #define PT_ADDR(v) align_dn(v, PT_SZ) // physical address of the PT
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61 #define PT_ORDER 10
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62
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63 #endif |
