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comparison src/mmu.h @ 0:83c23a36980d

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author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Fri, 26 May 2017 23:11:05 +0900
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1 // Definition for ARM MMU
2 #ifndef MMU_INCLUDE
3 #define MMU_INCLUDE
4
5 // align_up/down: al must be of power of 2
6 #define align_up(sz, al) (((uint)(sz)+ (uint)(al)-1) & ~((uint)(al)-1))
7 #define align_dn(sz, al) ((uint)(sz) & ~((uint)(al)-1))
8 //
9 // Since ARMv6, you may use two page tables, one for kernel pages (TTBR1),
10 // and one for user pages (TTBR0). We use this architecture. Memory address
11 // lower than UVIR_BITS^2 is translated by TTBR0, while higher memory is
12 // translated by TTBR1.
13 // Kernel pages are create statically during system initialization. It use
14 // 1MB page mapping. User pages use 4K pages.
15 //
16
17
18 // access permission for page directory/page table entries.
19 #define AP_NA 0x00 // no access
20 #define AP_KO 0x01 // privilaged access, kernel: RW, user: no access
21 #define AP_KUR 0x02 // no write access from user, read allowed
22 #define AP_KU 0x03 // full access
23
24 // domain definition for page table entries
25 #define DM_NA 0x00 // any access causing a domain fault
26 #define DM_CLIENT 0x01 // any access checked against TLB (page table)
27 #define DM_RESRVED 0x02 // reserved
28 #define DM_MANAGER 0x03 // no access check
29
30 #define PE_CACHE (1 << 3)// cachable
31 #define PE_BUF (1 << 2)// bufferable
32
33 #define PE_TYPES 0x03 // mask for page type
34 #define KPDE_TYPE 0x02 // use "section" type for kernel page directory
35 #define UPDE_TYPE 0x01 // use "coarse page table" for user page directory
36 #define PTE_TYPE 0x02 // executable user page(subpage disable)
37
38 // 1st-level or large (1MB) page directory (always maps 1MB memory)
39 #define PDE_SHIFT 20 // shift how many bits to get PDE index
40 #define PDE_SZ (1 << PDE_SHIFT)
41 #define PDE_MASK (PDE_SZ - 1) // offset for page directory entries
42 #define PDE_IDX(v) ((uint)(v) >> PDE_SHIFT) // index for page table entry
43
44 // 2nd-level page table
45 #define PTE_SHIFT 12 // shift how many bits to get PTE index
46 #define PTE_IDX(v) (((uint)(v) >> PTE_SHIFT) & (NUM_PTE - 1))
47 #define PTE_SZ (1 << PTE_SHIFT)
48 #define PTE_ADDR(v) align_dn (v, PTE_SZ)
49 #define PTE_AP(pte) (((pte) >> 4) & 0x03)
50
51 // size of two-level page tables
52 #define UADDR_BITS 28 // maximum user-application memory, 256MB
53 #define UADDR_SZ (1 << UADDR_BITS) // maximum user address space size
54
55 // must have NUM_UPDE == NUM_PTE
56 #define NUM_UPDE (1 << (UADDR_BITS - PDE_SHIFT)) // # of PDE for user space
57 #define NUM_PTE (1 << (PDE_SHIFT - PTE_SHIFT)) // how many PTE in a PT
58
59 #define PT_SZ (NUM_PTE << 2) // user page table size (1K)
60 #define PT_ADDR(v) align_dn(v, PT_SZ) // physical address of the PT
61 #define PT_ORDER 10
62
63 #endif