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comparison io.c @ 34:2032755628dc

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fix for nitros9
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 15 Jul 2018 14:18:19 +0900
parents 7b1b25ff010a
children 01519215ec70
comparison
equal deleted inserted replaced
33:7c5379eb406e 34:2032755628dc
1 /* 6808 Simulator V092 1 /* 6808 Simulator V092
2 created 1993,1994 by L.C. Benschop. copyleft (c) 1994-2014 2 created 1993,1994 by L.C. Benschop. copyleft (c) 1994-2014
3 by the sbc09 team, see AUTHORS for more details. license: 3 by the sbc09 team, see AUTHORS for more details. license: GNU
4 GNU General Public License version 2, see LICENSE for more 4 General Public License version 2, see LICENSE for more details.
5 details.
6 5
7 This program simulates a 6809 processor. 6 This program simulates a 6809 processor.
8 7
9 System dependencies: short must be 16 bits. 8 System dependencies: short must be 16 bits.
10 char must be 8 bits. 9 char must be 8 bits.
47 * IO Map ( can be overrupped by ROM ) 46 * IO Map ( can be overrupped by ROM )
48 * 47 *
49 * IOPAGE ~ IOPAGE+0x7f 48 * IOPAGE ~ IOPAGE+0x7f
50 * for OS9 level2 49 * for OS9 level2
51 * IOPAGE 0xff80 means ioport beging 0xff80 but IOPAGE itself starts 0xff00 50 * IOPAGE 0xff80 means ioport beging 0xff80 but IOPAGE itself starts 0xff00
52 * 0xfe00-0xff7f, 0xffe0-0xffff can be used as ROM in fixed area 51 * 0xfe00-0xff7f, 0xffe0-0xffff can be used as RAM in fixed area in level2
52 * and these are ROM in level1
53 *
53 * 54 *
54 * IOPAGE + 0x00 ACIA control 55 * IOPAGE + 0x00 ACIA control
55 * IOPAGE + 0x01 ACIA data 56 * IOPAGE + 0x01 ACIA data
56 * 57 *
57 * IOPAGE + 0x11 MMU Taskreg 0 system map, 1 user map 58 * IOPAGE + 0x11 MMU Taskreg 0 system map, 1 user map
64 * phy addr = phymem[ ( mmu[ adr >> 13 ] <<13 ) + (adr & 0x1fff ) ] 65 * phy addr = phymem[ ( mmu[ adr >> 13 ] <<13 ) + (adr & 0x1fff ) ]
65 * tr=0 mmu=IOPAGE+0xa0 66 * tr=0 mmu=IOPAGE+0xa0
66 * tr=1 mmu=IOPAGE+0xa8 67 * tr=1 mmu=IOPAGE+0xa8
67 * 68 *
68 * IOPAGE + 0x30 Timer control 0x8f start timer/0x80 stop timer/0x04 update date 69 * IOPAGE + 0x30 Timer control 0x8f start timer/0x80 stop timer/0x04 update date
70 * read 0x10 bit menas timer
69 * IOPAGE + 0x31- YY/MM/DD/HH/MM/SS 71 * IOPAGE + 0x31- YY/MM/DD/HH/MM/SS
70 * 72 *
71 * IOPAGE + 0x40 Disk control 0x81 read/0x55 write 0 ... ok / 0xff .. error 73 * IOPAGE + 0x40 Disk control 0x81 read/0x55 write 0 ... ok / 0xff .. error
72 * IOPAGE + 0x41 drive no 74 * IOPAGE + 0x41 drive no
73 * IOPAGE + 0x42 LSN2 75 * IOPAGE + 0x42 LSN2
92 unsigned char xmbuf[132]; 94 unsigned char xmbuf[132];
93 int xidx; 95 int xidx;
94 int acknak; 96 int acknak;
95 int rcvdnak; 97 int rcvdnak;
96 int blocknum; 98 int blocknum;
99 int timer_irq = 2 ; // 2 = FIRQ, 1 = IRQ
97 100
98 FILE *infile; 101 FILE *infile;
99 FILE *xfile; 102 FILE *xfile;
100 FILE *logfile; 103 FILE *logfile;
101 FILE *disk[] = {0,0}; 104 FILE *disk[] = {0,0};
192 int do_input(int a) { 195 int do_input(int a) {
193 static int c, f = EOF; 196 static int c, f = EOF;
194 if (a == 0+(IOPAGE&0x1ff)) { 197 if (a == 0+(IOPAGE&0x1ff)) {
195 if (f == EOF) 198 if (f == EOF)
196 f = char_input(); 199 f = char_input();
197 if (f != EOF) 200 if (f != EOF) {
198 c = f; 201 c = f;
199 return 2 + (f != EOF); 202 mem[(IOPAGE&0xfe00) + a] = c;
203 }
204 mem[(IOPAGE&0xfe00) + a] = c = 2 + (f != EOF);
205 return c;
200 } else if (a == 1+(IOPAGE&0x1ff)) { /*data port*/ 206 } else if (a == 1+(IOPAGE&0x1ff)) { /*data port*/
201 if (f == EOF) 207 if (f == EOF)
202 f = char_input(); 208 f = char_input();
203 if (f != EOF) { 209 if (f != EOF) {
204 c = f; 210 c = f;
205 f = EOF; 211 f = EOF;
212 mem[(IOPAGE&0xfe00) + a] = c;
206 } 213 }
207 return c; 214 return c;
208 } 215 }
209 return mem[(IOPAGE&0xfe00) + a]; 216 return mem[(IOPAGE&0xfe00) + a];
210 } 217 }
272 if (a==0x30+(IOPAGE&0x1ff) && c==0x8f) { 279 if (a==0x30+(IOPAGE&0x1ff) && c==0x8f) {
273 timercontrol.it_interval.tv_sec = 0; 280 timercontrol.it_interval.tv_sec = 0;
274 timercontrol.it_interval.tv_usec = 20000; 281 timercontrol.it_interval.tv_usec = 20000;
275 timercontrol.it_value.tv_sec = 0; 282 timercontrol.it_value.tv_sec = 0;
276 timercontrol.it_value.tv_usec = 20000; 283 timercontrol.it_value.tv_usec = 20000;
284 timer_irq = 1;
277 setitimer(ITIMER_REAL, &timercontrol, NULL); 285 setitimer(ITIMER_REAL, &timercontrol, NULL);
286 mem[(IOPAGE&0xfe00)+a]=c;
278 } else if (a==0x30+(IOPAGE&0x1ff) && c==0x80) { 287 } else if (a==0x30+(IOPAGE&0x1ff) && c==0x80) {
279 timercontrol.it_interval.tv_sec = 0; 288 timercontrol.it_interval.tv_sec = 0;
280 timercontrol.it_interval.tv_usec = 0; 289 timercontrol.it_interval.tv_usec = 0;
281 setitimer(ITIMER_REAL, &timercontrol, NULL); 290 setitimer(ITIMER_REAL, &timercontrol, NULL);
291 mem[(IOPAGE&0xfe00)+a]=c;
282 } else if (a==0x30+(IOPAGE&0x1ff) && c==0x04) { 292 } else if (a==0x30+(IOPAGE&0x1ff) && c==0x04) {
283 time_t tm = time(0); 293 time_t tm = time(0);
284 struct tm *t = localtime(&tm); 294 struct tm *t = localtime(&tm);
285 mem[IOPAGE+0x31] = t->tm_year; 295 mem[IOPAGE+0x31] = t->tm_year;
286 mem[IOPAGE+0x32] = t->tm_mon; 296 mem[IOPAGE+0x32] = t->tm_mon;
336 } 346 }
337 347
338 void timehandler(int sig) { 348 void timehandler(int sig) {
339 attention = 1; 349 attention = 1;
340 irq = 2; 350 irq = 2;
341 signal(SIGALRM, timehandler); 351 mem[(IOPAGE&0xfe00)+0x30] |= 0x10 ;
352 // signal(SIGALRM, timehandler);
342 } 353 }
343 354
344 void handler(int sig) { 355 void handler(int sig) {
345 escape = 1; 356 escape = 1;
346 attention = 1; 357 attention = 1;