--- a/io.c	Mon Jul 02 21:39:55 2018 +0900
+++ b/io.c	Wed Jul 04 14:03:56 2018 +0900
@@ -44,23 +44,34 @@
 #include "v09.h"
 
 /*
- *      IO Map
+ *   IO Map ( can be overrupped by ROM )
+ *
+ *   IOPAGE ~ IOPAGE+0xff
  *
- *   0xe000 - 0xe100
+ *   IOPAGE + 0x00   ACIA  control
+ *   IOPAGE + 0x01   ACIA  data
  *
- *   0xe000   ACIA  control
- *   0xe001   ACIA  data
+ *   IOPAGE + 0x10   Timer control       0x8f start timer/0x80 stop timer/0x04 update date
+ *   IOPAGE + 0x11-  YY/MM/DD/HH/MM/SS
  *
- *   0xe010   Timer control       0x8f start timer/0x80 stop timer/0x04 update date
- *   0xe011-  YY/MM/DD/HH/MM/SS
+ *   IOPAGE + 0x20   Disk control        0x81 read/0x55 write   0 ... ok / 0xff .. error
+ *   IOPAGE + 0x21   drive no
+ *   IOPAGE + 0x22   LSN2
+ *   IOPAGE + 0x23   LSN1
+ *   IOPAGE + 0x24   LSN0
+ *   IOPAGE + 0x25   ADR2
+ *   IOPAGE + 0x26   ADR1
  *
- *   0xe020   Disk control        0x81 read/0x55 write   0 ... ok / 0xff .. error
- *   0xe021   drive no
- *   0xe022   LSN2
- *   0xe023   LSN1
- *   0xe024   LSN0
- *   0xe025   ADR2
- *   0xe026   ADR1
+ *   IOPAGE + 0x91   MMU Taskreg         0  system map, 1 user map
+ *   IOPAGE + 0xa0-0xa7   MMU reg        system map
+ *   IOPAGE + 0xa8-0xaf   MMU reg        user   map
+ *
+ *        on reset tr==0 and only IOPAGE is valid
+ *        translatation occur only on non-IOPAGE
+ *        mem == phymem + 0x70000
+ *        phy addr = phymem[ ( mmu[ adr >> 13 ] <<13 ) + (adr & 0x1fff ) ]
+ *            tr=0  mmu=IOPAGE+0xa0
+ *            tr=1  mmu=IOPAGE+0xa8
  *
  */
 
@@ -180,12 +191,8 @@
                         f = EOF;
                 }
                 return c;
-        } else if ((a&0xf0) == 0x10) { /* timer */
-                return mem[IOPAGE + a];
-        } else if ((a&0xf0) == 0x20) { /* disk */
-                return mem[IOPAGE + a];
         }
-        return 0;
+        return mem[IOPAGE + a];
 }
 
 void do_output(int a, int c) {