/*
 Copyright (C) 2002, Shinji Kono, University of the Ryukyus
                                  PRESTO21

 Everyone is permitted to copy and distribute verbatim copies
 of this license, but changing it is not allowed.  You can also
 use this wording to make the terms for other programs.

 send your comments to kono@ie.u-ryukyu.ac.jp
 $Id: verilog.pl,v 1.1 2007/08/30 03:44:35 kono Exp $
*/

:- dynamic st_variables/2.

% already in kiss.pl
set_verilog_var(In) :- 
	variable_list(L),
	(retract(st_variables(_));true),!,
	assert(st_variables(In,L)).

/* 
module check001(clk,inputs..,outputs...)
input clk;
input inputs;
output outputs;
reg outputs;
reg state;
initial state = 0;
    always @(posedge clk) begin
        case (state)
        0: if (inputs condtion) begin
            outputs set
           end else if (inputs condtion) begin
            outputs set
              ...
           end
        endcase
    end
endmodule
  */

verilog(File) :-
	tell(File),
	verilog,
	told.

verilog :-
	write('module check001(clk,'),
	(variable_list(L);L=[]),
	(st_variables(In,_);In=[]),
	delete(L,In,Out),
	write_verilog_var_list(L),
	write(')'),nl,write('input clk,'),nl,
	write_verilog_var_list(In),
	write(';'),nl,write('output '),nl,
	write_verilog_var_list(Out),
	write(';'),nl,write('reg '),nl,
	write_verilog_var_list(Out),
	write(';'),nl,write('initial state = 0;'),nl,
	write('    always @(posedge clk) begin'),nl,
	write('        case (state)'),nl,
	verilog(In,Out),
	write('        endcase'),nl,
	write('    end'),nl,
	write('endmodule'),nl.

verilog(In,Out) :-
	bagof((D,Cond),(state(S,Cond,D)),L),
	write_verilog(S,L,In,Out),fail.
verilog(_,_) :- nl.

write_verilog_var_list([]):-!.
write_verilog_var_list([H]):-!,write(H).
write_verilog_var_list([H|L]):-!,write(H),put(","),   % " "
	write_verilog_var_list(L).

%        0: if jinputs condtion) begin
%            outputs set
write_verilog(S,[(D,Cond)|L],In,Out) :-
	put(9), write_verilog_state(S),write(' if ('),
	write_verilog_cond(Cond,In),write(') begin'),nl,
	put(9),write('   '),
	write_verilog_output(Cond,D,Out),
	nl,
	write_verilog(L,In,Out).
%           end
%        endcase
write_verilog([],_In,_Out) :-
	nl,put(9),write('    end'),nl,put(9),write('endcase'),nl,!.
%           end else if (inputs condtion) begin
write_verilog([(D,Cond)|L],In,Out) :-
	nl,put(9),write('    end else if ('),
	write_verilog_cond(Cond,In),write(') begin'),nl,
	put(9),write('   '),
	write_verilog_output(Cond,D,Out),write(') begin'),nl,
	write_verilog(L,In,Out).

write_verilog_state(true) :-!,fail.
write_verilog_state(false) :-	!,fail.
write_verilog_state(S) :-	!,
       write(S),write(':').

write_verilog_cond([],_In) :-!.
write_verilog_cond([not(H)],In) :-member(H,In),!,
	put("!"),write(H).
write_verilog_cond([H],In) :-member(H,In),!,
	write(H).
write_verilog_cond([not(H)|L],In) :-member(H,In),!,
	put("!"),write(H),write('&&'),
	write_verilog_cond(L,In).
write_verilog_cond([H|L],In) :-member(H,In),!,
	write(H),write('&&'),
	write_verilog_cond(L,In).
write_verilog_cond([_H|L],In) :-
	write_verilog_cond(L,In).

write_verilog_output([],D,_Out) :-!,
	write('state='),
	write_verilog_state(D),put(";").
write_verilog_output([not(H)|L],D,Out) :-member(H,Out),!,
	write(H),write('=0;'),
	write_verilog_output(L,D,Out).
write_verilog_output([H|L],D,Out) :-member(H,Out),!,
	write(H),write('=1;'),
	write_verilog_output(L,D,Out).
write_verilog_output([_H|L],D,Out) :-
	write_verilog_output(L,D,Out).

% delete([],_,[]) :-!.
% delete([H|X],L,Y) :- member(H,L),!,delete(X,L,Y).
% delete([H|X],L,[H|Y]) :- delete(X,L,Y).

write_verilog_var([],_):-!.
write_verilog_var([H|L],Cond) :- member(H,Cond),!,write(1),
	write_verilog_var(L,Cond).
write_verilog_var([H|L],Cond) :- member(not(H),Cond),!,write(0),
	write_verilog_var(L,Cond).
write_verilog_var([_|L],Cond) :- write(-),
	write_verilog_var(L,Cond).


/* end */