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111
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1 /* Machine description for AArch64 architecture.
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2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
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3 Contributed by ARM Ltd.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but
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13 WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21
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22 #ifndef GCC_AARCH64_PROTOS_H
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23 #define GCC_AARCH64_PROTOS_H
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24
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25 #include "input.h"
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26
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27 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through
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28 high and lo relocs that calculate the base address using a PC
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29 relative reloc.
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30 So to get the address of foo, we generate
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31 adrp x0, foo
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32 add x0, x0, :lo12:foo
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33
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34 To load or store something to foo, we could use the corresponding
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35 load store variants that generate an
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36 ldr x0, [x0,:lo12:foo]
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37 or
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38 str x1, [x0, :lo12:foo]
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39
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40 This corresponds to the small code model of the compiler.
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41
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42 SYMBOL_SMALL_GOT_4G: Similar to the one above but this
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43 gives us the GOT entry of the symbol being referred to :
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44 Thus calculating the GOT entry for foo is done using the
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45 following sequence of instructions. The ADRP instruction
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46 gets us to the page containing the GOT entry of the symbol
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47 and the got_lo12 gets us the actual offset in it, together
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48 the base and offset, we can address 4G size GOT table.
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49
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50 adrp x0, :got:foo
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51 ldr x0, [x0, :gotoff_lo12:foo]
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52
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53 This corresponds to the small PIC model of the compiler.
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54
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55 SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol
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56 restricted within 28K GOT table size.
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57
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58 ldr reg, [gp, #:gotpage_lo15:sym]
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59
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60 This corresponds to -fpic model for small memory model of the compiler.
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61
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62 SYMBOL_SMALL_TLSGD
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63 SYMBOL_SMALL_TLSDESC
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64 SYMBOL_SMALL_TLSIE
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65 SYMBOL_TINY_TLSIE
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66 SYMBOL_TLSLE12
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67 SYMBOL_TLSLE24
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68 SYMBOL_TLSLE32
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69 SYMBOL_TLSLE48
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70 Each of these represents a thread-local symbol, and corresponds to the
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71 thread local storage relocation operator for the symbol being referred to.
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72
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73 SYMBOL_TINY_ABSOLUTE
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74
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75 Generate symbol accesses as a PC relative address using a single
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76 instruction. To compute the address of symbol foo, we generate:
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77
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78 ADR x0, foo
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79
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80 SYMBOL_TINY_GOT
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81
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82 Generate symbol accesses via the GOT using a single PC relative
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83 instruction. To compute the address of symbol foo, we generate:
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84
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85 ldr t0, :got:foo
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86
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87 The value of foo can subsequently read using:
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88
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89 ldrb t0, [t0]
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90
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91 SYMBOL_FORCE_TO_MEM : Global variables are addressed using
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92 constant pool. All variable addresses are spilled into constant
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93 pools. The constant pools themselves are addressed using PC
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94 relative accesses. This only works for the large code model.
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95 */
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96 enum aarch64_symbol_type
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97 {
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98 SYMBOL_SMALL_ABSOLUTE,
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99 SYMBOL_SMALL_GOT_28K,
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100 SYMBOL_SMALL_GOT_4G,
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101 SYMBOL_SMALL_TLSGD,
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102 SYMBOL_SMALL_TLSDESC,
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103 SYMBOL_SMALL_TLSIE,
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104 SYMBOL_TINY_ABSOLUTE,
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105 SYMBOL_TINY_GOT,
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106 SYMBOL_TINY_TLSIE,
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107 SYMBOL_TLSLE12,
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108 SYMBOL_TLSLE24,
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109 SYMBOL_TLSLE32,
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110 SYMBOL_TLSLE48,
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111 SYMBOL_FORCE_TO_MEM
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112 };
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113
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114 /* A set of tuning parameters contains references to size and time
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115 cost models and vectors for address cost calculations, register
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116 move costs and memory move costs. */
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117
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118 /* Scaled addressing modes can vary cost depending on the mode of the
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119 value to be loaded/stored. QImode values cannot use scaled
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120 addressing modes. */
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121
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122 struct scale_addr_mode_cost
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123 {
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124 const int hi;
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125 const int si;
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126 const int di;
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127 const int ti;
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128 };
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129
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130 /* Additional cost for addresses. */
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131 struct cpu_addrcost_table
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132 {
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133 const struct scale_addr_mode_cost addr_scale_costs;
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134 const int pre_modify;
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135 const int post_modify;
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136 const int register_offset;
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137 const int register_sextend;
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138 const int register_zextend;
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139 const int imm_offset;
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140 };
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141
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142 /* Additional costs for register copies. Cost is for one register. */
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143 struct cpu_regmove_cost
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144 {
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145 const int GP2GP;
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146 const int GP2FP;
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147 const int FP2GP;
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148 const int FP2FP;
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149 };
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150
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151 /* Cost for vector insn classes. */
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152 struct cpu_vector_cost
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153 {
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154 const int scalar_int_stmt_cost; /* Cost of any int scalar operation,
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155 excluding load and store. */
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156 const int scalar_fp_stmt_cost; /* Cost of any fp scalar operation,
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157 excluding load and store. */
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158 const int scalar_load_cost; /* Cost of scalar load. */
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159 const int scalar_store_cost; /* Cost of scalar store. */
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160 const int vec_int_stmt_cost; /* Cost of any int vector operation,
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161 excluding load, store, permute,
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162 vector-to-scalar and
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163 scalar-to-vector operation. */
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164 const int vec_fp_stmt_cost; /* Cost of any fp vector operation,
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165 excluding load, store, permute,
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166 vector-to-scalar and
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167 scalar-to-vector operation. */
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168 const int vec_permute_cost; /* Cost of permute operation. */
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169 const int vec_to_scalar_cost; /* Cost of vec-to-scalar operation. */
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170 const int scalar_to_vec_cost; /* Cost of scalar-to-vector
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171 operation. */
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172 const int vec_align_load_cost; /* Cost of aligned vector load. */
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173 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
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174 const int vec_unalign_store_cost; /* Cost of unaligned vector store. */
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175 const int vec_store_cost; /* Cost of vector store. */
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176 const int cond_taken_branch_cost; /* Cost of taken branch. */
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177 const int cond_not_taken_branch_cost; /* Cost of not taken branch. */
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178 };
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179
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180 /* Branch costs. */
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181 struct cpu_branch_cost
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182 {
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183 const int predictable; /* Predictable branch or optimizing for size. */
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184 const int unpredictable; /* Unpredictable branch or optimizing for speed. */
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185 };
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186
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187 /* Control approximate alternatives to certain FP operators. */
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188 #define AARCH64_APPROX_MODE(MODE) \
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189 ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \
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190 ? (1 << ((MODE) - MIN_MODE_FLOAT)) \
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191 : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \
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192 ? (1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \
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193 + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \
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194 : (0))
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195 #define AARCH64_APPROX_NONE (0)
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196 #define AARCH64_APPROX_ALL (-1)
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197
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198 /* Allowed modes for approximations. */
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199 struct cpu_approx_modes
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200 {
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201 const unsigned int division; /* Division. */
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202 const unsigned int sqrt; /* Square root. */
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203 const unsigned int recip_sqrt; /* Reciprocal square root. */
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204 };
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205
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206 /* Cache prefetch settings for prefetch-loop-arrays. */
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207 struct cpu_prefetch_tune
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208 {
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209 const int num_slots;
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210 const int l1_cache_size;
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211 const int l1_cache_line_size;
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212 const int l2_cache_size;
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213 const int default_opt_level;
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214 };
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215
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216 struct tune_params
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217 {
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218 const struct cpu_cost_table *insn_extra_cost;
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219 const struct cpu_addrcost_table *addr_cost;
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220 const struct cpu_regmove_cost *regmove_cost;
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221 const struct cpu_vector_cost *vec_costs;
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222 const struct cpu_branch_cost *branch_costs;
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223 const struct cpu_approx_modes *approx_modes;
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224 int memmov_cost;
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225 int issue_rate;
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226 unsigned int fusible_ops;
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227 int function_align;
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228 int jump_align;
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229 int loop_align;
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230 int int_reassoc_width;
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231 int fp_reassoc_width;
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232 int vec_reassoc_width;
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233 int min_div_recip_mul_sf;
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234 int min_div_recip_mul_df;
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235 /* Value for aarch64_case_values_threshold; or 0 for the default. */
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236 unsigned int max_case_values;
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237 /* An enum specifying how to take into account CPU autoprefetch capabilities
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238 during instruction scheduling:
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239 - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account.
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240 - AUTOPREFETCHER_WEAK: Attempt to sort sequences of loads/store in order of
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241 offsets but allow the pipeline hazard recognizer to alter that order to
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242 maximize multi-issue opportunities.
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243 - AUTOPREFETCHER_STRONG: Attempt to sort sequences of loads/store in order of
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244 offsets and prefer this even if it restricts multi-issue opportunities. */
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245
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246 enum aarch64_autoprefetch_model
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247 {
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248 AUTOPREFETCHER_OFF,
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249 AUTOPREFETCHER_WEAK,
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250 AUTOPREFETCHER_STRONG
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251 } autoprefetcher_model;
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252
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253 unsigned int extra_tuning_flags;
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254
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255 /* Place prefetch struct pointer at the end to enable type checking
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256 errors when tune_params misses elements (e.g., from erroneous merges). */
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257 const struct cpu_prefetch_tune *prefetch;
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258 };
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259
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260 #define AARCH64_FUSION_PAIR(x, name) \
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261 AARCH64_FUSE_##name##_index,
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262 /* Supported fusion operations. */
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263 enum aarch64_fusion_pairs_index
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264 {
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265 #include "aarch64-fusion-pairs.def"
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266 AARCH64_FUSE_index_END
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267 };
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268
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269 #define AARCH64_FUSION_PAIR(x, name) \
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270 AARCH64_FUSE_##name = (1u << AARCH64_FUSE_##name##_index),
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271 /* Supported fusion operations. */
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272 enum aarch64_fusion_pairs
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273 {
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274 AARCH64_FUSE_NOTHING = 0,
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275 #include "aarch64-fusion-pairs.def"
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276 AARCH64_FUSE_ALL = (1u << AARCH64_FUSE_index_END) - 1
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277 };
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278
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279 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
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280 AARCH64_EXTRA_TUNE_##name##_index,
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281 /* Supported tuning flags indexes. */
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282 enum aarch64_extra_tuning_flags_index
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283 {
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284 #include "aarch64-tuning-flags.def"
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285 AARCH64_EXTRA_TUNE_index_END
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286 };
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287
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288
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289 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
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290 AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index),
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291 /* Supported tuning flags. */
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292 enum aarch64_extra_tuning_flags
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293 {
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294 AARCH64_EXTRA_TUNE_NONE = 0,
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295 #include "aarch64-tuning-flags.def"
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296 AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1
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297 };
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298
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299 /* Enum describing the various ways that the
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300 aarch64_parse_{arch,tune,cpu,extension} functions can fail.
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301 This way their callers can choose what kind of error to give. */
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302
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303 enum aarch64_parse_opt_result
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304 {
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305 AARCH64_PARSE_OK, /* Parsing was successful. */
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306 AARCH64_PARSE_MISSING_ARG, /* Missing argument. */
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307 AARCH64_PARSE_INVALID_FEATURE, /* Invalid feature modifier. */
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308 AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */
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309 };
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310
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311 /* Enum to distinguish which type of check is to be done in
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312 aarch64_simd_valid_immediate. This is used as a bitmask where
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313 AARCH64_CHECK_MOV has both bits set. Thus AARCH64_CHECK_MOV will
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314 perform all checks. Adding new types would require changes accordingly. */
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315 enum simd_immediate_check {
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316 AARCH64_CHECK_ORR = 1 << 0,
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317 AARCH64_CHECK_BIC = 1 << 1,
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318 AARCH64_CHECK_MOV = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
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319 };
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320
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321 extern struct tune_params aarch64_tune_params;
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322
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323 HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
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324 int aarch64_get_condition_code (rtx);
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325 bool aarch64_address_valid_for_prefetch_p (rtx, bool);
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326 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
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327 unsigned HOST_WIDE_INT aarch64_and_split_imm1 (HOST_WIDE_INT val_in);
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328 unsigned HOST_WIDE_INT aarch64_and_split_imm2 (HOST_WIDE_INT val_in);
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329 bool aarch64_and_bitmask_imm (unsigned HOST_WIDE_INT val_in, machine_mode mode);
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330 int aarch64_branch_cost (bool, bool);
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331 enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
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332 bool aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode);
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333 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
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334 bool aarch64_constant_address_p (rtx);
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335 bool aarch64_emit_approx_div (rtx, rtx, rtx);
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336 bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
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337 void aarch64_expand_call (rtx, rtx, bool);
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338 bool aarch64_expand_movmem (rtx *);
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339 bool aarch64_float_const_zero_rtx_p (rtx);
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340 bool aarch64_float_const_rtx_p (rtx);
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341 bool aarch64_function_arg_regno_p (unsigned);
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342 bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs);
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343 bool aarch64_gen_movmemqi (rtx *);
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344 bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *);
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345 bool aarch64_is_extend_from_extract (scalar_int_mode, rtx, rtx);
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346 bool aarch64_is_long_call_p (rtx);
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347 bool aarch64_is_noplt_call_p (rtx);
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348 bool aarch64_label_mentioned_p (rtx);
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349 void aarch64_declare_function_name (FILE *, const char*, tree);
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350 bool aarch64_legitimate_pic_operand_p (rtx);
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351 bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx);
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352 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
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353 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
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354 bool aarch64_mov_operand_p (rtx, machine_mode);
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355 rtx aarch64_reverse_mask (machine_mode);
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356 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT);
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357 char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
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358 char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned,
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359 enum simd_immediate_check w = AARCH64_CHECK_MOV);
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360 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);
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361 bool aarch64_regno_ok_for_base_p (int, bool);
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362 bool aarch64_regno_ok_for_index_p (int, bool);
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363 bool aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *fail);
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364 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode,
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365 bool high);
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366 bool aarch64_simd_imm_zero_p (rtx, machine_mode);
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367 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode);
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368 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
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369 bool aarch64_simd_valid_immediate (rtx, machine_mode, bool,
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370 struct simd_immediate_info *,
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371 enum simd_immediate_check w = AARCH64_CHECK_MOV);
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372 bool aarch64_split_dimode_const_store (rtx, rtx);
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373 bool aarch64_symbolic_address_p (rtx);
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374 bool aarch64_uimm12_shift (HOST_WIDE_INT);
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375 bool aarch64_use_return_insn_p (void);
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376 const char *aarch64_mangle_builtin_type (const_tree);
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377 const char *aarch64_output_casesi (rtx *);
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378
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379 enum aarch64_symbol_type aarch64_classify_symbol (rtx, rtx);
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380 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
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381 enum reg_class aarch64_regno_regclass (unsigned);
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382 int aarch64_asm_preferred_eh_data_format (int, int);
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383 int aarch64_fpconst_pow_of_2 (rtx);
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384 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
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385 machine_mode);
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386 int aarch64_uxt_size (int, HOST_WIDE_INT);
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387 int aarch64_vec_fpconst_pow_of_2 (rtx);
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388 rtx aarch64_eh_return_handler_rtx (void);
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389 rtx aarch64_mask_from_zextract_ops (rtx, rtx);
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390 const char *aarch64_output_move_struct (rtx *operands);
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391 rtx aarch64_return_addr (int, rtx);
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392 rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT);
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393 bool aarch64_simd_mem_operand_p (rtx);
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394 rtx aarch64_simd_vect_par_cnst_half (machine_mode, bool);
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395 rtx aarch64_tls_get_addr (void);
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396 tree aarch64_fold_builtin (tree, int, tree *, bool);
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397 unsigned aarch64_dbx_register_number (unsigned);
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398 unsigned aarch64_trampoline_size (void);
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399 void aarch64_asm_output_labelref (FILE *, const char *);
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400 void aarch64_cpu_cpp_builtins (cpp_reader *);
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401 const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *);
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402 const char * aarch64_output_probe_stack_range (rtx, rtx);
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403 void aarch64_err_no_fpadvsimd (machine_mode, const char *);
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404 void aarch64_expand_epilogue (bool);
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405 void aarch64_expand_mov_immediate (rtx, rtx);
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406 void aarch64_expand_prologue (void);
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407 void aarch64_expand_vector_init (rtx, rtx);
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408 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx,
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409 const_tree, unsigned);
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410 void aarch64_init_expanders (void);
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411 void aarch64_init_simd_builtins (void);
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412 void aarch64_emit_call_insn (rtx);
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413 void aarch64_register_pragmas (void);
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414 void aarch64_relayout_simd_types (void);
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415 void aarch64_reset_previous_fndecl (void);
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416 bool aarch64_return_address_signing_enabled (void);
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417 void aarch64_save_restore_target_globals (tree);
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418
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419 /* Initialize builtins for SIMD intrinsics. */
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420 void init_aarch64_simd_builtins (void);
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421
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422 void aarch64_simd_emit_reg_reg_move (rtx *, machine_mode, unsigned int);
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423
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424 /* Expand builtins for SIMD intrinsics. */
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425 rtx aarch64_simd_expand_builtin (int, tree, rtx);
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426
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427 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
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428
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429 void aarch64_split_128bit_move (rtx, rtx);
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430
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431 bool aarch64_split_128bit_move_p (rtx, rtx);
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432
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433 void aarch64_split_simd_combine (rtx, rtx, rtx);
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434
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435 void aarch64_split_simd_move (rtx, rtx);
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436
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437 /* Check for a legitimate floating point constant for FMOV. */
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438 bool aarch64_float_const_representable_p (rtx);
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439
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440 #if defined (RTX_CODE)
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441
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442 bool aarch64_legitimate_address_p (machine_mode, rtx, RTX_CODE, bool);
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443 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx);
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444 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx);
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445 rtx aarch64_load_tp (rtx);
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446
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447 void aarch64_expand_compare_and_swap (rtx op[]);
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448 void aarch64_split_compare_and_swap (rtx op[]);
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449 void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx);
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450
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451 bool aarch64_atomic_ldop_supported_p (enum rtx_code);
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452 void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
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453 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
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454
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455 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE);
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456 #endif /* RTX_CODE */
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457
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458 void aarch64_init_builtins (void);
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459
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460 bool aarch64_process_target_attr (tree, const char*);
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461 void aarch64_override_options_internal (struct gcc_options *);
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462
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463 rtx aarch64_expand_builtin (tree exp,
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464 rtx target,
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465 rtx subtarget ATTRIBUTE_UNUSED,
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466 machine_mode mode ATTRIBUTE_UNUSED,
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467 int ignore ATTRIBUTE_UNUSED);
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468 tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED);
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469 tree aarch64_builtin_rsqrt (unsigned int);
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470 tree aarch64_builtin_vectorized_function (unsigned int, tree, tree);
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471
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472 extern void aarch64_split_combinev16qi (rtx operands[3]);
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473 extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
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474 extern bool aarch64_madd_needs_nop (rtx_insn *);
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475 extern void aarch64_final_prescan_insn (rtx_insn *);
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476 extern bool
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477 aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
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478 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
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479 int aarch64_ccmp_mode_to_code (machine_mode mode);
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480
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481 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
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482 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);
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483 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode);
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484
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485 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
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486 tree, HOST_WIDE_INT);
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487
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488 /* Defined in common/config/aarch64-common.c. */
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489 bool aarch64_handle_option (struct gcc_options *, struct gcc_options *,
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490 const struct cl_decoded_option *, location_t);
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491 const char *aarch64_rewrite_selected_cpu (const char *name);
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492 enum aarch64_parse_opt_result aarch64_parse_extension (const char *,
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493 unsigned long *);
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494 std::string aarch64_get_extension_string_for_isa_flags (unsigned long,
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495 unsigned long);
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496
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497 rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt);
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498
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499 #endif /* GCC_AARCH64_PROTOS_H */
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