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111
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1 /* Machine description for AArch64 architecture.
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2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
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3 Contributed by ARM Ltd.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but
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13 WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21
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22 #ifndef GCC_AARCH64_H
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23 #define GCC_AARCH64_H
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24
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25 /* Target CPU builtins. */
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26 #define TARGET_CPU_CPP_BUILTINS() \
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27 aarch64_cpu_cpp_builtins (pfile)
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28
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29
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30
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31 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
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32
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33 /* Target machine storage layout. */
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34
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35 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
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36 if (GET_MODE_CLASS (MODE) == MODE_INT \
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37 && GET_MODE_SIZE (MODE) < 4) \
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38 { \
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39 if (MODE == QImode || MODE == HImode) \
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40 { \
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41 MODE = SImode; \
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42 } \
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43 }
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44
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45 /* Bits are always numbered from the LSBit. */
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46 #define BITS_BIG_ENDIAN 0
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47
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48 /* Big/little-endian flavour. */
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49 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
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50 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
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51
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52 /* AdvSIMD is supported in the default configuration, unless disabled by
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53 -mgeneral-regs-only or by the +nosimd extension. */
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54 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
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55 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
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56
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57 #define UNITS_PER_WORD 8
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58
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59 #define UNITS_PER_VREG 16
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60
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61 #define PARM_BOUNDARY 64
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62
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63 #define STACK_BOUNDARY 128
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64
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65 #define FUNCTION_BOUNDARY 32
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66
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67 #define EMPTY_FIELD_BOUNDARY 32
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68
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69 #define BIGGEST_ALIGNMENT 128
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70
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71 #define SHORT_TYPE_SIZE 16
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72
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73 #define INT_TYPE_SIZE 32
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74
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75 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
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76
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77 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
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78
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79 #define LONG_LONG_TYPE_SIZE 64
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80
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81 #define FLOAT_TYPE_SIZE 32
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82
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83 #define DOUBLE_TYPE_SIZE 64
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84
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85 #define LONG_DOUBLE_TYPE_SIZE 128
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86
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87 /* The architecture reserves all bits of the address for hardware use,
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88 so the vbit must go into the delta field of pointers to member
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89 functions. This is the same config as that in the AArch32
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90 port. */
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91 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
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92
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93 /* Align definitions of arrays, unions and structures so that
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94 initializations and copies can be made more efficient. This is not
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95 ABI-changing, so it only affects places where we can see the
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96 definition. Increasing the alignment tends to introduce padding,
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97 so don't do this when optimizing for size/conserving stack space. */
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98 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
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99 (((COND) && ((ALIGN) < BITS_PER_WORD) \
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100 && (TREE_CODE (EXP) == ARRAY_TYPE \
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101 || TREE_CODE (EXP) == UNION_TYPE \
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102 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
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103
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104 /* Align global data. */
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105 #define DATA_ALIGNMENT(EXP, ALIGN) \
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106 AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
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107
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108 /* Similarly, make sure that objects on the stack are sensibly aligned. */
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109 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
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110 AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
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111
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112 #define STRUCTURE_SIZE_BOUNDARY 8
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113
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114 /* Defined by the ABI */
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115 #define WCHAR_TYPE "unsigned int"
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116 #define WCHAR_TYPE_SIZE 32
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117
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118 /* Using long long breaks -ansi and -std=c90, so these will need to be
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119 made conditional for an LLP64 ABI. */
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120
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121 #define SIZE_TYPE "long unsigned int"
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122
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123 #define PTRDIFF_TYPE "long int"
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124
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125 #define PCC_BITFIELD_TYPE_MATTERS 1
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126
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127 /* Major revision number of the ARM Architecture implemented by the target. */
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128 extern unsigned aarch64_architecture_version;
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129
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130 /* Instruction tuning/selection flags. */
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131
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132 /* Bit values used to identify processor capabilities. */
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133 #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */
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134 #define AARCH64_FL_FP (1 << 1) /* Has FP. */
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135 #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */
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136 #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */
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137 /* ARMv8.1-A architecture extensions. */
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138 #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */
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139 #define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */
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140 #define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */
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141 /* ARMv8.2-A architecture extensions. */
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142 #define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */
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143 #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */
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144 /* ARMv8.3-A architecture extensions. */
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145 #define AARCH64_FL_V8_3 (1 << 10) /* Has ARMv8.3-A features. */
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146 #define AARCH64_FL_RCPC (1 << 11) /* Has support for RCpc model. */
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147 #define AARCH64_FL_DOTPROD (1 << 12) /* Has ARMv8.2-A Dot Product ins. */
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148
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149 /* Has FP and SIMD. */
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150 #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
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151
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152 /* Has FP without SIMD. */
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153 #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
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154
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155 /* Architecture flags that effect instruction selection. */
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156 #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD)
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157 #define AARCH64_FL_FOR_ARCH8_1 \
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158 (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \
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159 | AARCH64_FL_RDMA | AARCH64_FL_V8_1)
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160 #define AARCH64_FL_FOR_ARCH8_2 \
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161 (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
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162 #define AARCH64_FL_FOR_ARCH8_3 \
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163 (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
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164
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165 /* Macros to test ISA flags. */
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166
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167 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC)
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168 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO)
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169 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP)
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170 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD)
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171 #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE)
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172 #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA)
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173 #define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2)
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174 #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16)
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175 #define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3)
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176 #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD)
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177
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178 /* Crypto is an optional extension to AdvSIMD. */
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179 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
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180
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181 /* CRC instructions that can be enabled through +crc arch extension. */
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182 #define TARGET_CRC32 (AARCH64_ISA_CRC)
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183
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184 /* Atomic instructions that can be enabled through the +lse extension. */
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185 #define TARGET_LSE (AARCH64_ISA_LSE)
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186
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187 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */
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188 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
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189 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
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190
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191 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */
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192 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD)
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193
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194 /* ARMv8.3-A features. */
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195 #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3)
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196
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197 /* Make sure this is always defined so we don't have to check for ifdefs
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198 but rather use normal ifs. */
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199 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
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200 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
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201 #else
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202 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
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203 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
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204 #endif
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205
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206 /* Apply the workaround for Cortex-A53 erratum 835769. */
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207 #define TARGET_FIX_ERR_A53_835769 \
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208 ((aarch64_fix_a53_err835769 == 2) \
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209 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
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210
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211 /* Make sure this is always defined so we don't have to check for ifdefs
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212 but rather use normal ifs. */
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213 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
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214 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
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215 #else
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216 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
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217 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
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218 #endif
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219
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220 /* Apply the workaround for Cortex-A53 erratum 843419. */
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221 #define TARGET_FIX_ERR_A53_843419 \
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222 ((aarch64_fix_a53_err843419 == 2) \
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223 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
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224
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225 /* ARMv8.1-A Adv.SIMD support. */
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226 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
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227
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228 /* Standard register usage. */
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229
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230 /* 31 64-bit general purpose registers R0-R30:
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231 R30 LR (link register)
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232 R29 FP (frame pointer)
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233 R19-R28 Callee-saved registers
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234 R18 The platform register; use as temporary register.
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235 R17 IP1 The second intra-procedure-call temporary register
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236 (can be used by call veneers and PLT code); otherwise use
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237 as a temporary register
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238 R16 IP0 The first intra-procedure-call temporary register (can
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239 be used by call veneers and PLT code); otherwise use as a
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240 temporary register
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241 R9-R15 Temporary registers
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242 R8 Structure value parameter / temporary register
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243 R0-R7 Parameter/result registers
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244
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245 SP stack pointer, encoded as X/R31 where permitted.
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246 ZR zero register, encoded as X/R31 elsewhere
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247
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248 32 x 128-bit floating-point/vector registers
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249 V16-V31 Caller-saved (temporary) registers
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250 V8-V15 Callee-saved registers
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251 V0-V7 Parameter/result registers
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252
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253 The vector register V0 holds scalar B0, H0, S0 and D0 in its least
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254 significant bits. Unlike AArch32 S1 is not packed into D0,
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255 etc. */
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256
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257 /* Note that we don't mark X30 as a call-clobbered register. The idea is
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258 that it's really the call instructions themselves which clobber X30.
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259 We don't care what the called function does with it afterwards.
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260
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261 This approach makes it easier to implement sibcalls. Unlike normal
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262 calls, sibcalls don't clobber X30, so the register reaches the
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263 called function intact. EPILOGUE_USES says that X30 is useful
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264 to the called function. */
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265
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266 #define FIXED_REGISTERS \
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267 { \
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268 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \
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269 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \
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270 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \
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271 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \
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272 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \
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273 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \
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274 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \
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275 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \
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276 1, 1, 1, /* SFP, AP, CC */ \
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277 }
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278
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279 #define CALL_USED_REGISTERS \
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280 { \
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281 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \
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282 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \
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283 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \
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284 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \
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285 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \
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286 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \
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287 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \
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288 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \
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289 1, 1, 1, /* SFP, AP, CC */ \
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290 }
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291
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292 #define REGISTER_NAMES \
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293 { \
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294 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \
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295 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \
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296 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \
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297 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \
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298 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
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299 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
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300 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
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301 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
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302 "sfp", "ap", "cc", \
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303 }
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304
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305 /* Generate the register aliases for core register N */
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306 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
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307 {"w" # N, R0_REGNUM + (N)}
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308
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309 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
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310 {"d" # N, V0_REGNUM + (N)}, \
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311 {"s" # N, V0_REGNUM + (N)}, \
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312 {"h" # N, V0_REGNUM + (N)}, \
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313 {"b" # N, V0_REGNUM + (N)}
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314
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315 /* Provide aliases for all of the ISA defined register name forms.
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316 These aliases are convenient for use in the clobber lists of inline
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317 asm statements. */
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318
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319 #define ADDITIONAL_REGISTER_NAMES \
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320 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \
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321 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \
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322 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \
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323 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
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324 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
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325 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
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326 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
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327 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
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328 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \
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|
|
329 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \
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|
|
330 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \
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|
|
331 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
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|
|
332 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
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|
|
333 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
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|
|
334 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
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|
|
335 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \
|
|
|
336 }
|
|
|
337
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|
|
338 /* Say that the epilogue uses the return address register. Note that
|
|
|
339 in the case of sibcalls, the values "used by the epilogue" are
|
|
|
340 considered live at the start of the called function. */
|
|
|
341
|
|
|
342 #define EPILOGUE_USES(REGNO) \
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|
|
343 (epilogue_completed && (REGNO) == LR_REGNUM)
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|
|
344
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|
345 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
|
|
346 the stack pointer does not matter. This is only true if the function
|
|
|
347 uses alloca. */
|
|
|
348 #define EXIT_IGNORE_STACK (cfun->calls_alloca)
|
|
|
349
|
|
|
350 #define STATIC_CHAIN_REGNUM R18_REGNUM
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|
|
351 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM
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|
|
352 #define FRAME_POINTER_REGNUM SFP_REGNUM
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|
|
353 #define STACK_POINTER_REGNUM SP_REGNUM
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|
|
354 #define ARG_POINTER_REGNUM AP_REGNUM
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|
|
355 #define FIRST_PSEUDO_REGISTER 67
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|
|
356
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|
|
357 /* The number of (integer) argument register available. */
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|
|
358 #define NUM_ARG_REGS 8
|
|
|
359 #define NUM_FP_ARG_REGS 8
|
|
|
360
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|
|
361 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
|
|
|
362 four members. */
|
|
|
363 #define HA_MAX_NUM_FLDS 4
|
|
|
364
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|
|
365 /* External dwarf register number scheme. These number are used to
|
|
|
366 identify registers in dwarf debug information, the values are
|
|
|
367 defined by the AArch64 ABI. The numbering scheme is independent of
|
|
|
368 GCC's internal register numbering scheme. */
|
|
|
369
|
|
|
370 #define AARCH64_DWARF_R0 0
|
|
|
371
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|
|
372 /* The number of R registers, note 31! not 32. */
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|
|
373 #define AARCH64_DWARF_NUMBER_R 31
|
|
|
374
|
|
|
375 #define AARCH64_DWARF_SP 31
|
|
|
376 #define AARCH64_DWARF_V0 64
|
|
|
377
|
|
|
378 /* The number of V registers. */
|
|
|
379 #define AARCH64_DWARF_NUMBER_V 32
|
|
|
380
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|
|
381 /* For signal frames we need to use an alternative return column. This
|
|
|
382 value must not correspond to a hard register and must be out of the
|
|
|
383 range of DWARF_FRAME_REGNUM(). */
|
|
|
384 #define DWARF_ALT_FRAME_RETURN_COLUMN \
|
|
|
385 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
|
|
|
386
|
|
|
387 /* We add 1 extra frame register for use as the
|
|
|
388 DWARF_ALT_FRAME_RETURN_COLUMN. */
|
|
|
389 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
|
|
|
390
|
|
|
391
|
|
|
392 #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO)
|
|
|
393 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
|
|
|
394 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same
|
|
|
395 as the default definition in dwarf2out.c. */
|
|
|
396 #undef DWARF_FRAME_REGNUM
|
|
|
397 #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO)
|
|
|
398
|
|
|
399 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
|
|
|
400
|
|
|
401 #define DWARF2_UNWIND_INFO 1
|
|
|
402
|
|
|
403 /* Use R0 through R3 to pass exception handling information. */
|
|
|
404 #define EH_RETURN_DATA_REGNO(N) \
|
|
|
405 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
|
|
|
406
|
|
|
407 /* Select a format to encode pointers in exception handling data. */
|
|
|
408 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
|
|
|
409 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
|
|
|
410
|
|
|
411 /* Output the assembly strings we want to add to a function definition. */
|
|
|
412 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \
|
|
|
413 aarch64_declare_function_name (STR, NAME, DECL)
|
|
|
414
|
|
|
415 /* For EH returns X4 contains the stack adjustment. */
|
|
|
416 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM)
|
|
|
417 #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx ()
|
|
|
418
|
|
|
419 /* Don't use __builtin_setjmp until we've defined it. */
|
|
|
420 #undef DONT_USE_BUILTIN_SETJMP
|
|
|
421 #define DONT_USE_BUILTIN_SETJMP 1
|
|
|
422
|
|
|
423 /* Register in which the structure value is to be returned. */
|
|
|
424 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
|
|
|
425
|
|
|
426 /* Non-zero if REGNO is part of the Core register set.
|
|
|
427
|
|
|
428 The rather unusual way of expressing this check is to avoid
|
|
|
429 warnings when building the compiler when R0_REGNUM is 0 and REGNO
|
|
|
430 is unsigned. */
|
|
|
431 #define GP_REGNUM_P(REGNO) \
|
|
|
432 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
|
|
|
433
|
|
|
434 #define FP_REGNUM_P(REGNO) \
|
|
|
435 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
|
|
|
436
|
|
|
437 #define FP_LO_REGNUM_P(REGNO) \
|
|
|
438 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
|
|
|
439
|
|
|
440
|
|
|
441 /* Register and constant classes. */
|
|
|
442
|
|
|
443 enum reg_class
|
|
|
444 {
|
|
|
445 NO_REGS,
|
|
|
446 CALLER_SAVE_REGS,
|
|
|
447 GENERAL_REGS,
|
|
|
448 STACK_REG,
|
|
|
449 POINTER_REGS,
|
|
|
450 FP_LO_REGS,
|
|
|
451 FP_REGS,
|
|
|
452 POINTER_AND_FP_REGS,
|
|
|
453 ALL_REGS,
|
|
|
454 LIM_REG_CLASSES /* Last */
|
|
|
455 };
|
|
|
456
|
|
|
457 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
|
|
|
458
|
|
|
459 #define REG_CLASS_NAMES \
|
|
|
460 { \
|
|
|
461 "NO_REGS", \
|
|
|
462 "CALLER_SAVE_REGS", \
|
|
|
463 "GENERAL_REGS", \
|
|
|
464 "STACK_REG", \
|
|
|
465 "POINTER_REGS", \
|
|
|
466 "FP_LO_REGS", \
|
|
|
467 "FP_REGS", \
|
|
|
468 "POINTER_AND_FP_REGS", \
|
|
|
469 "ALL_REGS" \
|
|
|
470 }
|
|
|
471
|
|
|
472 #define REG_CLASS_CONTENTS \
|
|
|
473 { \
|
|
|
474 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
|
|
|
475 { 0x0007ffff, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
|
|
|
476 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \
|
|
|
477 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
|
|
|
478 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \
|
|
|
479 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \
|
|
|
480 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
|
|
|
481 { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\
|
|
|
482 { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \
|
|
|
483 }
|
|
|
484
|
|
|
485 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO)
|
|
|
486
|
|
|
487 #define INDEX_REG_CLASS GENERAL_REGS
|
|
|
488 #define BASE_REG_CLASS POINTER_REGS
|
|
|
489
|
|
|
490 /* Register pairs used to eliminate unneeded registers that point into
|
|
|
491 the stack frame. */
|
|
|
492 #define ELIMINABLE_REGS \
|
|
|
493 { \
|
|
|
494 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
|
|
495 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
|
|
|
496 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
|
|
497 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
|
|
|
498 }
|
|
|
499
|
|
|
500 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
|
|
501 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
|
|
|
502
|
|
|
503 /* CPU/ARCH option handling. */
|
|
|
504 #include "config/aarch64/aarch64-opts.h"
|
|
|
505
|
|
|
506 enum target_cpus
|
|
|
507 {
|
|
|
508 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
|
|
|
509 TARGET_CPU_##INTERNAL_IDENT,
|
|
|
510 #include "aarch64-cores.def"
|
|
|
511 TARGET_CPU_generic
|
|
|
512 };
|
|
|
513
|
|
|
514 /* If there is no CPU defined at configure, use generic as default. */
|
|
|
515 #ifndef TARGET_CPU_DEFAULT
|
|
|
516 #define TARGET_CPU_DEFAULT \
|
|
|
517 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
|
|
|
518 #endif
|
|
|
519
|
|
|
520 /* If inserting NOP before a mult-accumulate insn remember to adjust the
|
|
|
521 length so that conditional branching code is updated appropriately. */
|
|
|
522 #define ADJUST_INSN_LENGTH(insn, length) \
|
|
|
523 do \
|
|
|
524 { \
|
|
|
525 if (aarch64_madd_needs_nop (insn)) \
|
|
|
526 length += 4; \
|
|
|
527 } while (0)
|
|
|
528
|
|
|
529 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
|
|
|
530 aarch64_final_prescan_insn (INSN); \
|
|
|
531
|
|
|
532 /* The processor for which instructions should be scheduled. */
|
|
|
533 extern enum aarch64_processor aarch64_tune;
|
|
|
534
|
|
|
535 /* RTL generation support. */
|
|
|
536 #define INIT_EXPANDERS aarch64_init_expanders ()
|
|
|
537
|
|
|
538
|
|
|
539 /* Stack layout; function entry, exit and calling. */
|
|
|
540 #define STACK_GROWS_DOWNWARD 1
|
|
|
541
|
|
|
542 #define FRAME_GROWS_DOWNWARD 1
|
|
|
543
|
|
|
544 #define ACCUMULATE_OUTGOING_ARGS 1
|
|
|
545
|
|
|
546 #define FIRST_PARM_OFFSET(FNDECL) 0
|
|
|
547
|
|
|
548 /* Fix for VFP */
|
|
|
549 #define LIBCALL_VALUE(MODE) \
|
|
|
550 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
|
|
|
551
|
|
|
552 #define DEFAULT_PCC_STRUCT_RETURN 0
|
|
|
553
|
|
|
554 #ifdef HOST_WIDE_INT
|
|
|
555 struct GTY (()) aarch64_frame
|
|
|
556 {
|
|
|
557 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
|
|
|
558
|
|
|
559 /* The number of extra stack bytes taken up by register varargs.
|
|
|
560 This area is allocated by the callee at the very top of the
|
|
|
561 frame. This value is rounded up to a multiple of
|
|
|
562 STACK_BOUNDARY. */
|
|
|
563 HOST_WIDE_INT saved_varargs_size;
|
|
|
564
|
|
|
565 /* The size of the saved callee-save int/FP registers. */
|
|
|
566
|
|
|
567 HOST_WIDE_INT saved_regs_size;
|
|
|
568
|
|
|
569 /* Offset from the base of the frame (incomming SP) to the
|
|
|
570 top of the locals area. This value is always a multiple of
|
|
|
571 STACK_BOUNDARY. */
|
|
|
572 HOST_WIDE_INT locals_offset;
|
|
|
573
|
|
|
574 /* Offset from the base of the frame (incomming SP) to the
|
|
|
575 hard_frame_pointer. This value is always a multiple of
|
|
|
576 STACK_BOUNDARY. */
|
|
|
577 HOST_WIDE_INT hard_fp_offset;
|
|
|
578
|
|
|
579 /* The size of the frame. This value is the offset from base of the
|
|
|
580 * frame (incomming SP) to the stack_pointer. This value is always
|
|
|
581 * a multiple of STACK_BOUNDARY. */
|
|
|
582 HOST_WIDE_INT frame_size;
|
|
|
583
|
|
|
584 /* The size of the initial stack adjustment before saving callee-saves. */
|
|
|
585 HOST_WIDE_INT initial_adjust;
|
|
|
586
|
|
|
587 /* The writeback value when pushing callee-save registers.
|
|
|
588 It is zero when no push is used. */
|
|
|
589 HOST_WIDE_INT callee_adjust;
|
|
|
590
|
|
|
591 /* The offset from SP to the callee-save registers after initial_adjust.
|
|
|
592 It may be non-zero if no push is used (ie. callee_adjust == 0). */
|
|
|
593 HOST_WIDE_INT callee_offset;
|
|
|
594
|
|
|
595 /* The size of the stack adjustment after saving callee-saves. */
|
|
|
596 HOST_WIDE_INT final_adjust;
|
|
|
597
|
|
|
598 /* Store FP,LR and setup a frame pointer. */
|
|
|
599 bool emit_frame_chain;
|
|
|
600
|
|
|
601 unsigned wb_candidate1;
|
|
|
602 unsigned wb_candidate2;
|
|
|
603
|
|
|
604 bool laid_out;
|
|
|
605 };
|
|
|
606
|
|
|
607 typedef struct GTY (()) machine_function
|
|
|
608 {
|
|
|
609 struct aarch64_frame frame;
|
|
|
610 /* One entry for each hard register. */
|
|
|
611 bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
|
|
|
612 } machine_function;
|
|
|
613 #endif
|
|
|
614
|
|
|
615 /* Which ABI to use. */
|
|
|
616 enum aarch64_abi_type
|
|
|
617 {
|
|
|
618 AARCH64_ABI_LP64 = 0,
|
|
|
619 AARCH64_ABI_ILP32 = 1
|
|
|
620 };
|
|
|
621
|
|
|
622 #ifndef AARCH64_ABI_DEFAULT
|
|
|
623 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
|
|
|
624 #endif
|
|
|
625
|
|
|
626 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32)
|
|
|
627
|
|
|
628 enum arm_pcs
|
|
|
629 {
|
|
|
630 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */
|
|
|
631 ARM_PCS_UNKNOWN
|
|
|
632 };
|
|
|
633
|
|
|
634
|
|
|
635
|
|
|
636
|
|
|
637 /* We can't use machine_mode inside a generator file because it
|
|
|
638 hasn't been created yet; we shouldn't be using any code that
|
|
|
639 needs the real definition though, so this ought to be safe. */
|
|
|
640 #ifdef GENERATOR_FILE
|
|
|
641 #define MACHMODE int
|
|
|
642 #else
|
|
|
643 #include "insn-modes.h"
|
|
|
644 #define MACHMODE machine_mode
|
|
|
645 #endif
|
|
|
646
|
|
|
647 #ifndef USED_FOR_TARGET
|
|
|
648 /* AAPCS related state tracking. */
|
|
|
649 typedef struct
|
|
|
650 {
|
|
|
651 enum arm_pcs pcs_variant;
|
|
|
652 int aapcs_arg_processed; /* No need to lay out this argument again. */
|
|
|
653 int aapcs_ncrn; /* Next Core register number. */
|
|
|
654 int aapcs_nextncrn; /* Next next core register number. */
|
|
|
655 int aapcs_nvrn; /* Next Vector register number. */
|
|
|
656 int aapcs_nextnvrn; /* Next Next Vector register number. */
|
|
|
657 rtx aapcs_reg; /* Register assigned to this argument. This
|
|
|
658 is NULL_RTX if this parameter goes on
|
|
|
659 the stack. */
|
|
|
660 MACHMODE aapcs_vfp_rmode;
|
|
|
661 int aapcs_stack_words; /* If the argument is passed on the stack, this
|
|
|
662 is the number of words needed, after rounding
|
|
|
663 up. Only meaningful when
|
|
|
664 aapcs_reg == NULL_RTX. */
|
|
|
665 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the
|
|
|
666 stack arg area so far. */
|
|
|
667 } CUMULATIVE_ARGS;
|
|
|
668 #endif
|
|
|
669
|
|
|
670 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
|
|
|
671 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
|
|
|
672
|
|
|
673 #define PAD_VARARGS_DOWN 0
|
|
|
674
|
|
|
675 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
|
|
|
676 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
|
|
|
677
|
|
|
678 #define FUNCTION_ARG_REGNO_P(REGNO) \
|
|
|
679 aarch64_function_arg_regno_p(REGNO)
|
|
|
680
|
|
|
681
|
|
|
682 /* ISA Features. */
|
|
|
683
|
|
|
684 /* Addressing modes, etc. */
|
|
|
685 #define HAVE_POST_INCREMENT 1
|
|
|
686 #define HAVE_PRE_INCREMENT 1
|
|
|
687 #define HAVE_POST_DECREMENT 1
|
|
|
688 #define HAVE_PRE_DECREMENT 1
|
|
|
689 #define HAVE_POST_MODIFY_DISP 1
|
|
|
690 #define HAVE_PRE_MODIFY_DISP 1
|
|
|
691
|
|
|
692 #define MAX_REGS_PER_ADDRESS 2
|
|
|
693
|
|
|
694 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X)
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|
695
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|
696 #define REGNO_OK_FOR_BASE_P(REGNO) \
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|
|
697 aarch64_regno_ok_for_base_p (REGNO, true)
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|
698
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|
|
699 #define REGNO_OK_FOR_INDEX_P(REGNO) \
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|
|
700 aarch64_regno_ok_for_index_p (REGNO, true)
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|
|
701
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|
|
702 #define LEGITIMATE_PIC_OPERAND_P(X) \
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|
|
703 aarch64_legitimate_pic_operand_p (X)
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|
704
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|
705 #define CASE_VECTOR_MODE Pmode
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706
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|
707 #define DEFAULT_SIGNED_CHAR 0
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|
|
708
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|
709 /* An integer expression for the size in bits of the largest integer machine
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|
|
710 mode that should actually be used. We allow pairs of registers. */
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|
|
711 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
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|
|
712
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|
|
713 /* Maximum bytes moved by a single instruction (load/store pair). */
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|
|
714 #define MOVE_MAX (UNITS_PER_WORD * 2)
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|
|
715
|
|
|
716 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */
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|
|
717 #define AARCH64_CALL_RATIO 8
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|
|
718
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|
|
719 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
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|
|
720 move_by_pieces will continually copy the largest safe chunks. So a
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|
|
721 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient
|
|
|
722 for both size and speed of copy, so we will instead use the "movmem"
|
|
|
723 standard name to implement the copy. This logic does not apply when
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|
|
724 targeting -mstrict-align, so keep a sensible default in that case. */
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|
|
725 #define MOVE_RATIO(speed) \
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|
|
726 (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
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|
|
727
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|
|
728 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
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|
|
729 of the length of a memset call, but use the default otherwise. */
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|
|
730 #define CLEAR_RATIO(speed) \
|
|
|
731 ((speed) ? 15 : AARCH64_CALL_RATIO)
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|
|
732
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|
|
733 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
|
|
|
734 optimizing for size adjust the ratio to account for the overhead of loading
|
|
|
735 the constant. */
|
|
|
736 #define SET_RATIO(speed) \
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|
|
737 ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
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|
|
738
|
|
|
739 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is
|
|
|
740 rarely a good idea in straight-line code since it adds an extra address
|
|
|
741 dependency between each instruction. Better to use incrementing offsets. */
|
|
|
742 #define USE_LOAD_POST_INCREMENT(MODE) 0
|
|
|
743 #define USE_LOAD_POST_DECREMENT(MODE) 0
|
|
|
744 #define USE_LOAD_PRE_INCREMENT(MODE) 0
|
|
|
745 #define USE_LOAD_PRE_DECREMENT(MODE) 0
|
|
|
746 #define USE_STORE_POST_INCREMENT(MODE) 0
|
|
|
747 #define USE_STORE_POST_DECREMENT(MODE) 0
|
|
|
748 #define USE_STORE_PRE_INCREMENT(MODE) 0
|
|
|
749 #define USE_STORE_PRE_DECREMENT(MODE) 0
|
|
|
750
|
|
|
751 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
|
|
|
752 The assigned word_mode is DImode but operations narrower than SImode
|
|
|
753 behave as 32-bit operations if using the W-form of the registers rather
|
|
|
754 than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
|
|
|
755 expects. */
|
|
|
756 #define WORD_REGISTER_OPERATIONS 0
|
|
|
757
|
|
|
758 /* Define if loading from memory in MODE, an integral mode narrower than
|
|
|
759 BITS_PER_WORD will either zero-extend or sign-extend. The value of this
|
|
|
760 macro should be the code that says which one of the two operations is
|
|
|
761 implicitly done, or UNKNOWN if none. */
|
|
|
762 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
|
|
|
763
|
|
|
764 /* Define this macro to be non-zero if instructions will fail to work
|
|
|
765 if given data not on the nominal alignment. */
|
|
|
766 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
|
|
|
767
|
|
|
768 /* Define this macro to be non-zero if accessing less than a word of
|
|
|
769 memory is no faster than accessing a word of memory, i.e., if such
|
|
|
770 accesses require more than one instruction or if there is no
|
|
|
771 difference in cost.
|
|
|
772 Although there's no difference in instruction count or cycles,
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|
|
773 in AArch64 we don't want to expand to a sub-word to a 64-bit access
|
|
|
774 if we don't have to, for power-saving reasons. */
|
|
|
775 #define SLOW_BYTE_ACCESS 0
|
|
|
776
|
|
|
777 #define NO_FUNCTION_CSE 1
|
|
|
778
|
|
|
779 /* Specify the machine mode that the hardware addresses have.
|
|
|
780 After generation of rtl, the compiler makes no further distinction
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|
|
781 between pointers and any other objects of this machine mode. */
|
|
|
782 #define Pmode DImode
|
|
|
783
|
|
|
784 /* A C expression whose value is zero if pointers that need to be extended
|
|
|
785 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
|
|
|
786 greater then zero if they are zero-extended and less then zero if the
|
|
|
787 ptr_extend instruction should be used. */
|
|
|
788 #define POINTERS_EXTEND_UNSIGNED 1
|
|
|
789
|
|
|
790 /* Mode of a function address in a call instruction (for indexing purposes). */
|
|
|
791 #define FUNCTION_MODE Pmode
|
|
|
792
|
|
|
793 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y)
|
|
|
794
|
|
|
795 #define REVERSIBLE_CC_MODE(MODE) 1
|
|
|
796
|
|
|
797 #define REVERSE_CONDITION(CODE, MODE) \
|
|
|
798 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
|
|
|
799 ? reverse_condition_maybe_unordered (CODE) \
|
|
|
800 : reverse_condition (CODE))
|
|
|
801
|
|
|
802 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
|
|
|
803 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
|
|
|
804 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
|
|
|
805 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
|
|
|
806
|
|
|
807 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
|
|
|
808
|
|
|
809 #define RETURN_ADDR_RTX aarch64_return_addr
|
|
|
810
|
|
|
811 /* 3 insns + padding + 2 pointer-sized entries. */
|
|
|
812 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
|
|
|
813
|
|
|
814 /* Trampolines contain dwords, so must be dword aligned. */
|
|
|
815 #define TRAMPOLINE_ALIGNMENT 64
|
|
|
816
|
|
|
817 /* Put trampolines in the text section so that mapping symbols work
|
|
|
818 correctly. */
|
|
|
819 #define TRAMPOLINE_SECTION text_section
|
|
|
820
|
|
|
821 /* To start with. */
|
|
|
822 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
|
|
|
823 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
|
|
|
824
|
|
|
825
|
|
|
826 /* Assembly output. */
|
|
|
827
|
|
|
828 /* For now we'll make all jump tables pc-relative. */
|
|
|
829 #define CASE_VECTOR_PC_RELATIVE 1
|
|
|
830
|
|
|
831 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
|
|
|
832 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \
|
|
|
833 : (min < -0x1f0 || max > 0x1f0) ? HImode \
|
|
|
834 : QImode)
|
|
|
835
|
|
|
836 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
|
|
|
837 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
|
|
|
838
|
|
|
839 #define MCOUNT_NAME "_mcount"
|
|
|
840
|
|
|
841 #define NO_PROFILE_COUNTERS 1
|
|
|
842
|
|
|
843 /* Emit rtl for profiling. Output assembler code to FILE
|
|
|
844 to call "_mcount" for profiling a function entry. */
|
|
|
845 #define PROFILE_HOOK(LABEL) \
|
|
|
846 { \
|
|
|
847 rtx fun, lr; \
|
|
|
848 lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \
|
|
|
849 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
|
|
|
850 emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \
|
|
|
851 }
|
|
|
852
|
|
|
853 /* All the work done in PROFILE_HOOK, but still required. */
|
|
|
854 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
|
|
|
855
|
|
|
856 /* For some reason, the Linux headers think they know how to define
|
|
|
857 these macros. They don't!!! */
|
|
|
858 #undef ASM_APP_ON
|
|
|
859 #undef ASM_APP_OFF
|
|
|
860 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n"
|
|
|
861 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n"
|
|
|
862
|
|
|
863 #define CONSTANT_POOL_BEFORE_FUNCTION 0
|
|
|
864
|
|
|
865 /* This definition should be relocated to aarch64-elf-raw.h. This macro
|
|
|
866 should be undefined in aarch64-linux.h and a clear_cache pattern
|
|
|
867 implmented to emit either the call to __aarch64_sync_cache_range()
|
|
|
868 directly or preferably the appropriate sycall or cache clear
|
|
|
869 instructions inline. */
|
|
|
870 #define CLEAR_INSN_CACHE(beg, end) \
|
|
|
871 extern void __aarch64_sync_cache_range (void *, void *); \
|
|
|
872 __aarch64_sync_cache_range (beg, end)
|
|
|
873
|
|
|
874 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
|
|
|
875
|
|
|
876 /* Choose appropriate mode for caller saves, so we do the minimum
|
|
|
877 required size of load/store. */
|
|
|
878 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
|
|
|
879 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
|
|
|
880
|
|
|
881 #undef SWITCHABLE_TARGET
|
|
|
882 #define SWITCHABLE_TARGET 1
|
|
|
883
|
|
|
884 /* Check TLS Descriptors mechanism is selected. */
|
|
|
885 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
|
|
|
886
|
|
|
887 extern enum aarch64_code_model aarch64_cmodel;
|
|
|
888
|
|
|
889 /* When using the tiny addressing model conditional and unconditional branches
|
|
|
890 can span the whole of the available address space (1MB). */
|
|
|
891 #define HAS_LONG_COND_BRANCH \
|
|
|
892 (aarch64_cmodel == AARCH64_CMODEL_TINY \
|
|
|
893 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
|
|
|
894
|
|
|
895 #define HAS_LONG_UNCOND_BRANCH \
|
|
|
896 (aarch64_cmodel == AARCH64_CMODEL_TINY \
|
|
|
897 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
|
|
|
898
|
|
|
899 #define TARGET_SUPPORTS_WIDE_INT 1
|
|
|
900
|
|
|
901 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */
|
|
|
902 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
|
|
|
903 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
|
|
|
904 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
|
|
|
905 || (MODE) == DFmode)
|
|
|
906
|
|
|
907 /* Modes valid for AdvSIMD Q registers. */
|
|
|
908 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
|
|
|
909 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
|
|
|
910 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
|
|
|
911 || (MODE) == V2DFmode)
|
|
|
912
|
|
|
913 #define ENDIAN_LANE_N(mode, n) \
|
|
|
914 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
|
|
|
915
|
|
|
916 /* Support for a configure-time default CPU, etc. We currently support
|
|
|
917 --with-arch and --with-cpu. Both are ignored if either is specified
|
|
|
918 explicitly on the command line at run time. */
|
|
|
919 #define OPTION_DEFAULT_SPECS \
|
|
|
920 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
|
|
|
921 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },
|
|
|
922
|
|
|
923 #define MCPU_TO_MARCH_SPEC \
|
|
|
924 " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
|
|
|
925
|
|
|
926 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
|
|
|
927 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
|
|
|
928 { "rewrite_mcpu", aarch64_rewrite_mcpu },
|
|
|
929
|
|
|
930 #if defined(__aarch64__)
|
|
|
931 extern const char *host_detect_local_cpu (int argc, const char **argv);
|
|
|
932 # define EXTRA_SPEC_FUNCTIONS \
|
|
|
933 { "local_cpu_detect", host_detect_local_cpu }, \
|
|
|
934 MCPU_TO_MARCH_SPEC_FUNCTIONS
|
|
|
935
|
|
|
936 # define MCPU_MTUNE_NATIVE_SPECS \
|
|
|
937 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
|
|
|
938 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
|
|
|
939 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
|
|
|
940 #else
|
|
|
941 # define MCPU_MTUNE_NATIVE_SPECS ""
|
|
|
942 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
|
|
|
943 #endif
|
|
|
944
|
|
|
945 #define ASM_CPU_SPEC \
|
|
|
946 MCPU_TO_MARCH_SPEC
|
|
|
947
|
|
|
948 #define EXTRA_SPECS \
|
|
|
949 { "asm_cpu_spec", ASM_CPU_SPEC }
|
|
|
950
|
|
|
951 #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue
|
|
|
952
|
|
|
953 /* This type is the user-visible __fp16, and a pointer to that type. We
|
|
|
954 need it in many places in the backend. Defined in aarch64-builtins.c. */
|
|
|
955 extern tree aarch64_fp16_type_node;
|
|
|
956 extern tree aarch64_fp16_ptr_type_node;
|
|
|
957
|
|
|
958 /* The generic unwind code in libgcc does not initialize the frame pointer.
|
|
|
959 So in order to unwind a function using a frame pointer, the very first
|
|
|
960 function that is unwound must save the frame pointer. That way the frame
|
|
|
961 pointer is restored and its value is now valid - otherwise _Unwind_GetGR
|
|
|
962 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */
|
|
|
963 #define LIBGCC2_UNWIND_ATTRIBUTE \
|
|
|
964 __attribute__((optimize ("no-omit-frame-pointer")))
|
|
|
965
|
|
|
966 #endif /* GCC_AARCH64_H */
|
