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1 ;; Machine description for AArch64 architecture.
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2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
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3 ;; Contributed by ARM Ltd.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_special_predicate "cc_register"
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22 (and (match_code "reg")
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23 (and (match_test "REGNO (op) == CC_REGNUM")
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24 (ior (match_test "mode == GET_MODE (op)")
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25 (match_test "mode == VOIDmode
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26 && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
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27 )
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28
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29 (define_predicate "aarch64_call_insn_operand"
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30 (ior (match_code "symbol_ref")
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31 (match_operand 0 "register_operand")))
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32
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33 ;; Return true if OP a (const_int 0) operand.
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34 (define_predicate "const0_operand"
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35 (and (match_code "const_int")
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36 (match_test "op == CONST0_RTX (mode)")))
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37
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38 (define_special_predicate "subreg_lowpart_operator"
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39 (and (match_code "subreg")
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40 (match_test "subreg_lowpart_p (op)")))
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41
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42 (define_predicate "aarch64_ccmp_immediate"
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43 (and (match_code "const_int")
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44 (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
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45
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46 (define_predicate "aarch64_ccmp_operand"
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47 (ior (match_operand 0 "register_operand")
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48 (match_operand 0 "aarch64_ccmp_immediate")))
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49
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50 (define_predicate "aarch64_simd_register"
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51 (and (match_code "reg")
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52 (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
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53 (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
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54
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55 (define_predicate "aarch64_reg_or_zero"
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56 (and (match_code "reg,subreg,const_int")
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57 (ior (match_operand 0 "register_operand")
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58 (match_test "op == const0_rtx"))))
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59
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60 (define_predicate "aarch64_reg_or_fp_zero"
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61 (ior (match_operand 0 "register_operand")
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62 (and (match_code "const_double")
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63 (match_test "aarch64_float_const_zero_rtx_p (op)"))))
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64
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65 (define_predicate "aarch64_reg_zero_or_m1_or_1"
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66 (and (match_code "reg,subreg,const_int")
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67 (ior (match_operand 0 "register_operand")
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68 (ior (match_test "op == const0_rtx")
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69 (ior (match_test "op == constm1_rtx")
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70 (match_test "op == const1_rtx"))))))
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71
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72 (define_predicate "aarch64_reg_or_orr_imm"
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73 (ior (match_operand 0 "register_operand")
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74 (and (match_code "const_vector")
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75 (match_test "aarch64_simd_valid_immediate (op, mode, false,
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76 NULL, AARCH64_CHECK_ORR)"))))
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77
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78 (define_predicate "aarch64_reg_or_bic_imm"
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79 (ior (match_operand 0 "register_operand")
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80 (and (match_code "const_vector")
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81 (match_test "aarch64_simd_valid_immediate (op, mode, false,
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82 NULL, AARCH64_CHECK_BIC)"))))
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83
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84 (define_predicate "aarch64_fp_compare_operand"
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85 (ior (match_operand 0 "register_operand")
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86 (and (match_code "const_double")
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87 (match_test "aarch64_float_const_zero_rtx_p (op)"))))
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88
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89 (define_predicate "aarch64_fp_pow2"
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90 (and (match_code "const_double")
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91 (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
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92
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93 (define_predicate "aarch64_fp_vec_pow2"
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94 (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
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95
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96 (define_predicate "aarch64_sub_immediate"
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97 (and (match_code "const_int")
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98 (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
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99
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100 (define_predicate "aarch64_plus_immediate"
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101 (and (match_code "const_int")
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102 (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
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103 (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
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104
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105 (define_predicate "aarch64_plus_operand"
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106 (ior (match_operand 0 "register_operand")
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107 (match_operand 0 "aarch64_plus_immediate")))
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108
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109 (define_predicate "aarch64_pluslong_immediate"
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110 (and (match_code "const_int")
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111 (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
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112
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113 (define_predicate "aarch64_pluslong_strict_immedate"
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114 (and (match_operand 0 "aarch64_pluslong_immediate")
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115 (not (match_operand 0 "aarch64_plus_immediate"))))
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116
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117 (define_predicate "aarch64_pluslong_operand"
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118 (ior (match_operand 0 "register_operand")
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119 (match_operand 0 "aarch64_pluslong_immediate")))
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120
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121 (define_predicate "aarch64_logical_immediate"
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122 (and (match_code "const_int")
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123 (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
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124
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125 (define_predicate "aarch64_logical_operand"
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126 (ior (match_operand 0 "register_operand")
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127 (match_operand 0 "aarch64_logical_immediate")))
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128
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129 (define_predicate "aarch64_mov_imm_operand"
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130 (and (match_code "const_int")
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131 (match_test "aarch64_move_imm (INTVAL (op), mode)")))
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132
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133 (define_predicate "aarch64_logical_and_immediate"
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134 (and (match_code "const_int")
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135 (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
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136
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137 (define_predicate "aarch64_shift_imm_si"
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138 (and (match_code "const_int")
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139 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
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140
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141 (define_predicate "aarch64_shift_imm_di"
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142 (and (match_code "const_int")
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143 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
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144
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145 (define_predicate "aarch64_shift_imm64_di"
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146 (and (match_code "const_int")
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147 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
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148
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149 (define_predicate "aarch64_reg_or_shift_imm_si"
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150 (ior (match_operand 0 "register_operand")
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151 (match_operand 0 "aarch64_shift_imm_si")))
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152
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153 (define_predicate "aarch64_reg_or_shift_imm_di"
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154 (ior (match_operand 0 "register_operand")
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155 (match_operand 0 "aarch64_shift_imm_di")))
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156
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157 ;; The imm3 field is a 3-bit field that only accepts immediates in the
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158 ;; range 0..4.
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159 (define_predicate "aarch64_imm3"
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160 (and (match_code "const_int")
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161 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
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162
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163 ;; An immediate that fits into 24 bits.
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164 (define_predicate "aarch64_imm24"
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165 (and (match_code "const_int")
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166 (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
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167
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168 (define_predicate "aarch64_pwr_imm3"
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169 (and (match_code "const_int")
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170 (match_test "INTVAL (op) != 0
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171 && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
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172
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173 (define_predicate "aarch64_pwr_2_si"
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174 (and (match_code "const_int")
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175 (match_test "INTVAL (op) != 0
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176 && (unsigned) exact_log2 (INTVAL (op)) < 32")))
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177
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178 (define_predicate "aarch64_pwr_2_di"
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179 (and (match_code "const_int")
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180 (match_test "INTVAL (op) != 0
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181 && (unsigned) exact_log2 (INTVAL (op)) < 64")))
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182
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183 (define_predicate "aarch64_mem_pair_offset"
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184 (and (match_code "const_int")
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185 (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
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186
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187 (define_predicate "aarch64_mem_pair_operand"
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188 (and (match_code "mem")
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189 (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
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190 0)")))
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191
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192 (define_predicate "aarch64_prefetch_operand"
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193 (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
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194
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195 (define_predicate "aarch64_valid_symref"
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196 (match_code "const, symbol_ref, label_ref")
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197 {
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198 return (aarch64_classify_symbolic_expression (op)
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199 != SYMBOL_FORCE_TO_MEM);
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200 })
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201
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202 (define_predicate "aarch64_tls_ie_symref"
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203 (match_code "const, symbol_ref, label_ref")
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204 {
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205 switch (GET_CODE (op))
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206 {
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207 case CONST:
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208 op = XEXP (op, 0);
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209 if (GET_CODE (op) != PLUS
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210 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
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211 || GET_CODE (XEXP (op, 1)) != CONST_INT)
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212 return false;
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213 op = XEXP (op, 0);
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214 /* FALLTHRU */
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215
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216 case SYMBOL_REF:
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217 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
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218
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219 default:
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220 gcc_unreachable ();
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221 }
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222 })
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223
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224 (define_predicate "aarch64_tls_le_symref"
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225 (match_code "const, symbol_ref, label_ref")
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226 {
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227 switch (GET_CODE (op))
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228 {
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229 case CONST:
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230 op = XEXP (op, 0);
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231 if (GET_CODE (op) != PLUS
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232 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
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233 || GET_CODE (XEXP (op, 1)) != CONST_INT)
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234 return false;
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235 op = XEXP (op, 0);
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236 /* FALLTHRU */
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237
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238 case SYMBOL_REF:
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239 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
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240
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241 default:
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242 gcc_unreachable ();
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243 }
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244 })
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245
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246 (define_predicate "aarch64_mov_operand"
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247 (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high")
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248 (ior (match_operand 0 "register_operand")
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249 (ior (match_operand 0 "memory_operand")
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250 (match_test "aarch64_mov_operand_p (op, mode)")))))
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251
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252 (define_predicate "aarch64_movti_operand"
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253 (and (match_code "reg,subreg,mem,const_int")
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254 (ior (match_operand 0 "register_operand")
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255 (ior (match_operand 0 "memory_operand")
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256 (match_operand 0 "const_int_operand")))))
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257
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258 (define_predicate "aarch64_reg_or_imm"
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259 (and (match_code "reg,subreg,const_int")
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260 (ior (match_operand 0 "register_operand")
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261 (match_operand 0 "const_int_operand"))))
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262
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263 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
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264 (define_special_predicate "aarch64_comparison_operator"
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265 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
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266 ordered,unlt,unle,unge,ungt"))
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267
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268 ;; Same as aarch64_comparison_operator but don't ignore the mode.
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269 ;; RTL SET operations require their operands source and destination have
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270 ;; the same modes, so we can't ignore the modes there. See PR target/69161.
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271 (define_predicate "aarch64_comparison_operator_mode"
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272 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
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273 ordered,unlt,unle,unge,ungt"))
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274
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275 (define_special_predicate "aarch64_comparison_operation"
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276 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
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277 ordered,unlt,unle,unge,ungt")
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278 {
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279 if (XEXP (op, 1) != const0_rtx)
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280 return false;
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281 rtx op0 = XEXP (op, 0);
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282 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
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283 return false;
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284 return aarch64_get_condition_code (op) >= 0;
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285 })
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286
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287 (define_special_predicate "aarch64_carry_operation"
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288 (match_code "ne,geu")
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289 {
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290 if (XEXP (op, 1) != const0_rtx)
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291 return false;
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292 machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
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293 rtx op0 = XEXP (op, 0);
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294 return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
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295 })
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296
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297 (define_special_predicate "aarch64_borrow_operation"
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298 (match_code "eq,ltu")
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299 {
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300 if (XEXP (op, 1) != const0_rtx)
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301 return false;
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302 machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
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303 rtx op0 = XEXP (op, 0);
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304 return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
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305 })
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306
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307 ;; True if the operand is memory reference suitable for a load/store exclusive.
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308 (define_predicate "aarch64_sync_memory_operand"
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309 (and (match_operand 0 "memory_operand")
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310 (match_code "reg" "0")))
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311
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312 ;; Predicates for parallel expanders based on mode.
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313 (define_special_predicate "vect_par_cnst_hi_half"
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314 (match_code "parallel")
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315 {
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316 return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
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317 })
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318
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319 (define_special_predicate "vect_par_cnst_lo_half"
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320 (match_code "parallel")
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321 {
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322 return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
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323 })
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324
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325 (define_special_predicate "aarch64_simd_lshift_imm"
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326 (match_code "const_vector")
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327 {
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328 return aarch64_simd_shift_imm_p (op, mode, true);
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329 })
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330
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331 (define_special_predicate "aarch64_simd_rshift_imm"
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332 (match_code "const_vector")
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333 {
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334 return aarch64_simd_shift_imm_p (op, mode, false);
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335 })
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336
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337 (define_predicate "aarch64_simd_reg_or_zero"
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338 (and (match_code "reg,subreg,const_int,const_double,const_vector")
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339 (ior (match_operand 0 "register_operand")
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340 (ior (match_test "op == const0_rtx")
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341 (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
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342
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343 (define_predicate "aarch64_simd_struct_operand"
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344 (and (match_code "mem")
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345 (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
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346
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347 ;; Like general_operand but allow only valid SIMD addressing modes.
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348 (define_predicate "aarch64_simd_general_operand"
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349 (and (match_operand 0 "general_operand")
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350 (match_test "!MEM_P (op)
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351 || GET_CODE (XEXP (op, 0)) == POST_INC
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352 || GET_CODE (XEXP (op, 0)) == REG")))
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353
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354 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
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355 (define_predicate "aarch64_simd_nonimmediate_operand"
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356 (and (match_operand 0 "nonimmediate_operand")
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357 (match_test "!MEM_P (op)
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358 || GET_CODE (XEXP (op, 0)) == POST_INC
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359 || GET_CODE (XEXP (op, 0)) == REG")))
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360
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361 (define_special_predicate "aarch64_simd_imm_zero"
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362 (match_code "const_vector")
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363 {
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364 return aarch64_simd_imm_zero_p (op, mode);
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365 })
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366
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367 (define_special_predicate "aarch64_simd_imm_minus_one"
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368 (match_code "const_vector")
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369 {
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370 return aarch64_const_vec_all_same_int_p (op, -1);
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371 })
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372
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373 ;; Predicates used by the various SIMD shift operations. These
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374 ;; fall in to 3 categories.
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375 ;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
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376 ;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
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377 ;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
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378 (define_predicate "aarch64_simd_shift_imm_qi"
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379 (and (match_code "const_int")
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380 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
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381
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382 (define_predicate "aarch64_simd_shift_imm_hi"
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383 (and (match_code "const_int")
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384 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
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385
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386 (define_predicate "aarch64_simd_shift_imm_si"
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387 (and (match_code "const_int")
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388 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
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389
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390 (define_predicate "aarch64_simd_shift_imm_di"
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391 (and (match_code "const_int")
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392 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
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393
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394 (define_predicate "aarch64_simd_shift_imm_offset_qi"
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395 (and (match_code "const_int")
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396 (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
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397
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398 (define_predicate "aarch64_simd_shift_imm_offset_hi"
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399 (and (match_code "const_int")
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400 (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
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401
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402 (define_predicate "aarch64_simd_shift_imm_offset_si"
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403 (and (match_code "const_int")
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404 (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
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405
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406 (define_predicate "aarch64_simd_shift_imm_offset_di"
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407 (and (match_code "const_int")
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408 (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
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409
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410 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
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411 (and (match_code "const_int")
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412 (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
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413
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414 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
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415 (and (match_code "const_int")
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416 (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
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417
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418 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
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419 (and (match_code "const_int")
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420 (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
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421
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422 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
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423 (and (match_code "const_int")
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424 (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
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425
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426 (define_predicate "aarch64_constant_pool_symref"
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427 (and (match_code "symbol_ref")
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428 (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
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