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1 ;; Cavium ThunderX pipeline description
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2 ;; Copyright (C) 2014-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; Written by Andrew Pinski <apinski@cavium.com>
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify
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9 ;; it under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful,
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14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 ;; GNU General Public License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22
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23 ;; Thunder is a dual-issue processor that can issue all instructions on
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24 ;; pipe0 and a subset on pipe1.
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25
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26
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27 (define_automaton "thunderx_main, thunderx_mult, thunderx_divide, thunderx_simd")
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28
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29 (define_cpu_unit "thunderx_pipe0" "thunderx_main")
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30 (define_cpu_unit "thunderx_pipe1" "thunderx_main")
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31 (define_cpu_unit "thunderx_mult" "thunderx_mult")
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32 (define_cpu_unit "thunderx_divide" "thunderx_divide")
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33 (define_cpu_unit "thunderx_simd" "thunderx_simd")
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34
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35 (define_insn_reservation "thunderx_add" 1
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36 (and (eq_attr "tune" "thunderx")
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37 (eq_attr "type" "adc_imm,adc_reg,adr,alu_imm,alu_sreg,alus_imm,alus_sreg,extend,logic_imm,logic_reg,logics_imm,logics_reg,mov_imm,mov_reg"))
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38 "thunderx_pipe0 | thunderx_pipe1")
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39
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40 (define_insn_reservation "thunderx_shift" 1
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41 (and (eq_attr "tune" "thunderx")
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42 (eq_attr "type" "bfm,bfx,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
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43 "thunderx_pipe0 | thunderx_pipe1")
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44
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45
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46 ;; Arthimentic instructions with an extra shift or extend is two cycles.
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47 ;; FIXME: This needs more attributes on aarch64 than what is currently there;
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48 ;; this is conserative for now.
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49 ;; Except this is not correct as this is only for !(LSL && shift by 0/1/2/3)
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50 ;; Except this is not correct as this is only for !(zero extend)
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51
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52 (define_insn_reservation "thunderx_arith_shift" 2
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53 (and (eq_attr "tune" "thunderx")
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54 (eq_attr "type" "alu_ext,alu_shift_imm,alu_shift_reg,alus_ext,logic_shift_imm,logic_shift_reg,logics_shift_imm,logics_shift_reg,alus_shift_imm"))
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55 "thunderx_pipe0 | thunderx_pipe1")
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56
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57 (define_insn_reservation "thunderx_csel" 2
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58 (and (eq_attr "tune" "thunderx")
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59 (eq_attr "type" "csel"))
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60 "thunderx_pipe0 | thunderx_pipe1")
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61
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62 ;; Multiply and mulitply accumulate and count leading zeros can only happen on pipe 1
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63
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64 (define_insn_reservation "thunderx_mul" 4
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65 (and (eq_attr "tune" "thunderx")
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66 (eq_attr "type" "mul,muls,mla,mlas,clz,smull,umull,smlal,umlal"))
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67 "thunderx_pipe1 + thunderx_mult")
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68
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69 ;; crcb,crch,crcw is 4 cycles and can only happen on pipe 1
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70
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71 (define_insn_reservation "thunderx_crc32" 4
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72 (and (eq_attr "tune" "thunderx")
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73 (eq_attr "type" "crc"))
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74 "thunderx_pipe1 + thunderx_mult")
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75
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76 ;; crcx is 5 cycles and only happen on pipe 1
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77 ;(define_insn_reservation "thunderx_crc64" 5
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78 ; (and (eq_attr "tune" "thunderx")
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79 ; (eq_attr "type" "crc")
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80 ; (eq_attr "mode" "DI"))
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81 ; "thunderx_pipe1 + thunderx_mult")
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82
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83 (define_insn_reservation "thunderx_div32" 22
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84 (and (eq_attr "tune" "thunderx")
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85 (eq_attr "type" "udiv,sdiv"))
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86 "thunderx_pipe1 + thunderx_divide, thunderx_divide * 21")
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87
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88 ;(define_insn_reservation "thunderx_div64" 38
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89 ; (and (eq_attr "tune" "thunderx")
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90 ; (eq_attr "type" "udiv,sdiv")
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91 ; (eq_attr "mode" "DI"))
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92 ; "thunderx_pipe1 + thunderx_divide, thunderx_divide * 34")
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93
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94 ;; Stores take one cycle in pipe 0
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95 (define_insn_reservation "thunderx_store" 1
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96 (and (eq_attr "tune" "thunderx")
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97 (eq_attr "type" "store_4"))
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98 "thunderx_pipe0")
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99
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100 ;; Store pair are single issued
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101 (define_insn_reservation "thunderx_storepair" 1
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102 (and (eq_attr "tune" "thunderx")
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103 (eq_attr "type" "store_8,store_16"))
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104 "thunderx_pipe0 + thunderx_pipe1")
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105
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106 ;; Prefetch are single issued
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107 ;(define_insn_reservation "thunderx_prefetch" 1
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108 ; (and (eq_attr "tune" "thunderx")
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109 ; (eq_attr "type" "prefetch"))
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110 ; "thunderx_pipe0 + thunderx_pipe1")
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111
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112 ;; loads (and load pairs) from L1 take 3 cycles in pipe 0
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113 (define_insn_reservation "thunderx_load" 3
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114 (and (eq_attr "tune" "thunderx")
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115 (eq_attr "type" "load_4, load_8, load_16"))
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116 "thunderx_pipe0")
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117
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118 (define_insn_reservation "thunderx_brj" 1
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119 (and (eq_attr "tune" "thunderx")
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120 (eq_attr "type" "branch,trap,call"))
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121 "thunderx_pipe1")
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122
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123 ;; FPU
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124
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125 (define_insn_reservation "thunderx_fadd" 4
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126 (and (eq_attr "tune" "thunderx")
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127 (eq_attr "type" "faddd,fadds"))
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128 "thunderx_pipe1")
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129
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130 (define_insn_reservation "thunderx_fconst" 1
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131 (and (eq_attr "tune" "thunderx")
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132 (eq_attr "type" "fconsts,fconstd"))
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133 "thunderx_pipe1")
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134
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135 ;; Moves between fp are 2 cycles including min/max
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136 (define_insn_reservation "thunderx_fmov" 2
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137 (and (eq_attr "tune" "thunderx")
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138 (eq_attr "type" "fmov,f_minmaxs,f_minmaxd"))
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139 "thunderx_pipe1")
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140
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141 ;; ABS, and NEG are 1 cycle
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142 (define_insn_reservation "thunderx_fabs" 1
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143 (and (eq_attr "tune" "thunderx")
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144 (eq_attr "type" "ffariths,ffarithd"))
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145 "thunderx_pipe1")
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146
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147 (define_insn_reservation "thunderx_fcsel" 3
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148 (and (eq_attr "tune" "thunderx")
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149 (eq_attr "type" "fcsel"))
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150 "thunderx_pipe1")
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151
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152 (define_insn_reservation "thunderx_fmovgpr" 2
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153 (and (eq_attr "tune" "thunderx")
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154 (eq_attr "type" "f_mrc, f_mcr"))
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155 "thunderx_pipe1")
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156
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157 (define_insn_reservation "thunderx_fcmp" 3
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158 (and (eq_attr "tune" "thunderx")
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159 (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
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160 "thunderx_pipe1")
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161
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162 (define_insn_reservation "thunderx_fmul" 6
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163 (and (eq_attr "tune" "thunderx")
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164 (eq_attr "type" "fmacs,fmacd,fmuls,fmuld"))
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165 "thunderx_pipe1")
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166
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167 (define_insn_reservation "thunderx_fdivs" 12
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168 (and (eq_attr "tune" "thunderx")
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169 (eq_attr "type" "fdivs"))
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170 "thunderx_pipe1 + thunderx_divide, thunderx_divide*8")
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171
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172 (define_insn_reservation "thunderx_fdivd" 22
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173 (and (eq_attr "tune" "thunderx")
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174 (eq_attr "type" "fdivd"))
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175 "thunderx_pipe1 + thunderx_divide, thunderx_divide*18")
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176
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177 (define_insn_reservation "thunderx_fsqrts" 17
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178 (and (eq_attr "tune" "thunderx")
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179 (eq_attr "type" "fsqrts"))
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180 "thunderx_pipe1 + thunderx_divide, thunderx_divide*13")
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181
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182 (define_insn_reservation "thunderx_fsqrtd" 31
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183 (and (eq_attr "tune" "thunderx")
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184 (eq_attr "type" "fsqrtd"))
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185 "thunderx_pipe1 + thunderx_divide, thunderx_divide*27")
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186
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187 ;; The rounding conversion inside fp is 4 cycles
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188 (define_insn_reservation "thunderx_frint" 4
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189 (and (eq_attr "tune" "thunderx")
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190 (eq_attr "type" "f_cvt,f_rints,f_rintd"))
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191 "thunderx_pipe1")
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192
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193 ;; Float to integer with a move from int to/from float is 6 cycles
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194 (define_insn_reservation "thunderx_f_cvt" 6
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195 (and (eq_attr "tune" "thunderx")
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196 (eq_attr "type" "f_cvtf2i,f_cvti2f"))
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197 "thunderx_pipe1")
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198
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199 ;; FP/SIMD load/stores happen in pipe 0
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200 ;; 64bit Loads register/pairs are 4 cycles from L1
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201 (define_insn_reservation "thunderx_64simd_fp_load" 4
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202 (and (eq_attr "tune" "thunderx")
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203 (eq_attr "type" "f_loadd,f_loads,neon_load1_1reg,\
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204 neon_load1_1reg_q,neon_load1_2reg"))
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205 "thunderx_pipe0")
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206
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207 ;; 128bit load pair is singled issue and 4 cycles from L1
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208 (define_insn_reservation "thunderx_128simd_pair_load" 4
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209 (and (eq_attr "tune" "thunderx")
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210 (eq_attr "type" "neon_load1_2reg_q"))
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211 "thunderx_pipe0+thunderx_pipe1")
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212
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213 ;; FP/SIMD Stores takes one cycle in pipe 0
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214 ;; ST1 with one registers either multiple structures or single structure is
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215 ;; also one cycle.
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216 (define_insn_reservation "thunderx_simd_fp_store" 1
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217 (and (eq_attr "tune" "thunderx")
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218 (eq_attr "type" "f_stored,f_stores,neon_store1_1reg,neon_store1_1reg_q, \
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219 neon_store1_one_lane, neon_store1_one_lane_q"))
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220 "thunderx_pipe0")
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221
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222 ;; 64bit neon store pairs are single issue for one cycle
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223 (define_insn_reservation "thunderx_64neon_storepair" 1
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224 (and (eq_attr "tune" "thunderx")
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225 (eq_attr "type" "neon_store1_2reg"))
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226 "thunderx_pipe0 + thunderx_pipe1")
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227
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228 ;; 128bit neon store pair are single issued for two cycles
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229 (define_insn_reservation "thunderx_128neon_storepair" 2
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230 (and (eq_attr "tune" "thunderx")
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231 (eq_attr "type" "neon_store1_2reg_q"))
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232 "(thunderx_pipe0 + thunderx_pipe1)*2")
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233
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234 ;; LD1R/LD1 (with a single struct) takes 6 cycles and issued in pipe0
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235 (define_insn_reservation "thunderx_neon_ld1" 6
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236 (and (eq_attr "tune" "thunderx")
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237 (eq_attr "type" "neon_load1_all_lanes"))
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238 "thunderx_pipe0")
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239
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240 ;; SIMD/NEON (q forms take an extra cycle)
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241 ;; SIMD For ThunderX is 64bit wide,
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242
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243 ;; ThunderX simd move instruction types - 2/3 cycles
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244 ;; ThunderX dup, ins is the same
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245 ;; ThunderX SIMD fabs/fneg instruction types
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246 (define_insn_reservation "thunderx_neon_move" 2
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247 (and (eq_attr "tune" "thunderx")
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248 (eq_attr "type" "neon_logic, neon_bsl, neon_fp_compare_s, \
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249 neon_fp_compare_d, neon_move, neon_dup, \
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250 neon_ins, neon_from_gp, neon_to_gp, \
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251 neon_abs, neon_neg, \
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252 neon_fp_neg_s, neon_fp_abs_s"))
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253 "thunderx_pipe1 + thunderx_simd")
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254
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255 (define_insn_reservation "thunderx_neon_move_q" 3
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256 (and (eq_attr "tune" "thunderx")
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257 (eq_attr "type" "neon_logic_q, neon_bsl_q, neon_fp_compare_s_q, \
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258 neon_fp_compare_d_q, neon_move_q, neon_dup_q, \
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259 neon_ins_q, neon_from_gp_q, neon_to_gp_q, \
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260 neon_abs_q, neon_neg_q, \
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261 neon_fp_neg_s_q, neon_fp_neg_d_q, \
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262 neon_fp_abs_s_q, neon_fp_abs_d_q"))
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263 "thunderx_pipe1 + thunderx_simd, thunderx_simd")
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264
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265 ;; ThunderX simd simple/add instruction types - 4/5 cycles
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266
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267 (define_insn_reservation "thunderx_neon_add" 4
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268 (and (eq_attr "tune" "thunderx")
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269 (eq_attr "type" "neon_reduc_add, neon_reduc_minmax, neon_fp_reduc_add_s, \
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270 neon_fp_reduc_add_d, neon_fp_to_int_s, neon_fp_to_int_d, \
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271 neon_add_halve, neon_sub_halve, neon_qadd, neon_compare, \
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272 neon_compare_zero, neon_minmax, neon_abd, neon_add, neon_sub, \
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273 neon_fp_minmax_s, neon_fp_minmax_d, neon_reduc_add, neon_cls, \
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274 neon_qabs, neon_qneg, neon_fp_addsub_s, neon_fp_addsub_d, \
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275 neon_arith_acc, neon_rev, neon_fp_abd_s, neon_fp_abd_d, \
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276 neon_fp_reduc_minmax_s"))
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277 "thunderx_pipe1 + thunderx_simd")
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278
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279 ;; BIG NOTE: neon_add_long/neon_sub_long don't have a q form which is incorrect
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280
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281 (define_insn_reservation "thunderx_neon_add_q" 5
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282 (and (eq_attr "tune" "thunderx")
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283 (eq_attr "type" "neon_reduc_add_q, neon_reduc_minmax_q, neon_fp_reduc_add_s_q, \
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284 neon_fp_reduc_add_d_q, neon_fp_to_int_s_q, neon_fp_to_int_d_q, \
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285 neon_add_halve_q, neon_sub_halve_q, neon_qadd_q, neon_compare_q, \
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286 neon_compare_zero_q, neon_minmax_q, neon_abd_q, neon_add_q, neon_sub_q, \
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287 neon_fp_minmax_s_q, neon_fp_minmax_d_q, neon_reduc_add_q, neon_cls_q, \
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288 neon_qabs_q, neon_qneg_q, neon_fp_addsub_s_q, neon_fp_addsub_d_q, \
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289 neon_add_long, neon_sub_long, neon_fp_abd_s_q, neon_fp_abd_d_q, \
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290 neon_arith_acc_q, neon_rev_q, \
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291 neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d_q"))
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292 "thunderx_pipe1 + thunderx_simd, thunderx_simd")
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293
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294 ;; Multiplies (float and integer) and shifts and permutes (except for TBL) and float conversions
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295 ;; are 6/7 cycles
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296 (define_insn_reservation "thunderx_neon_mult" 6
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297 (and (eq_attr "tune" "thunderx")
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298 (eq_attr "type" "neon_fp_mul_s, neon_fp_mul_d, neon_fp_mla_s, neon_fp_mla_d, \
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299 neon_mla_b, neon_mla_h, neon_mla_s, \
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300 neon_mla_h_scalar, neon_mla_s_scalar, \
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301 neon_ext, neon_shift_imm, neon_permute, \
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302 neon_int_to_fp_s, neon_int_to_fp_d, neon_shift_reg, \
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303 neon_sat_shift_reg, neon_shift_acc, \
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304 neon_mul_b, neon_mul_h, neon_mul_s, \
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305 neon_mul_h_scalar, neon_mul_s_scalar, \
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306 neon_fp_mul_s_scalar, \
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307 neon_fp_mla_s_scalar"))
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308 "thunderx_pipe1 + thunderx_simd")
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309
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310 (define_insn_reservation "thunderx_neon_mult_q" 7
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311 (and (eq_attr "tune" "thunderx")
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312 (eq_attr "type" "neon_fp_mul_s_q, neon_fp_mul_d_q, neon_fp_mla_s_q, neon_fp_mla_d_q, \
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313 neon_mla_b_q, neon_mla_h_q, neon_mla_s_q, \
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314 neon_mla_h_scalar_q, neon_mla_s_scalar_q, \
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315 neon_ext_q, neon_shift_imm_q, neon_permute_q, \
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316 neon_int_to_fp_s_q, neon_int_to_fp_d_q, neon_shift_reg_q, \
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317 neon_sat_shift_reg_q, neon_shift_acc_q, \
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318 neon_shift_imm_long, \
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319 neon_mul_b_q, neon_mul_h_q, neon_mul_s_q, \
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320 neon_mul_h_scalar_q, neon_mul_s_scalar_q, \
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321 neon_fp_mul_s_scalar_q, neon_fp_mul_d_scalar_q, \
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322 neon_mul_b_long, neon_mul_h_long, neon_mul_s_long, \
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323 neon_shift_imm_narrow_q, neon_fp_cvt_widen_s, neon_fp_cvt_narrow_d_q, \
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324 neon_fp_mla_s_scalar_q, neon_fp_mla_d_scalar_q"))
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325 "thunderx_pipe1 + thunderx_simd, thunderx_simd")
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326
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327
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328 ;; AES[ED] is 5 cycles
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329 (define_insn_reservation "thunderx_crypto_aese" 5
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330 (and (eq_attr "tune" "thunderx")
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331 (eq_attr "type" "crypto_aese"))
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332 "thunderx_pipe1 + thunderx_simd, thunderx_simd")
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333
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334 ;; AES{,I}MC is 3 cycles
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335 (define_insn_reservation "thunderx_crypto_aesmc" 3
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336 (and (eq_attr "tune" "thunderx")
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337 (eq_attr "type" "crypto_aesmc"))
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338 "thunderx_pipe1 + thunderx_simd, thunderx_simd")
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339
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340
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341 ;; Thunder 128bit SIMD reads the upper halve in cycle 2 and writes upper halve in the last cycle
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342 (define_bypass 2 "thunderx_neon_move_q" "thunderx_neon_move_q, thunderx_neon_add_q, thunderx_neon_mult_q")
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343 (define_bypass 4 "thunderx_neon_add_q" "thunderx_neon_move_q, thunderx_neon_add_q, thunderx_neon_mult_q")
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344 (define_bypass 6 "thunderx_neon_mult_q" "thunderx_neon_move_q, thunderx_neon_add_q, thunderx_neon_mult_q")
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345
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346 ;; 64bit TBL is emulated and takes 160 cycles
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347 (define_insn_reservation "thunderx_tbl" 160
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348 (and (eq_attr "tune" "thunderx")
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349 (eq_attr "type" "neon_tbl1"))
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350 "(thunderx_pipe1+thunderx_pipe0)*160")
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351
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352 ;; 128bit TBL is emulated and takes 320 cycles
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353 (define_insn_reservation "thunderx_tblq" 320
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354 (and (eq_attr "tune" "thunderx")
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355 (eq_attr "type" "neon_tbl1_q"))
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356 "(thunderx_pipe1+thunderx_pipe0)*320")
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357
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358 ;; Assume both pipes are needed for unknown and multiple-instruction
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359 ;; patterns.
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360
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361 (define_insn_reservation "thunderx_unknown" 1
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362 (and (eq_attr "tune" "thunderx")
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363 (eq_attr "type" "untyped,multiple"))
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364 "thunderx_pipe0 + thunderx_pipe1")
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365
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366
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