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1 ;; Scheduling description for Alpha EV4.
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2 ;; Copyright (C) 2002-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ; On EV4 there are two classes of resources to consider: resources needed
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21 ; to issue, and resources needed to execute. IBUS[01] are in the first
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22 ; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
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23 ; (There are a few other register-like resources, but ...)
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24
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25 (define_automaton "ev4_0,ev4_1,ev4_2")
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26 (define_cpu_unit "ev4_ib0,ev4_ib1,ev4_abox,ev4_bbox" "ev4_0")
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27 (define_cpu_unit "ev4_ebox,ev4_imul" "ev4_1")
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28 (define_cpu_unit "ev4_fbox,ev4_fdiv" "ev4_2")
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29 (define_reservation "ev4_ib01" "ev4_ib0|ev4_ib1")
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30
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31 ; Assume type "multi" single issues.
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32 (define_insn_reservation "ev4_multi" 1
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33 (and (eq_attr "tune" "ev4")
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34 (eq_attr "type" "multi"))
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35 "ev4_ib0+ev4_ib1")
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36
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37 ; Loads from L0 completes in three cycles. adjust_cost still factors
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38 ; in user-specified memory latency, so return 1 here.
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39 (define_insn_reservation "ev4_ld" 1
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40 (and (eq_attr "tune" "ev4")
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41 (eq_attr "type" "ild,fld,ldsym,ld_l"))
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42 "ev4_ib01+ev4_abox")
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43
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44 ; Stores can issue before the data (but not address) is ready.
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45 (define_insn_reservation "ev4_ist" 1
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46 (and (eq_attr "tune" "ev4")
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47 (eq_attr "type" "ist"))
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48 "ev4_ib1+ev4_abox")
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49
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50 ; ??? Separate from ev4_ist because store_data_bypass_p can't handle
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51 ; the patterns with multiple sets, like store-conditional.
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52 (define_insn_reservation "ev4_ist_c" 1
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53 (and (eq_attr "tune" "ev4")
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54 (eq_attr "type" "st_c"))
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55 "ev4_ib1+ev4_abox")
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56
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57 (define_insn_reservation "ev4_fst" 1
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58 (and (eq_attr "tune" "ev4")
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59 (eq_attr "type" "fst"))
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60 "ev4_ib0+ev4_abox")
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61
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62 ; Memory barrier blocks ABOX insns until it's acknowledged by the external
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63 ; memory bus. This may be *quite* slow. Setting this to 4 cycles gets
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64 ; about all the benefit without making the DFA too large.
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65 (define_insn_reservation "ev4_mb" 4
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66 (and (eq_attr "tune" "ev4")
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67 (eq_attr "type" "mb"))
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68 "ev4_ib1+ev4_abox,ev4_abox*3")
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69
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70 ; Branches have no delay cost, but do tie up the unit for two cycles.
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71 (define_insn_reservation "ev4_ibr" 2
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72 (and (eq_attr "tune" "ev4")
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73 (eq_attr "type" "ibr,jsr"))
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74 "ev4_ib1+ev4_bbox,ev4_bbox")
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75
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76 (define_insn_reservation "ev4_callpal" 2
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77 (and (eq_attr "tune" "ev4")
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78 (eq_attr "type" "callpal"))
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79 "ev4_ib1+ev4_bbox,ev4_bbox")
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80
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81 (define_insn_reservation "ev4_fbr" 2
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82 (and (eq_attr "tune" "ev4")
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83 (eq_attr "type" "fbr"))
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84 "ev4_ib0+ev4_bbox,ev4_bbox")
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85
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86 ; Arithmetic insns are normally have their results available after
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87 ; two cycles. There are a number of exceptions.
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88
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89 (define_insn_reservation "ev4_iaddlog" 2
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90 (and (eq_attr "tune" "ev4")
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91 (eq_attr "type" "iadd,ilog"))
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92 "ev4_ib0+ev4_ebox")
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93
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94 (define_bypass 1
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95 "ev4_iaddlog"
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96 "ev4_ibr,ev4_iaddlog,ev4_shiftcm,ev4_icmp,ev4_imulsi,ev4_imuldi")
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97
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98 (define_insn_reservation "ev4_shiftcm" 2
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99 (and (eq_attr "tune" "ev4")
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100 (eq_attr "type" "shift,icmov"))
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101 "ev4_ib0+ev4_ebox")
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102
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103 (define_insn_reservation "ev4_icmp" 2
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104 (and (eq_attr "tune" "ev4")
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105 (eq_attr "type" "icmp"))
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106 "ev4_ib0+ev4_ebox")
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107
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108 (define_bypass 1 "ev4_icmp" "ev4_ibr")
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109
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110 (define_bypass 0
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111 "ev4_iaddlog,ev4_shiftcm,ev4_icmp"
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112 "ev4_ist"
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113 "store_data_bypass_p")
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114
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115 ; Multiplies use a non-pipelined imul unit. Also, "no [ebox] insn can
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116 ; be issued exactly three cycles before an integer multiply completes".
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117
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118 (define_insn_reservation "ev4_imulsi" 21
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119 (and (eq_attr "tune" "ev4")
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120 (and (eq_attr "type" "imul")
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121 (eq_attr "opsize" "si")))
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122 "ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox")
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123
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124 (define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p")
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125
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126 (define_insn_reservation "ev4_imuldi" 23
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127 (and (eq_attr "tune" "ev4")
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128 (and (eq_attr "type" "imul")
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129 (eq_attr "opsize" "!si")))
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130 "ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox")
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131
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132 (define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p")
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133
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134 ; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in.
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135 (define_insn_reservation "ev4_fpop" 6
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136 (and (eq_attr "tune" "ev4")
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137 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
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138 "ev4_ib1+ev4_fbox")
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139
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140 (define_bypass 4 "ev4_fpop" "ev4_fpop")
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141
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142 ; The floating point divider is not pipelined. Also, "no FPOP insn can be
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143 ; issued exactly five or exactly six cycles before an fdiv insn completes".
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144
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145 (define_insn_reservation "ev4_fdivsf" 34
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146 (and (eq_attr "tune" "ev4")
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147 (and (eq_attr "type" "fdiv")
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148 (eq_attr "opsize" "si")))
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149 "ev4_ib1+ev4_fdiv,ev4_fdiv*28,ev4_fdiv+ev4_fbox,ev4_fbox")
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150
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151 (define_insn_reservation "ev4_fdivdf" 63
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152 (and (eq_attr "tune" "ev4")
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153 (and (eq_attr "type" "fdiv")
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154 (eq_attr "opsize" "di")))
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155 "ev4_ib1+ev4_fdiv,ev4_fdiv*57,ev4_fdiv+ev4_fbox,ev4_fbox")
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156
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157 ; Traps don't consume or produce data.
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158 (define_insn_reservation "ev4_misc" 1
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159 (and (eq_attr "tune" "ev4")
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160 (eq_attr "type" "misc"))
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161 "ev4_ib1")
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