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1 ;; Scheduling description for Alpha EV5.
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2 ;; Copyright (C) 2002-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; EV5 has two asymmetric integer units, E0 and E1, plus separate
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21 ;; FP add and multiply units.
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22
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23 (define_automaton "ev5_0,ev5_1")
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24 (define_cpu_unit "ev5_e0,ev5_e1,ev5_fa,ev5_fm" "ev5_0")
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25 (define_reservation "ev5_e01" "ev5_e0|ev5_e1")
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26 (define_reservation "ev5_fam" "ev5_fa|ev5_fm")
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27 (define_cpu_unit "ev5_imul" "ev5_0")
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28 (define_cpu_unit "ev5_fdiv" "ev5_1")
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29
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30 ; Assume type "multi" single issues.
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31 (define_insn_reservation "ev5_multi" 1
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32 (and (eq_attr "tune" "ev5")
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33 (eq_attr "type" "multi"))
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34 "ev5_e0+ev5_e1+ev5_fa+ev5_fm")
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35
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36 ; Stores can only issue to E0, and may not issue with loads.
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37 ; Model this with some fake units.
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38
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39 (define_cpu_unit "ev5_l0,ev5_l1,ev5_st" "ev5_0")
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40 (define_reservation "ev5_ld" "ev5_l0|ev5_l1")
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41 (exclusion_set "ev5_l0,ev5_l1" "ev5_st")
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42
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43 (define_insn_reservation "ev5_st" 1
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44 (and (eq_attr "tune" "ev5")
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45 (eq_attr "type" "ist,fst,st_c,mb"))
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46 "ev5_e0+ev5_st")
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47
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48 ; Loads from L0 complete in two cycles. adjust_cost still factors
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49 ; in user-specified memory latency, so return 1 here.
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50 (define_insn_reservation "ev5_ld" 1
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51 (and (eq_attr "tune" "ev5")
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52 (eq_attr "type" "ild,fld,ldsym"))
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53 "ev5_e01+ev5_ld")
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54
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55 (define_insn_reservation "ev5_ld_l" 1
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56 (and (eq_attr "tune" "ev5")
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57 (eq_attr "type" "ld_l"))
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58 "ev5_e0+ev5_ld")
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59
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60 ; Integer branches slot only to E1.
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61 (define_insn_reservation "ev5_ibr" 1
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62 (and (eq_attr "tune" "ev5")
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63 (eq_attr "type" "ibr"))
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64 "ev5_e1")
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65
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66 (define_insn_reservation "ev5_callpal" 1
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67 (and (eq_attr "tune" "ev5")
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68 (eq_attr "type" "callpal"))
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69 "ev5_e1")
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70
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71 (define_insn_reservation "ev5_jsr" 1
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72 (and (eq_attr "tune" "ev5")
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73 (eq_attr "type" "jsr"))
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74 "ev5_e1")
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75
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76 (define_insn_reservation "ev5_shift" 1
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77 (and (eq_attr "tune" "ev5")
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78 (eq_attr "type" "shift"))
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79 "ev5_e0")
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80
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81 (define_insn_reservation "ev5_mvi" 2
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82 (and (eq_attr "tune" "ev5")
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83 (eq_attr "type" "mvi"))
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84 "ev5_e0")
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85
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86 (define_insn_reservation "ev5_cmov" 2
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87 (and (eq_attr "tune" "ev5")
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88 (eq_attr "type" "icmov"))
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89 "ev5_e01")
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90
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91 (define_insn_reservation "ev5_iadd" 1
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92 (and (eq_attr "tune" "ev5")
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93 (eq_attr "type" "iadd"))
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94 "ev5_e01")
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95
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96 (define_insn_reservation "ev5_ilogcmp" 1
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97 (and (eq_attr "tune" "ev5")
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98 (eq_attr "type" "ilog,icmp"))
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99 "ev5_e01")
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100
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101 ; Conditional move and branch can issue the same cycle as the test.
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102 (define_bypass 0 "ev5_ilogcmp" "ev5_ibr,ev5_cmov" "if_test_bypass_p")
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103
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104 ; Multiplies use a non-pipelined imul unit. Also, "no insn can be issued
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105 ; to E0 exactly two cycles before an integer multiply completes".
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106
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107 (define_insn_reservation "ev5_imull" 8
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108 (and (eq_attr "tune" "ev5")
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109 (and (eq_attr "type" "imul")
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110 (eq_attr "opsize" "si")))
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111 "ev5_e0+ev5_imul,ev5_imul*3,nothing,ev5_e0")
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112
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113 (define_insn_reservation "ev5_imulq" 12
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114 (and (eq_attr "tune" "ev5")
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115 (and (eq_attr "type" "imul")
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116 (eq_attr "opsize" "di")))
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117 "ev5_e0+ev5_imul,ev5_imul*7,nothing,ev5_e0")
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118
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119 (define_insn_reservation "ev5_imulh" 14
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120 (and (eq_attr "tune" "ev5")
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121 (and (eq_attr "type" "imul")
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122 (eq_attr "opsize" "udi")))
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123 "ev5_e0+ev5_imul,ev5_imul*7,nothing*3,ev5_e0")
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124
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125 ; The multiplier is unable to receive data from Ebox bypass paths. The
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126 ; instruction issues at the expected time, but its latency is increased
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127 ; by the time it takes for the input data to become available to the
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128 ; multiplier. For example, an IMULL instruction issued one cycle later
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129 ; than an ADDL instruction, which produced one of its operands, has a
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130 ; latency of 10 (8 + 2). If the IMULL instruction is issued two cycles
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131 ; later than the ADDL instruction, the latency is 9 (8 + 1).
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132 ;
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133 ; Model this instead with increased latency on the input instruction.
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134
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135 (define_bypass 3
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136 "ev5_ld,ev5_ld_l,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
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137 "ev5_imull,ev5_imulq,ev5_imulh")
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138
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139 (define_bypass 9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh")
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140 (define_bypass 13 "ev5_imulq" "ev5_imull,ev5_imulq,ev5_imulh")
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141 (define_bypass 15 "ev5_imulh" "ev5_imull,ev5_imulq,ev5_imulh")
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142
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143 ; Similarly for the FPU we have two asymmetric units.
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144
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145 (define_insn_reservation "ev5_fadd" 4
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146 (and (eq_attr "tune" "ev5")
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147 (eq_attr "type" "fadd,fcmov"))
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148 "ev5_fa")
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149
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150 (define_insn_reservation "ev5_fbr" 1
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151 (and (eq_attr "tune" "ev5")
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152 (eq_attr "type" "fbr"))
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153 "ev5_fa")
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154
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155 (define_insn_reservation "ev5_fcpys" 4
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156 (and (eq_attr "tune" "ev5")
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157 (eq_attr "type" "fcpys"))
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158 "ev5_fam")
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159
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160 (define_insn_reservation "ev5_fmul" 4
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161 (and (eq_attr "tune" "ev5")
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162 (eq_attr "type" "fmul"))
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163 "ev5_fm")
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164
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165 ; The floating point divider is not pipelined. Also, "no insn can be issued
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166 ; to FA exactly five before an fdiv insn completes".
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167 ;
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168 ; ??? Do not model this late reservation due to the enormously increased
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169 ; size of the resulting DFA.
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170 ;
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171 ; ??? Putting ev5_fa and ev5_fdiv alone into the same automata produces
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172 ; a DFA of acceptable size, but putting ev5_fm and ev5_fa into separate
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173 ; automata produces incorrect results for insns that can choose one or
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174 ; the other, i.e. ev5_fcpys.
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175
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176 (define_insn_reservation "ev5_fdivsf" 15
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177 (and (eq_attr "tune" "ev5")
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178 (and (eq_attr "type" "fdiv")
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179 (eq_attr "opsize" "si")))
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180 ; "ev5_fa+ev5_fdiv,ev5_fdiv*9,ev5_fa+ev5_fdiv,ev5_fdiv*4"
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181 "ev5_fa+ev5_fdiv,ev5_fdiv*14")
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182
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183 (define_insn_reservation "ev5_fdivdf" 22
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184 (and (eq_attr "tune" "ev5")
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185 (and (eq_attr "type" "fdiv")
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186 (eq_attr "opsize" "di")))
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187 ; "ev5_fa+ev5_fdiv,ev5_fdiv*17,ev5_fa+ev5_fdiv,ev5_fdiv*4"
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188 "ev5_fa+ev5_fdiv,ev5_fdiv*21")
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189
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190 ; Traps don't consume or produce data; rpcc is latency 2 if we ever add it.
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191 (define_insn_reservation "ev5_misc" 2
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192 (and (eq_attr "tune" "ev5")
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193 (eq_attr "type" "misc"))
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194 "ev5_e0")
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