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1 ;; ARM Cortex-A57 pipeline description
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2 ;; Copyright (C) 2014-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but
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12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 ;; General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "cortex_a57")
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21
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22 (define_attr "cortex_a57_neon_type"
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23 "neon_abd, neon_abd_q, neon_arith_acc, neon_arith_acc_q,
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24 neon_arith_basic, neon_arith_complex,
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25 neon_reduc_add_acc, neon_multiply, neon_multiply_q,
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26 neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long,
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27 neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic,
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28 neon_shift_imm_complex,
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29 neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex,
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30 neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith,
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31 neon_fp_arith_q, neon_fp_reductions_q, neon_fp_cvt_int,
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32 neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul,
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33 neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte,
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34 neon_fp_recpe_rsqrte_q, neon_fp_recps_rsqrts, neon_fp_recps_rsqrts_q,
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35 neon_bitops, neon_bitops_q, neon_from_gp,
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36 neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp,
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37 neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e,
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38 neon_load_f, neon_store_a, neon_store_b, neon_store_complex,
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39 unknown"
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40 (cond [
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41 (eq_attr "type" "neon_abd, neon_abd_long")
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42 (const_string "neon_abd")
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43 (eq_attr "type" "neon_abd_q")
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44 (const_string "neon_abd_q")
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45 (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\
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46 neon_reduc_add_acc_q")
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47 (const_string "neon_arith_acc")
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48 (eq_attr "type" "neon_arith_acc_q")
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49 (const_string "neon_arith_acc_q")
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50 (eq_attr "type" "neon_add, neon_add_q, neon_add_long,\
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51 neon_add_widen, neon_neg, neon_neg_q,\
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52 neon_reduc_add, neon_reduc_add_q,\
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53 neon_reduc_add_long, neon_sub, neon_sub_q,\
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54 neon_sub_long, neon_sub_widen, neon_logic,\
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55 neon_logic_q, neon_tst, neon_tst_q")
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56 (const_string "neon_arith_basic")
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57 (eq_attr "type" "neon_abs, neon_abs_q, neon_add_halve_narrow_q,\
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58 neon_add_halve, neon_add_halve_q,\
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59 neon_sub_halve, neon_sub_halve_q, neon_qabs,\
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60 neon_qabs_q, neon_qadd, neon_qadd_q, neon_qneg,\
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61 neon_qneg_q, neon_qsub, neon_qsub_q,\
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62 neon_sub_halve_narrow_q,\
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63 neon_compare, neon_compare_q,\
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64 neon_compare_zero, neon_compare_zero_q,\
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65 neon_minmax, neon_minmax_q, neon_reduc_minmax,\
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66 neon_reduc_minmax_q")
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67 (const_string "neon_arith_complex")
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68
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69 (eq_attr "type" "neon_mul_b, neon_mul_h, neon_mul_s,\
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70 neon_mul_h_scalar, neon_mul_s_scalar,\
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71 neon_sat_mul_b, neon_sat_mul_h,\
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72 neon_sat_mul_s, neon_sat_mul_h_scalar,\
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73 neon_sat_mul_s_scalar,\
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74 neon_mul_b_long, neon_mul_h_long,\
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75 neon_mul_s_long, neon_mul_d_long,\
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76 neon_mul_h_scalar_long, neon_mul_s_scalar_long,\
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77 neon_sat_mul_b_long, neon_sat_mul_h_long,\
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78 neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\
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79 neon_sat_mul_s_scalar_long, crypto_pmull")
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80 (const_string "neon_multiply")
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81 (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\
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82 neon_mul_h_scalar_q, neon_mul_s_scalar_q,\
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83 neon_sat_mul_b_q, neon_sat_mul_h_q,\
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84 neon_sat_mul_s_q, neon_sat_mul_h_scalar_q,\
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85 neon_sat_mul_s_scalar_q")
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86 (const_string "neon_multiply_q")
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87 (eq_attr "type" "neon_mla_b, neon_mla_h, neon_mla_s,\
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88 neon_mla_h_scalar, neon_mla_s_scalar,\
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89 neon_mla_b_long, neon_mla_h_long,\
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90 neon_mla_s_long,\
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91 neon_mla_h_scalar_long, neon_mla_s_scalar_long")
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92 (const_string "neon_mla")
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93 (eq_attr "type" "neon_mla_b_q, neon_mla_h_q, neon_mla_s_q,\
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94 neon_mla_h_scalar_q, neon_mla_s_scalar_q")
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95 (const_string "neon_mla_q")
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96 (eq_attr "type" "neon_sat_mla_b_long, neon_sat_mla_h_long,\
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97 neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\
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98 neon_sat_mla_s_scalar_long")
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99 (const_string "neon_sat_mla_long")
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100
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101 (eq_attr "type" "neon_shift_acc, neon_shift_acc_q")
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102 (const_string "neon_shift_acc")
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103 (eq_attr "type" "neon_shift_imm, neon_shift_imm_q,\
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104 neon_shift_imm_narrow_q, neon_shift_imm_long")
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105 (const_string "neon_shift_imm_basic")
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106 (eq_attr "type" "neon_sat_shift_imm, neon_sat_shift_imm_q,\
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107 neon_sat_shift_imm_narrow_q")
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108 (const_string "neon_shift_imm_complex")
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109 (eq_attr "type" "neon_shift_reg")
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110 (const_string "neon_shift_reg_basic")
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111 (eq_attr "type" "neon_shift_reg_q")
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112 (const_string "neon_shift_reg_basic_q")
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113 (eq_attr "type" "neon_sat_shift_reg")
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114 (const_string "neon_shift_reg_complex")
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115 (eq_attr "type" "neon_sat_shift_reg_q")
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116 (const_string "neon_shift_reg_complex_q")
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117
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118 (eq_attr "type" "neon_fp_neg_s, neon_fp_neg_s_q,\
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119 neon_fp_abs_s, neon_fp_abs_s_q,\
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120 neon_fp_neg_d, neon_fp_neg_d_q,\
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121 neon_fp_abs_d, neon_fp_abs_d_q")
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122 (const_string "neon_fp_negabs")
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123 (eq_attr "type" "neon_fp_addsub_s, neon_fp_abd_s,\
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124 neon_fp_reduc_add_s, neon_fp_compare_s,\
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125 neon_fp_minmax_s, neon_fp_round_s,\
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126 neon_fp_addsub_d, neon_fp_abd_d,\
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127 neon_fp_reduc_add_d, neon_fp_compare_d,\
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128 neon_fp_minmax_d, neon_fp_round_d,\
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129 neon_fp_reduc_minmax_s, neon_fp_reduc_minmax_d")
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130 (const_string "neon_fp_arith")
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131 (eq_attr "type" "neon_fp_addsub_s_q, neon_fp_abd_s_q,\
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132 neon_fp_reduc_add_s_q, neon_fp_compare_s_q,\
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133 neon_fp_minmax_s_q, neon_fp_round_s_q,\
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134 neon_fp_addsub_d_q, neon_fp_abd_d_q,\
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135 neon_fp_reduc_add_d_q, neon_fp_compare_d_q,\
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136 neon_fp_minmax_d_q, neon_fp_round_d_q")
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137 (const_string "neon_fp_arith_q")
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138 (eq_attr "type" "neon_fp_reduc_minmax_s_q,\
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139 neon_fp_reduc_minmax_d_q,\
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140 neon_fp_reduc_add_s_q, neon_fp_reduc_add_d_q")
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141 (const_string "neon_fp_reductions_q")
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142 (eq_attr "type" "neon_fp_to_int_s, neon_int_to_fp_s,\
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143 neon_fp_to_int_d, neon_int_to_fp_d")
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144 (const_string "neon_fp_cvt_int")
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145 (eq_attr "type" "neon_fp_to_int_s_q, neon_int_to_fp_s_q,\
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146 neon_fp_to_int_d_q, neon_int_to_fp_d_q")
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147 (const_string "neon_fp_cvt_int_q")
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148 (eq_attr "type" "neon_fp_cvt_narrow_s_q, neon_fp_cvt_widen_h")
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149 (const_string "neon_fp_cvt16")
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150 (eq_attr "type" "neon_fp_mul_s, neon_fp_mul_s_scalar,\
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151 neon_fp_mul_d")
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152 (const_string "neon_fp_mul")
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153 (eq_attr "type" "neon_fp_mul_s_q, neon_fp_mul_s_scalar_q,\
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154 neon_fp_mul_d_q, neon_fp_mul_d_scalar_q")
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155 (const_string "neon_fp_mul_q")
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156 (eq_attr "type" "neon_fp_mla_s, neon_fp_mla_s_scalar,\
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157 neon_fp_mla_d")
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158 (const_string "neon_fp_mla")
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159 (eq_attr "type" "neon_fp_mla_s_q, neon_fp_mla_s_scalar_q,
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160 neon_fp_mla_d_q, neon_fp_mla_d_scalar_q")
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161 (const_string "neon_fp_mla_q")
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162 (eq_attr "type" "neon_fp_recpe_s, neon_fp_rsqrte_s,\
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163 neon_fp_recpx_s,\
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164 neon_fp_recpe_d, neon_fp_rsqrte_d,\
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165 neon_fp_recpx_d")
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166 (const_string "neon_fp_recpe_rsqrte")
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167 (eq_attr "type" "neon_fp_recpe_s_q, neon_fp_rsqrte_s_q,\
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168 neon_fp_recpx_s_q,\
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169 neon_fp_recpe_d_q, neon_fp_rsqrte_d_q,\
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170 neon_fp_recpx_d_q")
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171 (const_string "neon_fp_recpe_rsqrte_q")
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172 (eq_attr "type" "neon_fp_recps_s, neon_fp_rsqrts_s,\
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173 neon_fp_recps_d, neon_fp_rsqrts_d")
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174 (const_string "neon_fp_recps_rsqrts")
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175 (eq_attr "type" "neon_fp_recps_s_q, neon_fp_rsqrts_s_q,\
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176 neon_fp_recps_d_q, neon_fp_rsqrts_d_q")
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177 (const_string "neon_fp_recps_rsqrts_q")
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178 (eq_attr "type" "neon_bsl, neon_cls, neon_cnt,\
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179 neon_rev, neon_permute, neon_rbit,\
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180 neon_tbl1, neon_tbl2, neon_zip,\
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181 neon_dup, neon_dup_q, neon_ext, neon_ext_q,\
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182 neon_move, neon_move_q, neon_move_narrow_q")
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183 (const_string "neon_bitops")
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184 (eq_attr "type" "neon_bsl_q, neon_cls_q, neon_cnt_q,\
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185 neon_rev_q, neon_permute_q, neon_rbit_q")
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186 (const_string "neon_bitops_q")
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187 (eq_attr "type" "neon_from_gp,f_mcr,f_mcrr")
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188 (const_string "neon_from_gp")
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189 (eq_attr "type" "neon_from_gp_q")
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190 (const_string "neon_from_gp_q")
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191 (eq_attr "type" "neon_tbl3, neon_tbl4")
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192 (const_string "neon_tbl3_tbl4")
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193 (eq_attr "type" "neon_zip_q")
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194 (const_string "neon_zip_q")
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195 (eq_attr "type" "neon_to_gp, neon_to_gp_q,f_mrc,f_mrrc")
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196 (const_string "neon_to_gp")
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197
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198 (eq_attr "type" "f_loads, f_loadd,\
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199 neon_load1_1reg, neon_load1_1reg_q,\
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200 neon_load1_2reg, neon_load1_2reg_q")
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201 (const_string "neon_load_a")
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202 (eq_attr "type" "neon_load1_3reg, neon_load1_3reg_q,\
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203 neon_load1_4reg, neon_load1_4reg_q")
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204 (const_string "neon_load_b")
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205 (eq_attr "type" "neon_ldp, neon_ldp_q,\
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206 neon_load1_one_lane, neon_load1_one_lane_q,\
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207 neon_load1_all_lanes, neon_load1_all_lanes_q,\
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208 neon_load2_2reg, neon_load2_2reg_q,\
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209 neon_load2_all_lanes, neon_load2_all_lanes_q")
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210 (const_string "neon_load_c")
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211 (eq_attr "type" "neon_load2_4reg, neon_load2_4reg_q,\
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212 neon_load3_3reg, neon_load3_3reg_q,\
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213 neon_load3_one_lane, neon_load3_one_lane_q,\
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214 neon_load4_4reg, neon_load4_4reg_q")
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215 (const_string "neon_load_d")
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216 (eq_attr "type" "neon_load2_one_lane, neon_load2_one_lane_q,\
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217 neon_load3_all_lanes, neon_load3_all_lanes_q,\
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218 neon_load4_all_lanes, neon_load4_all_lanes_q")
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219 (const_string "neon_load_e")
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220 (eq_attr "type" "neon_load4_one_lane, neon_load4_one_lane_q")
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221 (const_string "neon_load_f")
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222
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223 (eq_attr "type" "f_stores, f_stored,\
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224 neon_store1_1reg")
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225 (const_string "neon_store_a")
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226 (eq_attr "type" "neon_store1_2reg, neon_store1_1reg_q")
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227 (const_string "neon_store_b")
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228 (eq_attr "type" "neon_stp, neon_stp_q,\
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229 neon_store1_3reg, neon_store1_3reg_q,\
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230 neon_store3_3reg, neon_store3_3reg_q,\
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231 neon_store2_4reg, neon_store2_4reg_q,\
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232 neon_store4_4reg, neon_store4_4reg_q,\
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233 neon_store2_2reg, neon_store2_2reg_q,\
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234 neon_store3_one_lane, neon_store3_one_lane_q,\
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235 neon_store4_one_lane, neon_store4_one_lane_q,\
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236 neon_store1_4reg, neon_store1_4reg_q,\
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237 neon_store1_one_lane, neon_store1_one_lane_q,\
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238 neon_store2_one_lane, neon_store2_one_lane_q")
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239 (const_string "neon_store_complex")]
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240 (const_string "unknown")))
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241
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242 ;; The Cortex-A57 core is modelled as a triple issue pipeline that has
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243 ;; the following functional units.
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244 ;; 1. Two pipelines for integer operations: SX1, SX2
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245
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246 (define_cpu_unit "ca57_sx1_issue" "cortex_a57")
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247 (define_reservation "ca57_sx1" "ca57_sx1_issue")
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248
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249 (define_cpu_unit "ca57_sx2_issue" "cortex_a57")
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250 (define_reservation "ca57_sx2" "ca57_sx2_issue")
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251
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252 ;; 2. One pipeline for complex integer operations: MX
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253
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254 (define_cpu_unit "ca57_mx_issue"
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255 "cortex_a57")
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256 (define_reservation "ca57_mx" "ca57_mx_issue")
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257 (define_reservation "ca57_mx_block" "ca57_mx_issue")
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258
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259 ;; 3. Two asymmetric pipelines for Neon and FP operations: CX1, CX2
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260 (define_automaton "cortex_a57_cx")
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261
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262 (define_cpu_unit "ca57_cx1_issue"
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263 "cortex_a57_cx")
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264 (define_cpu_unit "ca57_cx2_issue"
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265 "cortex_a57_cx")
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266
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267 (define_reservation "ca57_cx1" "ca57_cx1_issue")
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268
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269 (define_reservation "ca57_cx2" "ca57_cx2_issue")
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270 (define_reservation "ca57_cx2_block" "ca57_cx2_issue*2")
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271
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272 ;; 4. One pipeline for branch operations: BX
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273
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274 (define_cpu_unit "ca57_bx_issue" "cortex_a57")
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275 (define_reservation "ca57_bx" "ca57_bx_issue")
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276
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277 ;; 5. Two pipelines for load and store operations: LS1, LS2. The most
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278 ;; valuable thing we can do is force a structural hazard to split
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279 ;; up loads/stores.
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280
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281 (define_cpu_unit "ca57_ls_issue" "cortex_a57")
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282 (define_cpu_unit "ca57_ldr, ca57_str" "cortex_a57")
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283 (define_reservation "ca57_load_model" "ca57_ls_issue,ca57_ldr*2")
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284 (define_reservation "ca57_store_model" "ca57_ls_issue,ca57_str")
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285
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286 ;; Block all issue queues.
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287
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288 (define_reservation "ca57_block" "ca57_cx1_issue + ca57_cx2_issue
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289 + ca57_mx_issue + ca57_sx1_issue
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290 + ca57_sx2_issue + ca57_ls_issue")
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291
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292 ;; Simple Execution Unit:
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293 ;;
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294 ;; Simple ALU without shift
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295 (define_insn_reservation "cortex_a57_alu" 2
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296 (and (eq_attr "tune" "cortexa57")
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297 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
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298 alu_sreg,alus_sreg,logic_reg,logics_reg,\
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299 adc_imm,adcs_imm,adc_reg,adcs_reg,\
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300 adr,bfx,extend,clz,rbit,rev,alu_dsp_reg,\
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301 rotate_imm,shift_imm,shift_reg,\
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302 mov_imm,mov_reg,\
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303 mvn_imm,mvn_reg,\
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304 mrs,multiple,no_insn"))
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305 "ca57_sx1|ca57_sx2")
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306
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307 ;; ALU ops with immediate shift
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308 (define_insn_reservation "cortex_a57_alu_shift" 3
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309 (and (eq_attr "tune" "cortexa57")
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310 (eq_attr "type" "bfm,\
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311 alu_shift_imm,alus_shift_imm,\
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312 crc,logic_shift_imm,logics_shift_imm,\
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313 mov_shift,mvn_shift"))
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314 "ca57_mx")
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315
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316 ;; Multi-Cycle Execution Unit:
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317 ;;
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318 ;; ALU ops with register controlled shift
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319 (define_insn_reservation "cortex_a57_alu_shift_reg" 3
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320 (and (eq_attr "tune" "cortexa57")
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321 (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
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322 logic_shift_reg,logics_shift_reg,\
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323 mov_shift_reg,mvn_shift_reg"))
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324 "ca57_mx")
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325
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326 ;; All multiplies
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327 ;; TODO: AArch32 and AArch64 have different behavior
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328 (define_insn_reservation "cortex_a57_mult32" 3
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329 (and (eq_attr "tune" "cortexa57")
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330 (ior (eq_attr "mul32" "yes")
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331 (eq_attr "mul64" "yes")))
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332 "ca57_mx")
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333
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334 ;; Integer divide
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335 (define_insn_reservation "cortex_a57_div" 10
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336 (and (eq_attr "tune" "cortexa57")
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337 (eq_attr "type" "udiv,sdiv"))
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338 "ca57_mx_issue,ca57_mx_block*3")
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339
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340 ;; Block all issue pipes for a cycle
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341 (define_insn_reservation "cortex_a57_block" 1
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342 (and (eq_attr "tune" "cortexa57")
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343 (eq_attr "type" "block"))
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344 "ca57_block")
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345
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346 ;; Branch execution Unit
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347 ;;
|
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348 ;; Branches take one issue slot.
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349 ;; No latency as there is no result
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350 (define_insn_reservation "cortex_a57_branch" 0
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351 (and (eq_attr "tune" "cortexa57")
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352 (eq_attr "type" "branch"))
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353 "ca57_bx")
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354
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355 ;; Load-store execution Unit
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356 ;;
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357 ;; Loads of up to two words.
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358 (define_insn_reservation "cortex_a57_load1" 5
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359 (and (eq_attr "tune" "cortexa57")
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360 (eq_attr "type" "load_byte,load_4,load_8"))
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361 "ca57_load_model")
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|
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362
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363 ;; Loads of three or four words.
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364 (define_insn_reservation "cortex_a57_load3" 5
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365 (and (eq_attr "tune" "cortexa57")
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366 (eq_attr "type" "load_12,load_16"))
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367 "ca57_ls_issue*2,ca57_load_model")
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368
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369 ;; Stores of up to two words.
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|
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370 (define_insn_reservation "cortex_a57_store1" 0
|
|
|
371 (and (eq_attr "tune" "cortexa57")
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|
372 (eq_attr "type" "store_4,store_8"))
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|
|
373 "ca57_store_model")
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374
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|
375 ;; Stores of three or four words.
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|
|
376 (define_insn_reservation "cortex_a57_store3" 0
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|
|
377 (and (eq_attr "tune" "cortexa57")
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|
|
378 (eq_attr "type" "store_12,store_16"))
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|
|
379 "ca57_ls_issue*2,ca57_store_model")
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|
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380
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|
|
381 ;; Advanced SIMD Unit - Integer Arithmetic Instructions.
|
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382
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|
|
383 (define_insn_reservation "cortex_a57_neon_abd" 5
|
|
|
384 (and (eq_attr "tune" "cortexa57")
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|
|
385 (eq_attr "cortex_a57_neon_type" "neon_abd"))
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|
|
386 "ca57_cx1|ca57_cx2")
|
|
|
387
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|
|
388 (define_insn_reservation "cortex_a57_neon_abd_q" 5
|
|
|
389 (and (eq_attr "tune" "cortexa57")
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|
|
390 (eq_attr "cortex_a57_neon_type" "neon_abd_q"))
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|
|
391 "ca57_cx1+ca57_cx2")
|
|
|
392
|
|
|
393 (define_insn_reservation "cortex_a57_neon_aba" 7
|
|
|
394 (and (eq_attr "tune" "cortexa57")
|
|
|
395 (eq_attr "cortex_a57_neon_type" "neon_arith_acc"))
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|
|
396 "ca57_cx2")
|
|
|
397
|
|
|
398 (define_insn_reservation "cortex_a57_neon_aba_q" 8
|
|
|
399 (and (eq_attr "tune" "cortexa57")
|
|
|
400 (eq_attr "cortex_a57_neon_type" "neon_arith_acc_q"))
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|
|
401 "ca57_cx2+(ca57_cx2_issue,ca57_cx2)")
|
|
|
402
|
|
|
403 (define_insn_reservation "cortex_a57_neon_arith_basic" 4
|
|
|
404 (and (eq_attr "tune" "cortexa57")
|
|
|
405 (eq_attr "cortex_a57_neon_type" "neon_arith_basic"))
|
|
|
406 "ca57_cx1|ca57_cx2")
|
|
|
407
|
|
|
408 (define_insn_reservation "cortex_a57_neon_arith_complex" 5
|
|
|
409 (and (eq_attr "tune" "cortexa57")
|
|
|
410 (eq_attr "cortex_a57_neon_type" "neon_arith_complex"))
|
|
|
411 "ca57_cx1|ca57_cx2")
|
|
|
412
|
|
|
413 ;; Integer Multiply Instructions.
|
|
|
414
|
|
|
415 (define_insn_reservation "cortex_a57_neon_multiply" 6
|
|
|
416 (and (eq_attr "tune" "cortexa57")
|
|
|
417 (eq_attr "cortex_a57_neon_type" "neon_multiply"))
|
|
|
418 "ca57_cx1")
|
|
|
419
|
|
|
420 (define_insn_reservation "cortex_a57_neon_multiply_q" 7
|
|
|
421 (and (eq_attr "tune" "cortexa57")
|
|
|
422 (eq_attr "cortex_a57_neon_type" "neon_multiply_q"))
|
|
|
423 "ca57_cx1+(ca57_cx1_issue,ca57_cx1)")
|
|
|
424
|
|
|
425 (define_insn_reservation "cortex_a57_neon_mla" 6
|
|
|
426 (and (eq_attr "tune" "cortexa57")
|
|
|
427 (eq_attr "cortex_a57_neon_type" "neon_mla"))
|
|
|
428 "ca57_cx1")
|
|
|
429
|
|
|
430 (define_insn_reservation "cortex_a57_neon_mla_q" 7
|
|
|
431 (and (eq_attr "tune" "cortexa57")
|
|
|
432 (eq_attr "cortex_a57_neon_type" "neon_mla_q"))
|
|
|
433 "ca57_cx1+(ca57_cx1_issue,ca57_cx1)")
|
|
|
434
|
|
|
435 (define_insn_reservation "cortex_a57_neon_sat_mla_long" 6
|
|
|
436 (and (eq_attr "tune" "cortexa57")
|
|
|
437 (eq_attr "cortex_a57_neon_type" "neon_sat_mla_long"))
|
|
|
438 "ca57_cx1")
|
|
|
439
|
|
|
440 ;; Integer Shift Instructions.
|
|
|
441
|
|
|
442 (define_insn_reservation
|
|
|
443 "cortex_a57_neon_shift_acc" 7
|
|
|
444 (and (eq_attr "tune" "cortexa57")
|
|
|
445 (eq_attr "cortex_a57_neon_type" "neon_shift_acc"))
|
|
|
446 "ca57_cx2")
|
|
|
447
|
|
|
448 (define_insn_reservation
|
|
|
449 "cortex_a57_neon_shift_imm_basic" 4
|
|
|
450 (and (eq_attr "tune" "cortexa57")
|
|
|
451 (eq_attr "cortex_a57_neon_type" "neon_shift_imm_basic"))
|
|
|
452 "ca57_cx2")
|
|
|
453
|
|
|
454 (define_insn_reservation
|
|
|
455 "cortex_a57_neon_shift_imm_complex" 5
|
|
|
456 (and (eq_attr "tune" "cortexa57")
|
|
|
457 (eq_attr "cortex_a57_neon_type" "neon_shift_imm_complex"))
|
|
|
458 "ca57_cx2")
|
|
|
459
|
|
|
460 (define_insn_reservation
|
|
|
461 "cortex_a57_neon_shift_reg_basic" 4
|
|
|
462 (and (eq_attr "tune" "cortexa57")
|
|
|
463 (eq_attr "cortex_a57_neon_type" "neon_shift_reg_basic"))
|
|
|
464 "ca57_cx2")
|
|
|
465
|
|
|
466 (define_insn_reservation
|
|
|
467 "cortex_a57_neon_shift_reg_basic_q" 5
|
|
|
468 (and (eq_attr "tune" "cortexa57")
|
|
|
469 (eq_attr "cortex_a57_neon_type" "neon_shift_reg_basic_q"))
|
|
|
470 "ca57_cx2+(ca57_cx2_issue,ca57_cx2)")
|
|
|
471
|
|
|
472 (define_insn_reservation
|
|
|
473 "cortex_a57_neon_shift_reg_complex" 5
|
|
|
474 (and (eq_attr "tune" "cortexa57")
|
|
|
475 (eq_attr "cortex_a57_neon_type" "neon_shift_reg_complex"))
|
|
|
476 "ca57_cx2")
|
|
|
477
|
|
|
478 (define_insn_reservation
|
|
|
479 "cortex_a57_neon_shift_reg_complex_q" 6
|
|
|
480 (and (eq_attr "tune" "cortexa57")
|
|
|
481 (eq_attr "cortex_a57_neon_type" "neon_shift_reg_complex_q"))
|
|
|
482 "ca57_cx2+(ca57_cx2_issue,ca57_cx2)")
|
|
|
483
|
|
|
484 ;; Floating Point Instructions.
|
|
|
485
|
|
|
486 (define_insn_reservation
|
|
|
487 "cortex_a57_neon_fp_negabs" 4
|
|
|
488 (and (eq_attr "tune" "cortexa57")
|
|
|
489 (eq_attr "cortex_a57_neon_type" "neon_fp_negabs"))
|
|
|
490 "(ca57_cx1|ca57_cx2)")
|
|
|
491
|
|
|
492 (define_insn_reservation
|
|
|
493 "cortex_a57_neon_fp_arith" 6
|
|
|
494 (and (eq_attr "tune" "cortexa57")
|
|
|
495 (eq_attr "cortex_a57_neon_type" "neon_fp_arith"))
|
|
|
496 "(ca57_cx1|ca57_cx2)")
|
|
|
497
|
|
|
498 (define_insn_reservation
|
|
|
499 "cortex_a57_neon_fp_arith_q" 6
|
|
|
500 (and (eq_attr "tune" "cortexa57")
|
|
|
501 (eq_attr "cortex_a57_neon_type" "neon_fp_arith_q"))
|
|
|
502 "(ca57_cx1+ca57_cx2)")
|
|
|
503
|
|
|
504 (define_insn_reservation
|
|
|
505 "cortex_a57_neon_fp_reductions_q" 10
|
|
|
506 (and (eq_attr "tune" "cortexa57")
|
|
|
507 (eq_attr "cortex_a57_neon_type" "neon_fp_reductions_q"))
|
|
|
508 "(ca57_cx1+ca57_cx2),(ca57_cx1|ca57_cx2)")
|
|
|
509
|
|
|
510 (define_insn_reservation
|
|
|
511 "cortex_a57_neon_fp_cvt_int" 6
|
|
|
512 (and (eq_attr "tune" "cortexa57")
|
|
|
513 (eq_attr "cortex_a57_neon_type" "neon_fp_cvt_int"))
|
|
|
514 "(ca57_cx1|ca57_cx2)")
|
|
|
515
|
|
|
516 (define_insn_reservation
|
|
|
517 "cortex_a57_neon_fp_cvt_int_q" 6
|
|
|
518 (and (eq_attr "tune" "cortexa57")
|
|
|
519 (eq_attr "cortex_a57_neon_type" "neon_fp_cvt_int_q"))
|
|
|
520 "(ca57_cx1+ca57_cx2)")
|
|
|
521
|
|
|
522 (define_insn_reservation
|
|
|
523 "cortex_a57_neon_fp_cvt16" 10
|
|
|
524 (and (eq_attr "tune" "cortexa57")
|
|
|
525 (eq_attr "cortex_a57_neon_type" "neon_fp_cvt16"))
|
|
|
526 "(ca57_cx1_issue+ca57_cx2_issue),(ca57_cx1|ca57_cx2)")
|
|
|
527
|
|
|
528 (define_insn_reservation
|
|
|
529 "cortex_a57_neon_fp_mul" 5
|
|
|
530 (and (eq_attr "tune" "cortexa57")
|
|
|
531 (eq_attr "cortex_a57_neon_type" "neon_fp_mul"))
|
|
|
532 "(ca57_cx1|ca57_cx2)")
|
|
|
533
|
|
|
534 (define_insn_reservation
|
|
|
535 "cortex_a57_neon_fp_mul_q" 5
|
|
|
536 (and (eq_attr "tune" "cortexa57")
|
|
|
537 (eq_attr "cortex_a57_neon_type" "neon_fp_mul_q"))
|
|
|
538 "(ca57_cx1+ca57_cx2)")
|
|
|
539
|
|
|
540 (define_insn_reservation
|
|
|
541 "cortex_a57_neon_fp_mla" 9
|
|
|
542 (and (eq_attr "tune" "cortexa57")
|
|
|
543 (eq_attr "cortex_a57_neon_type" "neon_fp_mla"))
|
|
|
544 "(ca57_cx1,ca57_cx1)|(ca57_cx2,ca57_cx2)")
|
|
|
545
|
|
|
546 (define_insn_reservation
|
|
|
547 "cortex_a57_neon_fp_mla_q" 9
|
|
|
548 (and (eq_attr "tune" "cortexa57")
|
|
|
549 (eq_attr "cortex_a57_neon_type" "neon_fp_mla_q"))
|
|
|
550 "(ca57_cx1+ca57_cx2),(ca57_cx1,ca57_cx2)")
|
|
|
551
|
|
|
552 (define_insn_reservation
|
|
|
553 "cortex_a57_neon_fp_recpe_rsqrte" 6
|
|
|
554 (and (eq_attr "tune" "cortexa57")
|
|
|
555 (eq_attr "cortex_a57_neon_type" "neon_fp_recpe_rsqrte"))
|
|
|
556 "(ca57_cx1|ca57_cx2)")
|
|
|
557
|
|
|
558 (define_insn_reservation
|
|
|
559 "cortex_a57_neon_fp_recpe_rsqrte_q" 6
|
|
|
560 (and (eq_attr "tune" "cortexa57")
|
|
|
561 (eq_attr "cortex_a57_neon_type" "neon_fp_recpe_rsqrte_q"))
|
|
|
562 "(ca57_cx1+ca57_cx2)")
|
|
|
563
|
|
|
564 (define_insn_reservation
|
|
|
565 "cortex_a57_neon_fp_recps_rsqrts" 10
|
|
|
566 (and (eq_attr "tune" "cortexa57")
|
|
|
567 (eq_attr "cortex_a57_neon_type" "neon_fp_recps_rsqrts"))
|
|
|
568 "(ca57_cx1|ca57_cx2)")
|
|
|
569
|
|
|
570 (define_insn_reservation
|
|
|
571 "cortex_a57_neon_fp_recps_rsqrts_q" 10
|
|
|
572 (and (eq_attr "tune" "cortexa57")
|
|
|
573 (eq_attr "cortex_a57_neon_type" "neon_fp_recps_rsqrts_q"))
|
|
|
574 "(ca57_cx1+ca57_cx2)")
|
|
|
575
|
|
|
576 ;; Miscellaneous Instructions.
|
|
|
577
|
|
|
578 (define_insn_reservation
|
|
|
579 "cortex_a57_neon_bitops" 4
|
|
|
580 (and (eq_attr "tune" "cortexa57")
|
|
|
581 (eq_attr "cortex_a57_neon_type" "neon_bitops"))
|
|
|
582 "(ca57_cx1|ca57_cx2)")
|
|
|
583
|
|
|
584 (define_insn_reservation
|
|
|
585 "cortex_a57_neon_bitops_q" 4
|
|
|
586 (and (eq_attr "tune" "cortexa57")
|
|
|
587 (eq_attr "cortex_a57_neon_type" "neon_bitops_q"))
|
|
|
588 "(ca57_cx1+ca57_cx2)")
|
|
|
589
|
|
|
590 (define_insn_reservation
|
|
|
591 "cortex_a57_neon_from_gp" 9
|
|
|
592 (and (eq_attr "tune" "cortexa57")
|
|
|
593 (eq_attr "cortex_a57_neon_type" "neon_from_gp"))
|
|
|
594 "(ca57_ls_issue+ca57_cx1_issue,ca57_cx1)
|
|
|
595 |(ca57_ls_issue+ca57_cx2_issue,ca57_cx2)")
|
|
|
596
|
|
|
597 (define_insn_reservation
|
|
|
598 "cortex_a57_neon_from_gp_q" 9
|
|
|
599 (and (eq_attr "tune" "cortexa57")
|
|
|
600 (eq_attr "cortex_a57_neon_type" "neon_from_gp_q"))
|
|
|
601 "(ca57_ls_issue+ca57_cx1_issue,ca57_cx1)
|
|
|
602 +(ca57_ls_issue+ca57_cx2_issue,ca57_cx2)")
|
|
|
603
|
|
|
604 (define_insn_reservation
|
|
|
605 "cortex_a57_neon_tbl3_tbl4" 7
|
|
|
606 (and (eq_attr "tune" "cortexa57")
|
|
|
607 (eq_attr "cortex_a57_neon_type" "neon_tbl3_tbl4"))
|
|
|
608 "(ca57_cx1_issue,ca57_cx1)
|
|
|
609 +(ca57_cx2_issue,ca57_cx2)")
|
|
|
610
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611 (define_insn_reservation
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612 "cortex_a57_neon_zip_q" 7
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613 (and (eq_attr "tune" "cortexa57")
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614 (eq_attr "cortex_a57_neon_type" "neon_zip_q"))
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615 "(ca57_cx1_issue,ca57_cx1)
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616 +(ca57_cx2_issue,ca57_cx2)")
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617
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618 (define_insn_reservation
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619 "cortex_a57_neon_to_gp" 7
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620 (and (eq_attr "tune" "cortexa57")
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621 (eq_attr "cortex_a57_neon_type" "neon_to_gp"))
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622 "((ca57_ls_issue+ca57_sx1_issue),ca57_sx1)
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623 |((ca57_ls_issue+ca57_sx2_issue),ca57_sx2)")
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624
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625 ;; Load Instructions.
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626
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627 (define_insn_reservation
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628 "cortex_a57_neon_load_a" 6
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629 (and (eq_attr "tune" "cortexa57")
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630 (eq_attr "cortex_a57_neon_type" "neon_load_a"))
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631 "ca57_load_model")
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632
|
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|
633 (define_insn_reservation
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634 "cortex_a57_neon_load_b" 7
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635 (and (eq_attr "tune" "cortexa57")
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636 (eq_attr "cortex_a57_neon_type" "neon_load_b"))
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637 "ca57_ls_issue,ca57_ls_issue+ca57_ldr,ca57_ldr*2")
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638
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639 (define_insn_reservation
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640 "cortex_a57_neon_load_c" 9
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641 (and (eq_attr "tune" "cortexa57")
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|
642 (eq_attr "cortex_a57_neon_type" "neon_load_c"))
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643 "ca57_load_model+(ca57_cx1|ca57_cx2)")
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644
|
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645 (define_insn_reservation
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646 "cortex_a57_neon_load_d" 11
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647 (and (eq_attr "tune" "cortexa57")
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648 (eq_attr "cortex_a57_neon_type" "neon_load_d"))
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|
|
649 "ca57_cx1_issue+ca57_cx2_issue,
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650 ca57_ls_issue+ca57_ls_issue,ca57_ldr*2")
|
|
|
651
|
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652 (define_insn_reservation
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653 "cortex_a57_neon_load_e" 9
|
|
|
654 (and (eq_attr "tune" "cortexa57")
|
|
|
655 (eq_attr "cortex_a57_neon_type" "neon_load_e"))
|
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|
656 "ca57_load_model+(ca57_cx1|ca57_cx2)")
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|
657
|
|
|
658 (define_insn_reservation
|
|
|
659 "cortex_a57_neon_load_f" 11
|
|
|
660 (and (eq_attr "tune" "cortexa57")
|
|
|
661 (eq_attr "cortex_a57_neon_type" "neon_load_f"))
|
|
|
662 "ca57_cx1_issue+ca57_cx2_issue,
|
|
|
663 ca57_ls_issue+ca57_ls_issue,ca57_ldr*2")
|
|
|
664
|
|
|
665 ;; Store Instructions.
|
|
|
666
|
|
|
667 (define_insn_reservation
|
|
|
668 "cortex_a57_neon_store_a" 0
|
|
|
669 (and (eq_attr "tune" "cortexa57")
|
|
|
670 (eq_attr "cortex_a57_neon_type" "neon_store_a"))
|
|
|
671 "ca57_store_model")
|
|
|
672
|
|
|
673 (define_insn_reservation
|
|
|
674 "cortex_a57_neon_store_b" 0
|
|
|
675 (and (eq_attr "tune" "cortexa57")
|
|
|
676 (eq_attr "cortex_a57_neon_type" "neon_store_b"))
|
|
|
677 "ca57_store_model")
|
|
|
678
|
|
|
679 ;; These block issue for a number of cycles proportional to the number
|
|
|
680 ;; of 64-bit chunks they will store, we don't attempt to model that
|
|
|
681 ;; precisely, treat them as blocking execution for two cycles when
|
|
|
682 ;; issued.
|
|
|
683 (define_insn_reservation
|
|
|
684 "cortex_a57_neon_store_complex" 0
|
|
|
685 (and (eq_attr "tune" "cortexa57")
|
|
|
686 (eq_attr "cortex_a57_neon_type" "neon_store_complex"))
|
|
|
687 "ca57_block*2")
|
|
|
688
|
|
|
689 ;; Floating-Point Operations.
|
|
|
690
|
|
|
691 (define_insn_reservation "cortex_a57_fp_const" 4
|
|
|
692 (and (eq_attr "tune" "cortexa57")
|
|
|
693 (eq_attr "type" "fconsts,fconstd"))
|
|
|
694 "(ca57_cx1|ca57_cx2)")
|
|
|
695
|
|
|
696 (define_insn_reservation "cortex_a57_fp_add_sub" 6
|
|
|
697 (and (eq_attr "tune" "cortexa57")
|
|
|
698 (eq_attr "type" "fadds,faddd"))
|
|
|
699 "(ca57_cx1|ca57_cx2)")
|
|
|
700
|
|
|
701 (define_insn_reservation "cortex_a57_fp_mul" 6
|
|
|
702 (and (eq_attr "tune" "cortexa57")
|
|
|
703 (eq_attr "type" "fmuls,fmuld"))
|
|
|
704 "(ca57_cx1|ca57_cx2)")
|
|
|
705
|
|
|
706 (define_insn_reservation "cortex_a57_fp_mac" 10
|
|
|
707 (and (eq_attr "tune" "cortexa57")
|
|
|
708 (eq_attr "type" "fmacs,ffmas,fmacd,ffmad"))
|
|
|
709 "(ca57_cx1,nothing,nothing,ca57_cx1) \
|
|
|
710 |(ca57_cx2,nothing,nothing,ca57_cx2)")
|
|
|
711
|
|
|
712 (define_insn_reservation "cortex_a57_fp_cvt" 6
|
|
|
713 (and (eq_attr "tune" "cortexa57")
|
|
|
714 (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
|
|
|
715 "(ca57_cx1|ca57_cx2)")
|
|
|
716
|
|
|
717 (define_insn_reservation "cortex_a57_fp_cmp" 7
|
|
|
718 (and (eq_attr "tune" "cortexa57")
|
|
|
719 (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
|
|
|
720 "ca57_cx2")
|
|
|
721
|
|
|
722 (define_insn_reservation "cortex_a57_fp_arith" 4
|
|
|
723 (and (eq_attr "tune" "cortexa57")
|
|
|
724 (eq_attr "type" "ffariths,ffarithd"))
|
|
|
725 "(ca57_cx1|ca57_cx2)")
|
|
|
726
|
|
|
727 (define_insn_reservation "cortex_a57_fp_cpys" 4
|
|
|
728 (and (eq_attr "tune" "cortexa57")
|
|
|
729 (eq_attr "type" "fmov,fcsel"))
|
|
|
730 "(ca57_cx1|ca57_cx2)")
|
|
|
731
|
|
|
732 (define_insn_reservation "cortex_a57_fp_divs" 12
|
|
|
733 (and (eq_attr "tune" "cortexa57")
|
|
|
734 (eq_attr "type" "fdivs, fsqrts,\
|
|
|
735 neon_fp_div_s, neon_fp_sqrt_s"))
|
|
|
736 "ca57_cx2_block*5")
|
|
|
737
|
|
|
738 (define_insn_reservation "cortex_a57_fp_divd" 16
|
|
|
739 (and (eq_attr "tune" "cortexa57")
|
|
|
740 (eq_attr "type" "fdivd, fsqrtd, neon_fp_div_d, neon_fp_sqrt_d"))
|
|
|
741 "ca57_cx2_block*3")
|
|
|
742
|
|
|
743 (define_insn_reservation "cortex_a57_neon_fp_div_q" 20
|
|
|
744 (and (eq_attr "tune" "cortexa57")
|
|
|
745 (eq_attr "type" "fdivd, fsqrtd,\
|
|
|
746 neon_fp_div_s_q, neon_fp_div_d_q,\
|
|
|
747 neon_fp_sqrt_s_q, neon_fp_sqrt_d_q"))
|
|
|
748 "ca57_cx2_block*3")
|
|
|
749
|
|
|
750 (define_insn_reservation "cortex_a57_crypto_simple" 3
|
|
|
751 (and (eq_attr "tune" "cortexa57")
|
|
|
752 (eq_attr "type" "crypto_aese,crypto_aesmc,crypto_sha1_fast,crypto_sha256_fast"))
|
|
|
753 "ca57_cx1")
|
|
|
754
|
|
|
755 (define_insn_reservation "cortex_a57_crypto_complex" 6
|
|
|
756 (and (eq_attr "tune" "cortexa57")
|
|
|
757 (eq_attr "type" "crypto_sha1_slow,crypto_sha256_slow"))
|
|
|
758 "ca57_cx1*2")
|
|
|
759
|
|
|
760 (define_insn_reservation "cortex_a57_crypto_xor" 6
|
|
|
761 (and (eq_attr "tune" "cortexa57")
|
|
|
762 (eq_attr "type" "crypto_sha1_xor"))
|
|
|
763 "(ca57_cx1*2)|(ca57_cx2*2)")
|
|
|
764
|
|
|
765 ;; We lie with calls. They take up all issue slots, but are otherwise
|
|
|
766 ;; not harmful.
|
|
|
767 (define_insn_reservation "cortex_a57_call" 1
|
|
|
768 (and (eq_attr "tune" "cortexa57")
|
|
|
769 (eq_attr "type" "call"))
|
|
|
770 "ca57_sx1_issue+ca57_sx2_issue+ca57_cx1_issue+ca57_cx2_issue\
|
|
|
771 +ca57_mx_issue+ca57_bx_issue+ca57_ls_issue"
|
|
|
772 )
|
|
|
773
|
|
|
774 ;; Simple execution unit bypasses
|
|
|
775 (define_bypass 1 "cortex_a57_alu"
|
|
|
776 "cortex_a57_alu,cortex_a57_alu_shift,cortex_a57_alu_shift_reg")
|
|
|
777 (define_bypass 2 "cortex_a57_alu_shift"
|
|
|
778 "cortex_a57_alu,cortex_a57_alu_shift,cortex_a57_alu_shift_reg")
|
|
|
779 (define_bypass 2 "cortex_a57_alu_shift_reg"
|
|
|
780 "cortex_a57_alu,cortex_a57_alu_shift,cortex_a57_alu_shift_reg")
|
|
|
781 (define_bypass 1 "cortex_a57_alu" "cortex_a57_load1,cortex_a57_load3")
|
|
|
782 (define_bypass 2 "cortex_a57_alu_shift" "cortex_a57_load1,cortex_a57_load3")
|
|
|
783 (define_bypass 2 "cortex_a57_alu_shift_reg"
|
|
|
784 "cortex_a57_load1,cortex_a57_load3")
|
|
|
785
|
|
|
786 ;; An MLA or a MUL can feed a dependent MLA.
|
|
|
787 (define_bypass 5 "cortex_a57_neon_*mla*,cortex_a57_neon_*mul*"
|
|
|
788 "cortex_a57_neon_*mla*")
|
|
|
789
|
|
|
790 (define_bypass 5 "cortex_a57_fp_mul,cortex_a57_fp_mac"
|
|
|
791 "cortex_a57_fp_mac")
|
|
|
792
|
|
|
793 ;; We don't need to care about control hazards, either the branch is
|
|
|
794 ;; predicted in which case we pay no penalty, or the branch is
|
|
|
795 ;; mispredicted in which case instruction scheduling will be unlikely to
|
|
|
796 ;; help.
|
|
|
797 (define_bypass 1 "cortex_a57_*"
|
|
|
798 "cortex_a57_call,cortex_a57_branch")
|
|
|
799
|
|
|
800 ;; AESE+AESMC and AESD+AESIMC pairs forward with zero latency
|
|
|
801 (define_bypass 0 "cortex_a57_crypto_simple"
|
|
|
802 "cortex_a57_crypto_simple"
|
|
|
803 "aarch_crypto_can_dual_issue")
|
|
|
804
|
