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111
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1 ;; This file contains instructions that support fixed-point operations
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2 ;; for Atmel AVR micro controllers.
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3 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
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4 ;;
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5 ;; Contributed by Sean D'Epagnier (sean@depagnier.com)
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6 ;; Georg-Johann Lay (avr@gjlay.de)
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7
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8 ;; This file is part of GCC.
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9 ;;
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10 ;; GCC is free software; you can redistribute it and/or modify
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11 ;; it under the terms of the GNU General Public License as published by
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12 ;; the Free Software Foundation; either version 3, or (at your option)
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13 ;; any later version.
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14 ;;
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15 ;; GCC is distributed in the hope that it will be useful,
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16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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18 ;; GNU General Public License for more details.
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19 ;;
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20 ;; You should have received a copy of the GNU General Public License
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21 ;; along with GCC; see the file COPYING3. If not see
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22 ;; <http://www.gnu.org/licenses/>.
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23
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24 (define_mode_iterator ALL1Q [QQ UQQ])
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25 (define_mode_iterator ALL2Q [HQ UHQ])
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26 (define_mode_iterator ALL2A [HA UHA])
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27 (define_mode_iterator ALL4A [SA USA])
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28 (define_mode_iterator ALL2QA [HQ UHQ HA UHA])
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29 (define_mode_iterator ALL4QA [SQ USQ SA USA])
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30 (define_mode_iterator ALL124QA [ QQ HQ HA SA SQ
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31 UQQ UHQ UHA USA USQ])
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32
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33 (define_mode_iterator ALL2S [HQ HA])
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34 (define_mode_iterator ALL4S [SA SQ])
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35 (define_mode_iterator ALL24S [ HQ HA SA SQ])
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36 (define_mode_iterator ALL124S [ QQ HQ HA SA SQ])
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37 (define_mode_iterator ALL124U [UQQ UHQ UHA USA USQ])
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38
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39 ;;; Conversions
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40
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41 (define_mode_iterator FIXED_A
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42 [QQ UQQ
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43 HQ UHQ HA UHA
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44 SQ USQ SA USA
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45 DQ UDQ DA UDA
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46 TA UTA
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47 QI HI SI DI])
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48
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49 ;; Same so that be can build cross products
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50
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51 (define_mode_iterator FIXED_B
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52 [QQ UQQ
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53 HQ UHQ HA UHA
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54 SQ USQ SA USA
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55 DQ UDQ DA UDA
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56 TA UTA
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57 QI HI SI DI])
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58
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59 (define_insn "fract<FIXED_B:mode><FIXED_A:mode>2"
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60 [(set (match_operand:FIXED_A 0 "register_operand" "=r")
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61 (fract_convert:FIXED_A
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62 (match_operand:FIXED_B 1 "register_operand" "r")))]
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63 "<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
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64 {
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65 return avr_out_fract (insn, operands, true, NULL);
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66 }
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67 [(set_attr "cc" "clobber")
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68 (set_attr "adjust_len" "sfract")])
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69
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70 (define_insn "fractuns<FIXED_B:mode><FIXED_A:mode>2"
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71 [(set (match_operand:FIXED_A 0 "register_operand" "=r")
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72 (unsigned_fract_convert:FIXED_A
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73 (match_operand:FIXED_B 1 "register_operand" "r")))]
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74 "<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
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75 {
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76 return avr_out_fract (insn, operands, false, NULL);
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77 }
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78 [(set_attr "cc" "clobber")
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79 (set_attr "adjust_len" "ufract")])
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80
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81 ;******************************************************************************
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82 ;** Saturated Addition and Subtraction
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83 ;******************************************************************************
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84
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85 ;; Fixme: It would be nice if we could expand the 32-bit versions to a
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86 ;; transparent libgcc call if $2 is a REG. Problem is that it is
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87 ;; not possible to describe that addition is commutative.
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88 ;; And defining register classes/constraintrs for the involved hard
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89 ;; registers and let IRA do the work, yields inacceptable bloated code.
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90 ;; Thus, we have to live with the up to 11 instructions that are output
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91 ;; for these 32-bit saturated operations.
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92
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93 ;; "ssaddqq3" "ssaddhq3" "ssaddha3" "ssaddsq3" "ssaddsa3"
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94 ;; "sssubqq3" "sssubhq3" "sssubha3" "sssubsq3" "sssubsa3"
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95 (define_insn "<code_stdname><mode>3"
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96 [(set (match_operand:ALL124S 0 "register_operand" "=??d,d")
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97 (ss_addsub:ALL124S (match_operand:ALL124S 1 "register_operand" "<abelian>0,0")
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98 (match_operand:ALL124S 2 "nonmemory_operand" "r,Ynn")))]
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99 ""
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100 {
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101 return avr_out_plus (insn, operands);
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102 }
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103 [(set_attr "cc" "clobber")
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104 (set_attr "adjust_len" "plus")])
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105
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106 ;; "usadduqq3" "usadduhq3" "usadduha3" "usaddusq3" "usaddusa3"
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107 ;; "ussubuqq3" "ussubuhq3" "ussubuha3" "ussubusq3" "ussubusa3"
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108 (define_insn "<code_stdname><mode>3"
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109 [(set (match_operand:ALL124U 0 "register_operand" "=??r,d")
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110 (us_addsub:ALL124U (match_operand:ALL124U 1 "register_operand" "<abelian>0,0")
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111 (match_operand:ALL124U 2 "nonmemory_operand" "r,Ynn")))]
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112 ""
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113 {
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114 return avr_out_plus (insn, operands);
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115 }
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116 [(set_attr "cc" "clobber")
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117 (set_attr "adjust_len" "plus")])
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118
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119 ;******************************************************************************
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120 ;** Saturated Negation and Absolute Value
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121 ;******************************************************************************
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122
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123 ;; Fixme: This will always result in 0. Dunno why simplify-rtx.c says
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124 ;; "unknown" on how to optimize this. libgcc call would be in order,
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125 ;; but the performance is *PLAIN* *HORROR* because the optimizers don't
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126 ;; manage to optimize out MEMCPY that's sprincled all over fixed-bit.c */
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127
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128 (define_expand "usneg<mode>2"
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129 [(parallel [(match_operand:ALL124U 0 "register_operand" "")
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130 (match_operand:ALL124U 1 "nonmemory_operand" "")])]
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131 ""
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132 {
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133 emit_move_insn (operands[0], CONST0_RTX (<MODE>mode));
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134 DONE;
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135 })
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136
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137 (define_insn "ssnegqq2"
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138 [(set (match_operand:QQ 0 "register_operand" "=r")
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139 (ss_neg:QQ (match_operand:QQ 1 "register_operand" "0")))]
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140 ""
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141 "neg %0\;brvc 0f\;dec %0\;0:"
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142 [(set_attr "cc" "clobber")
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143 (set_attr "length" "3")])
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144
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145 (define_insn "ssabsqq2"
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146 [(set (match_operand:QQ 0 "register_operand" "=r")
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147 (ss_abs:QQ (match_operand:QQ 1 "register_operand" "0")))]
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148 ""
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149 "sbrc %0,7\;neg %0\;sbrc %0,7\;dec %0"
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150 [(set_attr "cc" "clobber")
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151 (set_attr "length" "4")])
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152
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153 ;; "ssneghq2" "ssnegha2" "ssnegsq2" "ssnegsa2"
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154 ;; "ssabshq2" "ssabsha2" "ssabssq2" "ssabssa2"
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155 (define_expand "<code_stdname><mode>2"
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156 [(set (match_dup 2)
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157 (match_operand:ALL24S 1 "register_operand" ""))
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158 (set (match_dup 2)
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159 (ss_abs_neg:ALL24S (match_dup 2)))
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160 (set (match_operand:ALL24S 0 "register_operand" "")
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161 (match_dup 2))]
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162 ""
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163 {
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164 operands[2] = gen_rtx_REG (<MODE>mode, 26 - GET_MODE_SIZE (<MODE>mode));
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165 })
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166
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167 ;; "*ssneghq2" "*ssnegha2"
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168 ;; "*ssabshq2" "*ssabsha2"
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169 (define_insn "*<code_stdname><mode>2"
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170 [(set (reg:ALL2S 24)
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171 (ss_abs_neg:ALL2S (reg:ALL2S 24)))]
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172 ""
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173 "%~call __<code_stdname>_2"
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174 [(set_attr "type" "xcall")
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175 (set_attr "cc" "clobber")])
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176
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177 ;; "*ssnegsq2" "*ssnegsa2"
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178 ;; "*ssabssq2" "*ssabssa2"
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179 (define_insn "*<code_stdname><mode>2"
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180 [(set (reg:ALL4S 22)
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181 (ss_abs_neg:ALL4S (reg:ALL4S 22)))]
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182 ""
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183 "%~call __<code_stdname>_4"
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184 [(set_attr "type" "xcall")
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185 (set_attr "cc" "clobber")])
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186
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187 ;******************************************************************************
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188 ; mul
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189
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190 ;; "mulqq3" "muluqq3"
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191 (define_expand "mul<mode>3"
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192 [(parallel [(match_operand:ALL1Q 0 "register_operand" "")
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193 (match_operand:ALL1Q 1 "register_operand" "")
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194 (match_operand:ALL1Q 2 "register_operand" "")])]
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195 ""
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196 {
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197 emit_insn (AVR_HAVE_MUL
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198 ? gen_mul<mode>3_enh (operands[0], operands[1], operands[2])
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199 : gen_mul<mode>3_nomul (operands[0], operands[1], operands[2]));
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200 DONE;
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201 })
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202
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203 (define_insn "mulqq3_enh"
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204 [(set (match_operand:QQ 0 "register_operand" "=r")
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205 (mult:QQ (match_operand:QQ 1 "register_operand" "a")
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206 (match_operand:QQ 2 "register_operand" "a")))]
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207 "AVR_HAVE_MUL"
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208 "fmuls %1,%2\;dec r1\;brvs 0f\;inc r1\;0:\;mov %0,r1\;clr __zero_reg__"
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209 [(set_attr "length" "6")
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210 (set_attr "cc" "clobber")])
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211
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212 (define_insn "muluqq3_enh"
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213 [(set (match_operand:UQQ 0 "register_operand" "=r")
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214 (mult:UQQ (match_operand:UQQ 1 "register_operand" "r")
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215 (match_operand:UQQ 2 "register_operand" "r")))]
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216 "AVR_HAVE_MUL"
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217 "mul %1,%2\;mov %0,r1\;clr __zero_reg__"
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218 [(set_attr "length" "3")
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219 (set_attr "cc" "clobber")])
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220
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221 (define_expand "mulqq3_nomul"
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222 [(set (reg:QQ 24)
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223 (match_operand:QQ 1 "register_operand" ""))
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224 (set (reg:QQ 25)
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225 (match_operand:QQ 2 "register_operand" ""))
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226 ;; "*mulqq3.call"
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227 (parallel [(set (reg:QQ 23)
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228 (mult:QQ (reg:QQ 24)
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229 (reg:QQ 25)))
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230 (clobber (reg:QI 22))
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231 (clobber (reg:HI 24))])
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232 (set (match_operand:QQ 0 "register_operand" "")
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233 (reg:QQ 23))]
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234 "!AVR_HAVE_MUL"
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235 {
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236 avr_fix_inputs (operands, 1 << 2, regmask (QQmode, 24));
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237 })
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238
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239
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240 (define_expand "muluqq3_nomul"
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241 [(set (reg:UQQ 22)
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242 (match_operand:UQQ 1 "register_operand" ""))
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243 (set (reg:UQQ 24)
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244 (match_operand:UQQ 2 "register_operand" ""))
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245 ;; "*umulqihi3.call"
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246 (parallel [(set (reg:HI 24)
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247 (mult:HI (zero_extend:HI (reg:QI 22))
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248 (zero_extend:HI (reg:QI 24))))
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249 (clobber (reg:QI 21))
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250 (clobber (reg:HI 22))])
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251 (set (match_operand:UQQ 0 "register_operand" "")
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252 (reg:UQQ 25))]
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253 "!AVR_HAVE_MUL"
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254 {
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255 avr_fix_inputs (operands, 1 << 2, regmask (UQQmode, 22));
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256 })
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257
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258 (define_insn "*mulqq3.call"
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259 [(set (reg:QQ 23)
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260 (mult:QQ (reg:QQ 24)
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261 (reg:QQ 25)))
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262 (clobber (reg:QI 22))
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263 (clobber (reg:HI 24))]
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264 "!AVR_HAVE_MUL"
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265 "%~call __mulqq3"
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266 [(set_attr "type" "xcall")
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267 (set_attr "cc" "clobber")])
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268
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269
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270 ;; "mulhq3" "muluhq3"
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271 ;; "mulha3" "muluha3"
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272 (define_expand "mul<mode>3"
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273 [(set (reg:ALL2QA 18)
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274 (match_operand:ALL2QA 1 "register_operand" ""))
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275 (set (reg:ALL2QA 26)
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276 (match_operand:ALL2QA 2 "register_operand" ""))
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277 ;; "*mulhq3.call.enh"
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278 (parallel [(set (reg:ALL2QA 24)
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279 (mult:ALL2QA (reg:ALL2QA 18)
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280 (reg:ALL2QA 26)))
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281 (clobber (reg:HI 22))])
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282 (set (match_operand:ALL2QA 0 "register_operand" "")
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283 (reg:ALL2QA 24))]
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284 "AVR_HAVE_MUL"
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285 {
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286 avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 18));
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287 })
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288
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289 ;; "*mulhq3.call" "*muluhq3.call"
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290 ;; "*mulha3.call" "*muluha3.call"
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291 (define_insn "*mul<mode>3.call"
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292 [(set (reg:ALL2QA 24)
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293 (mult:ALL2QA (reg:ALL2QA 18)
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294 (reg:ALL2QA 26)))
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295 (clobber (reg:HI 22))]
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296 "AVR_HAVE_MUL"
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297 "%~call __mul<mode>3"
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298 [(set_attr "type" "xcall")
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299 (set_attr "cc" "clobber")])
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300
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301
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302 ;; On the enhanced core, don't clobber either input and use a separate output
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303
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304 ;; "mulsa3" "mulusa3"
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305 (define_expand "mul<mode>3"
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306 [(set (reg:ALL4A 16)
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307 (match_operand:ALL4A 1 "register_operand" ""))
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308 (set (reg:ALL4A 20)
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309 (match_operand:ALL4A 2 "register_operand" ""))
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310 (set (reg:ALL4A 24)
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311 (mult:ALL4A (reg:ALL4A 16)
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312 (reg:ALL4A 20)))
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313 (set (match_operand:ALL4A 0 "register_operand" "")
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314 (reg:ALL4A 24))]
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315 "AVR_HAVE_MUL"
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316 {
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317 avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 16));
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318 })
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319
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320 ;; "*mulsa3.call" "*mulusa3.call"
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321 (define_insn "*mul<mode>3.call"
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322 [(set (reg:ALL4A 24)
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323 (mult:ALL4A (reg:ALL4A 16)
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324 (reg:ALL4A 20)))]
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325 "AVR_HAVE_MUL"
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326 "%~call __mul<mode>3"
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327 [(set_attr "type" "xcall")
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328 (set_attr "cc" "clobber")])
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329
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330 ; / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
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331 ; div
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332
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333 (define_code_iterator usdiv [udiv div])
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334
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335 ;; "divqq3" "udivuqq3"
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336 (define_expand "<code><mode>3"
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337 [(set (reg:ALL1Q 25)
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338 (match_operand:ALL1Q 1 "register_operand" ""))
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339 (set (reg:ALL1Q 22)
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340 (match_operand:ALL1Q 2 "register_operand" ""))
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341 (parallel [(set (reg:ALL1Q 24)
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342 (usdiv:ALL1Q (reg:ALL1Q 25)
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343 (reg:ALL1Q 22)))
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344 (clobber (reg:QI 25))])
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345 (set (match_operand:ALL1Q 0 "register_operand" "")
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346 (reg:ALL1Q 24))]
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347 ""
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348 {
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349 avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 25));
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350 })
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351
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352
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353 ;; "*divqq3.call" "*udivuqq3.call"
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354 (define_insn "*<code><mode>3.call"
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355 [(set (reg:ALL1Q 24)
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356 (usdiv:ALL1Q (reg:ALL1Q 25)
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357 (reg:ALL1Q 22)))
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358 (clobber (reg:QI 25))]
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359 ""
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360 "%~call __<code><mode>3"
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361 [(set_attr "type" "xcall")
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362 (set_attr "cc" "clobber")])
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363
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364 ;; "divhq3" "udivuhq3"
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365 ;; "divha3" "udivuha3"
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366 (define_expand "<code><mode>3"
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367 [(set (reg:ALL2QA 26)
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368 (match_operand:ALL2QA 1 "register_operand" ""))
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369 (set (reg:ALL2QA 22)
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370 (match_operand:ALL2QA 2 "register_operand" ""))
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371 (parallel [(set (reg:ALL2QA 24)
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372 (usdiv:ALL2QA (reg:ALL2QA 26)
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373 (reg:ALL2QA 22)))
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374 (clobber (reg:HI 26))
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375 (clobber (reg:QI 21))])
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376 (set (match_operand:ALL2QA 0 "register_operand" "")
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377 (reg:ALL2QA 24))]
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378 ""
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379 {
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380 avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 26));
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381 })
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382
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383 ;; "*divhq3.call" "*udivuhq3.call"
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384 ;; "*divha3.call" "*udivuha3.call"
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385 (define_insn "*<code><mode>3.call"
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386 [(set (reg:ALL2QA 24)
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387 (usdiv:ALL2QA (reg:ALL2QA 26)
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388 (reg:ALL2QA 22)))
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389 (clobber (reg:HI 26))
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390 (clobber (reg:QI 21))]
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391 ""
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392 "%~call __<code><mode>3"
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393 [(set_attr "type" "xcall")
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394 (set_attr "cc" "clobber")])
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395
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396 ;; Note the first parameter gets passed in already offset by 2 bytes
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397
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398 ;; "divsa3" "udivusa3"
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399 (define_expand "<code><mode>3"
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400 [(set (reg:ALL4A 24)
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401 (match_operand:ALL4A 1 "register_operand" ""))
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402 (set (reg:ALL4A 18)
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403 (match_operand:ALL4A 2 "register_operand" ""))
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404 (parallel [(set (reg:ALL4A 22)
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405 (usdiv:ALL4A (reg:ALL4A 24)
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406 (reg:ALL4A 18)))
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407 (clobber (reg:HI 26))
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408 (clobber (reg:HI 30))])
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409 (set (match_operand:ALL4A 0 "register_operand" "")
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410 (reg:ALL4A 22))]
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411 ""
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412 {
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413 avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 24));
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414 })
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415
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416 ;; "*divsa3.call" "*udivusa3.call"
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417 (define_insn "*<code><mode>3.call"
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418 [(set (reg:ALL4A 22)
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419 (usdiv:ALL4A (reg:ALL4A 24)
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420 (reg:ALL4A 18)))
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421 (clobber (reg:HI 26))
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422 (clobber (reg:HI 30))]
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423 ""
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424 "%~call __<code><mode>3"
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425 [(set_attr "type" "xcall")
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426 (set_attr "cc" "clobber")])
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427
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428
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429 ;******************************************************************************
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430 ;** Rounding
|
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431 ;******************************************************************************
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432
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433 ;; "roundqq3" "rounduqq3"
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434 ;; "roundhq3" "rounduhq3" "roundha3" "rounduha3"
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435 ;; "roundsq3" "roundusq3" "roundsa3" "roundusa3"
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436 (define_expand "round<mode>3"
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437 [(set (match_dup 4)
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438 (match_operand:ALL124QA 1 "register_operand" ""))
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439 (set (reg:QI 24)
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440 (match_dup 5))
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441 (parallel [(set (match_dup 3)
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442 (unspec:ALL124QA [(match_dup 4)
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443 (reg:QI 24)] UNSPEC_ROUND))
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444 (clobber (match_dup 4))])
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445 (set (match_operand:ALL124QA 0 "register_operand" "")
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446 (match_dup 3))
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447 (use (match_operand:HI 2 "nonmemory_operand" ""))]
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448 ""
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449 {
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450 if (CONST_INT_P (operands[2])
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451 && !(optimize_size
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452 && 4 == GET_MODE_SIZE (<MODE>mode)))
|
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453 {
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454 emit_insn (gen_round<mode>3_const (operands[0], operands[1], operands[2]));
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455 DONE;
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|
456 }
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457
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458 // Input and output of the libgcc function
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459 const unsigned int regno_in[] = { -1U, 22, 22, -1U, 18 };
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460 const unsigned int regno_out[] = { -1U, 24, 24, -1U, 22 };
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461
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462 operands[3] = gen_rtx_REG (<MODE>mode, regno_out[(size_t) GET_MODE_SIZE (<MODE>mode)]);
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|
463 operands[4] = gen_rtx_REG (<MODE>mode, regno_in[(size_t) GET_MODE_SIZE (<MODE>mode)]);
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464 avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, REGNO (operands[4])));
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|
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465 operands[5] = simplify_gen_subreg (QImode, force_reg (HImode, operands[2]), HImode, 0);
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|
|
466 // $2 is no more needed, but is referenced for expand.
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|
467 operands[2] = const0_rtx;
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|
|
468 })
|
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|
469
|
|
|
470 ;; Expand rounding with known rounding points inline so that the addend / mask
|
|
|
471 ;; will be consumed by operation with immediate operands and there is no
|
|
|
472 ;; need for a shift with variable offset.
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473
|
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|
474 ;; "roundqq3_const" "rounduqq3_const"
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|
|
475 ;; "roundhq3_const" "rounduhq3_const" "roundha3_const" "rounduha3_const"
|
|
|
476 ;; "roundsq3_const" "roundusq3_const" "roundsa3_const" "roundusa3_const"
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|
|
477 (define_insn "round<mode>3_const"
|
|
|
478 [(set (match_operand:ALL124QA 0 "register_operand" "=d")
|
|
|
479 (unspec:ALL124QA [(match_operand:ALL124QA 1 "register_operand" "0")
|
|
|
480 (match_operand:HI 2 "const_int_operand" "n")
|
|
|
481 (const_int 0)]
|
|
|
482 UNSPEC_ROUND))]
|
|
|
483 ""
|
|
|
484 {
|
|
|
485 return avr_out_round (insn, operands);
|
|
|
486 }
|
|
|
487 [(set_attr "cc" "clobber")
|
|
|
488 (set_attr "adjust_len" "round")])
|
|
|
489
|
|
|
490
|
|
|
491 ;; "*roundqq3.libgcc" "*rounduqq3.libgcc"
|
|
|
492 (define_insn "*round<mode>3.libgcc"
|
|
|
493 [(set (reg:ALL1Q 24)
|
|
|
494 (unspec:ALL1Q [(reg:ALL1Q 22)
|
|
|
495 (reg:QI 24)] UNSPEC_ROUND))
|
|
|
496 (clobber (reg:ALL1Q 22))]
|
|
|
497 ""
|
|
|
498 "%~call __round<mode>3"
|
|
|
499 [(set_attr "type" "xcall")
|
|
|
500 (set_attr "cc" "clobber")])
|
|
|
501
|
|
|
502 ;; "*roundhq3.libgcc" "*rounduhq3.libgcc"
|
|
|
503 ;; "*roundha3.libgcc" "*rounduha3.libgcc"
|
|
|
504 (define_insn "*round<mode>3.libgcc"
|
|
|
505 [(set (reg:ALL2QA 24)
|
|
|
506 (unspec:ALL2QA [(reg:ALL2QA 22)
|
|
|
507 (reg:QI 24)] UNSPEC_ROUND))
|
|
|
508 (clobber (reg:ALL2QA 22))]
|
|
|
509 ""
|
|
|
510 "%~call __round<mode>3"
|
|
|
511 [(set_attr "type" "xcall")
|
|
|
512 (set_attr "cc" "clobber")])
|
|
|
513
|
|
|
514 ;; "*roundsq3.libgcc" "*roundusq3.libgcc"
|
|
|
515 ;; "*roundsa3.libgcc" "*roundusa3.libgcc"
|
|
|
516 (define_insn "*round<mode>3.libgcc"
|
|
|
517 [(set (reg:ALL4QA 22)
|
|
|
518 (unspec:ALL4QA [(reg:ALL4QA 18)
|
|
|
519 (reg:QI 24)] UNSPEC_ROUND))
|
|
|
520 (clobber (reg:ALL4QA 18))]
|
|
|
521 ""
|
|
|
522 "%~call __round<mode>3"
|
|
|
523 [(set_attr "type" "xcall")
|
|
|
524 (set_attr "cc" "clobber")])
|
