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1 ;; GCC machine description for CRIS atomic memory sequences.
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2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; The CRIS atomic support yields code in three flavors, depending on
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21 ;; the CPU for which code is generated:
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22 ;;
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23 ;; - Plain old CRIS v0 (..v8)
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24 ;; - CRIS v10 (as used in ETRAX 100 LX)
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25 ;; - CRIS v32 (as used in ETRAX FS)
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26 ;;
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27 ;; The last two alternatives are similar, of LL/SC type. They may
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28 ;; fail for other reasons; an exception, a cache miss or a bus request
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29 ;; from other parts of the system. The difference between them is
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30 ;; just in what condition-codes are used to track LL and success or
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31 ;; failure for the store. See the chapter on integral read-write
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32 ;; operations, chapter 1.13 in "ETRAX 100LX Programmers Manual",
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33 ;; <http://www.axis.com/files/tech_notes/etrax_100lx_prog_man-050519.pdf>
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34 ;; and chapter 2.1 in "ETRAX FS Designer's reference",
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35 ;; <http://www.axis.com/files/manuals/etrax_fs_des_ref-070821.pdf>.
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36 ;; Note that the datum being stored has to be contained fully within a
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37 ;; cache-line to be integral. A failure to store the data integrally
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38 ;; will be flagged, but the store may still have happened in part,
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39 ;; which translates most usefully into the data having to be
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40 ;; "naturally aligned" to work. Natural alignment is verified in the
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41 ;; generated code and will by default cause for unaligned pointers a
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42 ;; "break 8" to be executed or optionally a call to abort(). Beware
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43 ;; that options -m16bit and -m8bit may cause data to be unaligned
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44 ;; where it was otherwise aligned. Data has a better chance of being
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45 ;; aligned if it is declared with e.g. __attribute__ ((__align__ (4))).
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46 ;;
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47 ;; The "plain old v0..v8 flavor" just assumes there's a single CPU in
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48 ;; the system, that no other parts of the system have access to memory
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49 ;; used for atomic accesses and since there's no user mode without
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50 ;; access to interrupt flags (another assumption), it just turns off
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51 ;; interrupts while doing the access. Here, alignment is neither
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52 ;; required nor asserted.
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53
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54 (define_c_enum ""
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55 [
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56 CRIS_UNSPEC_ATOMIC_OP
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57 CRIS_UNSPEC_ATOMIC_SWAP_MEM
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58 CRIS_UNSPEC_ATOMIC_SWAP_BOOL
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59 ])
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60
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61 (define_constants [(CRIS_CCR_INTERRUPT_BIT 5)])
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62
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63 ;; We use "mult" as a placeholder for "nand" (which does not have a
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64 ;; separate binary rtx operation) so we can use an iterator in the
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65 ;; define_expand and define_insn and avoid having a separate
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66 ;; mostly-identical copy. You will see the "mult" operator in rtl
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67 ;; dumps, but it shouldn't matter as its use has one of its operands
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68 ;; inside an unspec_volatile.
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69
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70 (define_code_iterator atomic_op [plus minus ior and xor mult])
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71
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72 (define_code_attr atomic_op_name
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73 [(plus "add") (minus "sub") (and "and") (ior "or") (xor "xor") (mult "nand")])
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74
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75 ;; The operator nonatomic-operand can be memory, constant or register
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76 ;; for all but xor. We can't use memory or addressing modes with
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77 ;; side-effects though, so just use registers and literal constants.
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78 (define_code_attr atomic_op_op_cnstr
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79 [(plus "ri") (minus "ri") (and "ri") (ior "ri") (xor "r") (mult "ri")])
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80
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81 (define_code_attr atomic_op_op_pred
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82 [(plus "nonmemory_operand") (minus "nonmemory_operand")
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83 (and "nonmemory_operand") (ior "nonmemory_operand")
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84 (xor "register_operand") (mult "nonmemory_operand")])
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85
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86 ;; Pairs of these are used to insert the "not" after the "and" for nand.
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87 (define_code_attr atomic_op_mnem_pre_op2 ;; Upper-case only to simplify testing.
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88 [(plus "%P2") (minus "Sub.d %2") (and "And%q2 %2") (ior "Or%q2 %2") (xor "Xor %2")
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89 (mult "aNd%q2 %2")])
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90
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91 (define_code_attr atomic_op_mnem_post_op3
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92 [(plus "") (minus "") (and "") (ior "") (xor "") (mult "not %3\;")])
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93
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94 ;; For SImode, emit "q" for operands -31..31.
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95 (define_mode_attr qm3 [(SI "%q3") (HI ".w") (QI ".b")])
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96
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97 (define_expand "atomic_fetch_<atomic_op_name><mode>"
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98 [(match_operand:BWD 0 "register_operand")
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99 (match_operand:BWD 1 "memory_operand")
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100 (match_operand:BWD 2 "<atomic_op_op_pred>")
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101 (match_operand 3)
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102 (atomic_op:BWD (match_dup 0) (match_dup 1))]
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103 "<MODE>mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS"
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104 {
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105 enum memmodel mmodel = (enum memmodel) INTVAL (operands[3]);
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106
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107 if (<MODE>mode != QImode && TARGET_TRAP_UNALIGNED_ATOMIC)
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108 cris_emit_trap_for_misalignment (operands[1]);
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109
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110 if (need_atomic_barrier_p (mmodel, true))
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111 expand_mem_thread_fence (mmodel);
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112
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113 emit_insn (gen_cris_atomic_fetch_<atomic_op_name><mode>_1 (operands[0],
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114 operands[1],
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115 operands[2]));
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116 if (need_atomic_barrier_p (mmodel, false))
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117 expand_mem_thread_fence (mmodel);
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118
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119 DONE;
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120 })
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121
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122 (define_insn "cris_atomic_fetch_<atomic_op_name><mode>_1"
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123 [(set (match_operand:BWD 1 "memory_operand" "+Q")
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124 (atomic_op:BWD
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125 (unspec_volatile:BWD [(match_dup 1)] CRIS_UNSPEC_ATOMIC_OP)
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126 ;; FIXME: improve constants more for plus, minus, and, ior.
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127 ;; FIXME: handle memory operands without side-effects.
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128 (match_operand:BWD 2 "<atomic_op_op_pred>" "<atomic_op_op_cnstr>")))
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129 (set (match_operand:BWD 0 "register_operand" "=&r")
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130 (match_dup 1))
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131 (clobber (match_scratch:SI 3 "=&r"))]
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132 "<MODE>mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS"
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133 {
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134 /* Can't be too sure; better ICE if this happens. */
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135 gcc_assert (!reg_overlap_mentioned_p (operands[2], operands[1]));
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136
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137 if (TARGET_V32)
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138 return
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139 "clearf p\n"
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140 ".Lsync.%=:\;"
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141 "move<m> %1,%0\;"
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142 "move.d %0,%3\;"
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143 "<atomic_op_mnem_pre_op2>,%3\;<atomic_op_mnem_post_op3>"
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144 "ax\;"
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145 "move<m> %3,%1\;"
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146 "bcs .Lsync.%=\;"
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147 "clearf p";
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148 else if (cris_cpu_version == 10)
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149 return
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150 "clearf\n"
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151 ".Lsync.%=:\;"
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152 "move<m> %1,%0\;"
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153 "move.d %0,%3\;"
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154 "<atomic_op_mnem_pre_op2>,%3\;<atomic_op_mnem_post_op3>"
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155 "ax\;"
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156 "move<m> %3,%1\;"
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157 "bwf .Lsync.%=\;"
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158 "clearf";
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159 else
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160 {
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161 /* This one is for CRIS versions without load-locked-store-conditional
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162 machinery; assume single-core-non-shared-memory without user
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163 mode/supervisor mode distinction, and just disable interrupts
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164 while performing the operation.
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165 Rather than making this pattern more complex by freeing another
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166 register or stack position to save condition codes (the value
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167 of the interrupt-enabled bit), we check whether interrupts were
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168 enabled before we disabled them and branch to a version
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169 with/without afterwards re-enabling them. */
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170 rtx ops[5];
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171
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172 /* We have no available macro to stringify CRIS_CCR_INTERRUPT_BIT. */
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173 memcpy (ops, operands, sizeof(ops));
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174 ops[4] = GEN_INT (CRIS_CCR_INTERRUPT_BIT);
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175
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176 output_asm_insn ("move $ccr,%3\;"
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177 "di\;"
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178 "move<m> %1,%0\;"
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179 "btstq %4,%3",
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180 ops);
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181 return
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182 "bmi .Lsync.irqon.%=\;"
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183 "move.d %0,%3\;"
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184
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185 "<atomic_op_mnem_pre_op2>,%3\;<atomic_op_mnem_post_op3>"
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186 "ba .Lsync.irqoff.%=\;"
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187 "move<m> %3,%1\n"
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188
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189 ".Lsync.irqon.%=:\;"
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190 "<atomic_op_mnem_pre_op2>,%3\;<atomic_op_mnem_post_op3>"
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191 "move<m> %3,%1\;"
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192 "ei\n"
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193 ".Lsync.irqoff.%=:";
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194 }
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195 })
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196
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197 ;; This pattern is more-or-less assumed to always exist if any of the
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198 ;; other atomic patterns exist (see e.g. comment at the
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199 ;; can_compare_and_swap_p call in omp-low.c, 4.8 era). We'd slightly
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200 ;; prefer atomic_exchange<mode> over this, but having both would be
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201 ;; redundant.
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202 ;; FIXME: handle memory without side-effects for operand[3].
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203 (define_expand "atomic_compare_and_swap<mode>"
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204 [(match_operand:SI 0 "register_operand")
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205 (match_operand:BWD 1 "register_operand")
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206 (match_operand:BWD 2 "memory_operand")
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207 (match_operand:BWD 3 "nonmemory_operand")
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208 (match_operand:BWD 4 "register_operand")
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209 (match_operand 5)
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210 (match_operand 6)
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211 (match_operand 7)]
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212 "<MODE>mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS"
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213 {
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214 enum memmodel mmodel = (enum memmodel) INTVAL (operands[6]);
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215
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216 if (<MODE>mode != QImode && TARGET_TRAP_UNALIGNED_ATOMIC)
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217 cris_emit_trap_for_misalignment (operands[2]);
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218
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219 if (need_atomic_barrier_p (mmodel, true))
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220 expand_mem_thread_fence (mmodel);
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221
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222 emit_insn (gen_cris_atomic_compare_and_swap<mode>_1 (operands[0],
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223 operands[1],
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224 operands[2],
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225 operands[3],
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226 operands[4]));
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227 if (need_atomic_barrier_p (mmodel, false))
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228 expand_mem_thread_fence (mmodel);
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229
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230 DONE;
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231 })
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232
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233 (define_insn "cris_atomic_compare_and_swap<mode>_1"
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234 [(set (match_operand:SI 0 "register_operand" "=&r")
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235 (unspec_volatile:SI
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236 [(match_operand:BWD 2 "memory_operand" "+Q")
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237 (match_operand:BWD 3 "nonmemory_operand" "ri")]
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238 CRIS_UNSPEC_ATOMIC_SWAP_BOOL))
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239 (set (match_operand:BWD 1 "register_operand" "=&r") (match_dup 2))
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240 (set (match_dup 2)
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241 (unspec_volatile:BWD
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242 [(match_dup 2)
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243 (match_dup 3)
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244 (match_operand:BWD 4 "register_operand" "r")]
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245 CRIS_UNSPEC_ATOMIC_SWAP_MEM))]
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246 "<MODE>mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS"
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247 {
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248 if (TARGET_V32)
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249 return
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250 "\n.Lsync.repeat.%=:\;"
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251 "clearf p\;"
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252 "move<m> %2,%1\;"
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253 "cmp<qm3> %3,%1\;"
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254 "bne .Lsync.after.%=\;"
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255 "ax\;"
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256
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257 "move<m> %4,%2\;"
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258 "bcs .Lsync.repeat.%=\n"
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259 ".Lsync.after.%=:\;"
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260 "seq %0";
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261 else if (cris_cpu_version == 10)
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262 return
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263 "\n.Lsync.repeat.%=:\;"
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264 "clearf\;"
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265 "move<m> %2,%1\;"
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266 "cmp<qm3> %3,%1\;"
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267 "bne .Lsync.after.%=\;"
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268 "ax\;"
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269
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270 "move<m> %4,%2\;"
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271 "bwf .Lsync.repeat.%=\n"
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272 ".Lsync.after.%=:\;"
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273 "seq %0";
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274 else
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275 {
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276 /* This one is for CRIS versions without load-locked-store-conditional
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277 machinery; assume single-core-non-shared-memory without user
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278 mode/supervisor mode distinction, and just disable interrupts
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279 while performing the operation.
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280 Rather than making this pattern more complex by freeing another
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281 register or stack position to save condition codes (the value
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282 of the interrupt-enabled bit), we check whether interrupts were
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283 enabled before we disabled them and branch to a version
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284 with/without afterwards re-enabling them. */
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285 rtx ops[4];
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286
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287 /* We have no available macro to stringify CRIS_CCR_INTERRUPT_BIT. */
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288 memcpy (ops, operands, sizeof(ops));
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289 ops[3] = GEN_INT (CRIS_CCR_INTERRUPT_BIT);
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290
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291 output_asm_insn ("move $ccr,%0\;"
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292 "di\;"
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293 "move<m> %2,%1\;"
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294 "btstq %3,%0",
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295 ops);
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296 return
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297 "bmi .Lsync.irqon.%=\;"
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298 "nop\;"
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299
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300 "cmp<qm3> %3,%1\;"
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301 "bne .Lsync.after.%=\;"
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302 "seq %0\;"
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303 "ba .Lsync.after.%=\;"
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304 "move<m> %4,%2\n"
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305
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306 ".Lsync.irqon.%=:\;"
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307 "cmp<qm3> %3,%1\;"
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308 "bne .Lsync.after.%=\;"
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309 "seq %0\;"
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310 "move<m> %4,%2\;"
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311 "ei\n"
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312 ".Lsync.after.%=:";
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313 }
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314 })
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