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111
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1 ;; Scheduling for Haswell and derived processors.
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2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>. */
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19
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20 ;; The scheduling description in this file is based on core2.md.
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21 ;; The major difference from the CORE2 pipeline is that HASWELL has
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22 ;; two MU for load and one MU for store.
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23 (define_automaton "haswell_decoder,haswell_core,haswell_idiv,haswell_fdiv,haswell_ssediv,haswell_load,haswell_store")
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24
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25 ;; The CPU domain, used for HASWELL bypass latencies
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26 (define_attr "hsw_domain" "int,float,simd"
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27 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
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28 (const_string "float")
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29 (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
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30 sse,ssemov,sseadd,sseadd1,ssemul,ssecmp,ssecomi,ssecvt,
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31 ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg")
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32 (cond [(eq_attr "mode" "V4DF,V8SF,V2DF,V4SF,SF,DF")
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33 (const_string "float")
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34 (eq_attr "mode" "SI")
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35 (const_string "int")]
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36 (const_string "simd"))
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37 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
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38 (const_string "simd")]
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39 (const_string "int")))
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40
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41 (define_cpu_unit "hsw_decoder0" "haswell_decoder")
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42 (define_cpu_unit "hsw_decoder1" "haswell_decoder")
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43 (define_cpu_unit "hsw_decoder2" "haswell_decoder")
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44 (define_cpu_unit "hsw_decoder3" "haswell_decoder")
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45
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46 ;; We first wish to find an instruction for hsw_decoder0, so exclude
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47 ;; other hsw_decoders from being reserved until hsw_decoder0 is
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48 ;; reserved.
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49 (presence_set "hsw_decoder1" "hsw_decoder0")
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50 (presence_set "hsw_decoder2" "hsw_decoder0")
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51 (presence_set "hsw_decoder3" "hsw_decoder0")
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52
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53 ;; Most instructions can be decoded on any of the three decoders.
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54 (define_reservation "hsw_decodern" "(hsw_decoder0|hsw_decoder1|hsw_decoder2|hsw_decoder3)")
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55
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56 ;; The out-of-order core has eight pipelines. These are similar to the
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57 ;; Pentium Pro's five pipelines. Port 2,3 are responsible for memory loads,
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58 ;; port 7 for store address calculations, port 4 for memory stores, and
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59 ;; ports 0, 1, 5 and 6 for everything else.
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60
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61 (define_cpu_unit "hsw_p0,hsw_p1,hsw_p5,hsw_p6" "haswell_core")
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62 (define_cpu_unit "hsw_p2,hsw_p3" "haswell_load")
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63 (define_cpu_unit "hsw_p4,hsw_p7" "haswell_store")
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64 (define_cpu_unit "hsw_idiv" "haswell_idiv")
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65 (define_cpu_unit "hsw_fdiv" "haswell_fdiv")
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66 (define_cpu_unit "hsw_ssediv" "haswell_ssediv")
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67
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68 (define_reservation "hsw_p0156" "hsw_p0|hsw_p1|hsw_p5|hsw_p6")
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69 (define_reservation "hsw_p0p1p5p6" "hsw_p0+hsw_p1+hsw_p5+hsw_p6")
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70 (define_reservation "hsw_p23" "hsw_p2|hsw_p3")
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71 (define_reservation "hsw_p4p7" "hsw_p4+hsw_p7")
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72 (define_reservation "hsw_p237" "hsw_p2|hsw_p3|hsw_p7")
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73 (define_reservation "hsw_p015" "hsw_p0|hsw_p1|hsw_p5")
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74 (define_reservation "hsw_p01" "hsw_p0|hsw_p1")
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75
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76 (define_insn_reservation "hsw_complex_insn" 6
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77 (and (eq_attr "cpu" "haswell")
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78 (eq_attr "type" "other,multi,str"))
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79 "hsw_decoder0")
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80
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81 (define_insn_reservation "hsw_call" 1
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82 (and (eq_attr "cpu" "haswell")
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83 (eq_attr "type" "call,callv"))
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84 "hsw_decoder0")
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85
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86 ;; imov with memory operands does not use the integer units.
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87 ;; imovx always decodes to one uop, and also doesn't use the integer
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88 ;; units if it has memory operands.
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89 (define_insn_reservation "hsw_imov" 1
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90 (and (eq_attr "cpu" "haswell")
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91 (and (eq_attr "memory" "none")
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92 (eq_attr "type" "imov,imovx")))
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93 "hsw_decodern,hsw_p0156")
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94
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95 (define_insn_reservation "hsw_imov_load" 2
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96 (and (eq_attr "cpu" "haswell")
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97 (and (eq_attr "memory" "load")
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98 (eq_attr "type" "imov,imovx")))
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99 "hsw_decodern,hsw_p23")
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100
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101 (define_insn_reservation "hsw_imov_store" 3
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102 (and (eq_attr "cpu" "haswell")
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103 (and (eq_attr "memory" "store")
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104 (eq_attr "type" "imov")))
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105 "hsw_decodern,hsw_p4+(hsw_p2|hsw_p3|hsw_p7)")
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106
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107 (define_insn_reservation "hsw_icmov" 2
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108 (and (eq_attr "cpu" "haswell")
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109 (and (eq_attr "memory" "none")
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110 (eq_attr "type" "icmov")))
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111 "hsw_decodern,hsw_p0156,hsw_p0156")
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112
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113 (define_insn_reservation "hsw_icmov_load" 2
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114 (and (eq_attr "cpu" "haswell")
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115 (and (eq_attr "memory" "load")
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116 (eq_attr "type" "icmov")))
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117 "hsw_decodern,hsw_p23+hsw_p0156,hsw_p0156")
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118
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119 (define_insn_reservation "hsw_push_reg" 3
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120 (and (eq_attr "cpu" "haswell")
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121 (and (eq_attr "memory" "store")
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122 (eq_attr "type" "push")))
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123 "hsw_decodern,hsw_p4+hsw_p237")
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124
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125 (define_insn_reservation "hsw_push_mem" 3
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126 (and (eq_attr "cpu" "haswell")
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127 (and (eq_attr "memory" "both")
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128 (eq_attr "type" "push")))
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129 "hsw_decodern,hsw_p4+hsw_p237,hsw_p237")
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130
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131 ;; Consider lea latency as having 2 components.
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132 (define_insn_reservation "hsw_lea" 1
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133 (and (eq_attr "cpu" "haswell")
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134 (and (eq_attr "memory" "none")
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135 (eq_attr "type" "lea")))
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136 "hsw_decodern,hsw_p1|hsw_p5")
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137
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138 (define_insn_reservation "hsw_shift_rotate" 1
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139 (and (eq_attr "cpu" "haswell")
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140 (and (eq_attr "memory" "none")
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141 (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
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142 "hsw_decodern,hsw_p0|hsw_p6")
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143
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144 (define_insn_reservation "hsw_shift_rotate_mem" 1
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145 (and (eq_attr "cpu" "haswell")
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146 (and (eq_attr "memory" "!none")
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147 (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
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148 "hsw_decodern,(hsw_p0|hsw_p6)+hsw_p237+hsw_p4")
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149
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150 (define_insn_reservation "hsw_branch" 1
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151 (and (eq_attr "cpu" "haswell")
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152 (and (eq_attr "memory" "none")
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153 (eq_attr "type" "ibr")))
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154 "hsw_decodern,hsw_p6")
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155
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156 (define_insn_reservation "hsw_indirect_branch" 2
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157 (and (eq_attr "cpu" "haswell")
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158 (and (eq_attr "memory" "!none")
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159 (eq_attr "type" "ibr")))
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160 "hsw_decoder0,hsw_p23+hsw_p6")
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161
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162 (define_insn_reservation "hsw_leave" 4
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163 (and (eq_attr "cpu" "haswell")
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164 (eq_attr "type" "leave"))
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165 "hsw_decoder0,hsw_p23+hsw_p0156,hsw_p0156")
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166
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167 ;; imul and imulx with two/three operands only execute on port 1.
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168 (define_insn_reservation "hsw_imul" 3
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169 (and (eq_attr "cpu" "haswell")
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170 (and (eq_attr "memory" "none")
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171 (eq_attr "type" "imul")))
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172 "hsw_decodern,hsw_p1")
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173
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174 (define_insn_reservation "hsw_imul_mem" 3
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175 (and (eq_attr "cpu" "haswell")
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176 (and (eq_attr "memory" "!none")
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177 (eq_attr "type" "imul")))
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178 "hsw_decodern,hsw_p23+hsw_p1")
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179
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180 (define_insn_reservation "hsw_imulx" 4
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181 (and (eq_attr "cpu" "haswell")
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182 (and (eq_attr "memory" "none")
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183 (eq_attr "type" "imulx")))
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184 "hsw_decodern,hsw_p0156,hsw_p0156")
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185
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186 (define_insn_reservation "hsw_imulx_mem" 4
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187 (and (eq_attr "cpu" "haswell")
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188 (and (eq_attr "memory" "!none")
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189 (eq_attr "type" "imulx")))
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190 "hsw_decodern,hsw_p23+hsw_p0156,(hsw_p0|hsw_p6|hsw_p6)")
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191
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192
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193 ;; div and idiv are very similar, so we model them the same.
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194 ;; Use the same latency for all QI,HI and SI modes.
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195 (define_insn_reservation "hsw_idiv" 23
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196 (and (eq_attr "cpu" "haswell")
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197 (and (eq_attr "memory" "none")
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198 (eq_attr "type" "idiv")))
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199 "hsw_decoder0,(hsw_p0p1p5p6+hsw_idiv)*9")
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200
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201 (define_insn_reservation "hsw_idiv_load" 23
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202 (and (eq_attr "cpu" "haswell")
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203 (and (eq_attr "memory" "load")
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204 (eq_attr "type" "idiv")))
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205 "hsw_decoder0,hsw_p23+hsw_p0+hsw_idiv,(hsw_p0p1p5p6+hsw_idiv)*9")
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206
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207 ;; x87 floating point operations.
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208
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209 (define_insn_reservation "hsw_fxch" 0
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210 (and (eq_attr "cpu" "haswell")
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211 (eq_attr "type" "fxch"))
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212 "hsw_decodern")
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213
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214 (define_insn_reservation "hsw_fop" 3
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215 (and (eq_attr "cpu" "haswell")
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216 (and (eq_attr "memory" "none,unknown")
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217 (eq_attr "type" "fop")))
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218 "hsw_decodern,hsw_p1")
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219
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220 (define_insn_reservation "hsw_fop_load" 5
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221 (and (eq_attr "cpu" "haswell")
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222 (and (eq_attr "memory" "load")
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223 (eq_attr "type" "fop")))
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224 "hsw_decodern,hsw_p23+hsw_p1,hsw_p1")
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225
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226 (define_insn_reservation "hsw_fop_store" 3
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227 (and (eq_attr "cpu" "haswell")
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228 (and (eq_attr "memory" "store")
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229 (eq_attr "type" "fop")))
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230 "hsw_decodern,hsw_p0,hsw_p0,hsw_p0+hsw_p4+hsw_p3")
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231
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232 (define_insn_reservation "hsw_fop_both" 5
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233 (and (eq_attr "cpu" "haswell")
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234 (and (eq_attr "memory" "both")
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235 (eq_attr "type" "fop")))
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236 "hsw_decodern,hsw_p2+hsw_p0,hsw_p0+hsw_p4+hsw_p3")
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237
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238 (define_insn_reservation "hsw_fsgn" 1
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239 (and (eq_attr "cpu" "haswell")
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240 (eq_attr "type" "fsgn"))
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241 "hsw_decodern,hsw_p0")
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242
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243 (define_insn_reservation "hsw_fistp" 7
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244 (and (eq_attr "cpu" "haswell")
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245 (eq_attr "type" "fistp"))
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246 "hsw_decoder0,hsw_p1+hsw_p4+hsw_p23")
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247
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248 (define_insn_reservation "hsw_fcmov" 2
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249 (and (eq_attr "cpu" "haswell")
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250 (eq_attr "type" "fcmov"))
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251 "hsw_decoder0,hsw_p0+hsw_p5,hsw_p0")
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252
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253 (define_insn_reservation "hsw_fcmp" 1
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254 (and (eq_attr "cpu" "haswell")
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255 (and (eq_attr "memory" "none")
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256 (eq_attr "type" "fcmp")))
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257 "hsw_decodern,hsw_p1")
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258
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259 (define_insn_reservation "hsw_fcmp_load" 1
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260 (and (eq_attr "cpu" "haswell")
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261 (and (eq_attr "memory" "load")
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262 (eq_attr "type" "fcmp")))
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263 "hsw_decodern,hsw_p23+hsw_p1")
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264
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265 (define_insn_reservation "hsw_fmov" 1
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266 (and (eq_attr "cpu" "haswell")
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267 (and (eq_attr "memory" "none")
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268 (eq_attr "type" "fmov")))
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269 "hsw_decodern,hsw_p01")
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270
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271 (define_insn_reservation "hsw_fmov_load" 3
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272 (and (eq_attr "cpu" "haswell")
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273 (and (eq_attr "memory" "load")
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274 (and (eq_attr "mode" "!XF")
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275 (eq_attr "type" "fmov"))))
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276 "hsw_decodern,hsw_p23")
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277
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278 (define_insn_reservation "hsw_fmov_XF_load" 3
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279 (and (eq_attr "cpu" "haswell")
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280 (and (eq_attr "memory" "load")
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281 (and (eq_attr "mode" "XF")
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282 (eq_attr "type" "fmov"))))
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283 "hsw_decodern,(hsw_p23+hsw_p0)*2")
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284
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285 (define_insn_reservation "hsw_fmov_store" 1
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286 (and (eq_attr "cpu" "haswell")
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287 (and (eq_attr "memory" "store")
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288 (and (eq_attr "mode" "!XF")
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289 (eq_attr "type" "fmov"))))
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290 "hsw_decodern,hsw_p4p7")
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291
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292 (define_insn_reservation "hsw_fmov_XF_store" 3
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293 (and (eq_attr "cpu" "haswell")
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294 (and (eq_attr "memory" "store")
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295 (and (eq_attr "mode" "XF")
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296 (eq_attr "type" "fmov"))))
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297 "hsw_decodern,hsw_p4p7,hsw_p4p7")
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298
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299 (define_insn_reservation "hsw_fmul" 4
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300 (and (eq_attr "cpu" "haswell")
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301 (and (eq_attr "memory" "none")
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302 (eq_attr "type" "fmul")))
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303 "hsw_decodern,hsw_p01")
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304
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305 (define_insn_reservation "hsw_fmul_load" 4
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306 (and (eq_attr "cpu" "haswell")
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307 (and (eq_attr "memory" "load")
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308 (eq_attr "type" "fmul")))
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309 "hsw_decodern,hsw_p23+hsw_p01")
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310
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311 ;; fdiv latencies depend on the mode of the operands. XFmode gives
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312 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18.
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313 ;; Division by a power of 2 takes only 9 cycles, but we cannot model
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314 ;; that. Throughput is equal to latency - 1, which we model using the
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315 ;; hsw_div automaton.
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316 (define_insn_reservation "hsw_fdiv_SF" 18
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317 (and (eq_attr "cpu" "haswell")
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318 (and (eq_attr "memory" "none")
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319 (and (eq_attr "mode" "SF")
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320 (eq_attr "type" "fdiv,fpspc"))))
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321 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*16")
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322
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323 (define_insn_reservation "hsw_fdiv_SF_load" 19
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324 (and (eq_attr "cpu" "haswell")
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325 (and (eq_attr "memory" "load")
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326 (and (eq_attr "mode" "SF")
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327 (eq_attr "type" "fdiv,fpspc"))))
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328 "hsw_decodern,hsw_p23+hsw_p0+hsw_fdiv,hsw_fdiv*16")
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329
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330 (define_insn_reservation "hsw_fdiv_DF" 32
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331 (and (eq_attr "cpu" "haswell")
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332 (and (eq_attr "memory" "none")
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333 (and (eq_attr "mode" "DF")
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334 (eq_attr "type" "fdiv,fpspc"))))
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335 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*30")
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336
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337 (define_insn_reservation "hsw_fdiv_DF_load" 33
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338 (and (eq_attr "cpu" "haswell")
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339 (and (eq_attr "memory" "load")
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340 (and (eq_attr "mode" "DF")
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341 (eq_attr "type" "fdiv,fpspc"))))
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342 "hsw_decodern,hsw_p23+hsw_p0+hsw_fdiv,hsw_fdiv*30")
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343
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344 (define_insn_reservation "hsw_fdiv_XF" 38
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345 (and (eq_attr "cpu" "haswell")
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346 (and (eq_attr "memory" "none")
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347 (and (eq_attr "mode" "XF")
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348 (eq_attr "type" "fdiv,fpspc"))))
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349 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*36")
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350
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351 (define_insn_reservation "hsw_fdiv_XF_load" 39
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352 (and (eq_attr "cpu" "haswell")
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353 (and (eq_attr "memory" "load")
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354 (and (eq_attr "mode" "XF")
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355 (eq_attr "type" "fdiv,fpspc"))))
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356 "hsw_decodern,hsw_p2+hsw_p0+hsw_fdiv,hsw_fdiv*36")
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357
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358 ;; MMX instructions.
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359
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360 (define_insn_reservation "hsw_mmx_add" 1
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361 (and (eq_attr "cpu" "haswell")
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362 (and (eq_attr "memory" "none")
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363 (eq_attr "type" "mmxadd,sseiadd")))
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364 "hsw_decodern,hsw_p1|hsw_p5")
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365
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366 (define_insn_reservation "hsw_mmx_add_load" 2
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367 (and (eq_attr "cpu" "haswell")
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368 (and (eq_attr "memory" "load")
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369 (eq_attr "type" "mmxadd,sseiadd")))
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370 "hsw_decodern,hsw_p23+(hsw_p1|hsw_p5)")
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371
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372 (define_insn_reservation "hsw_mmx_shft" 1
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373 (and (eq_attr "cpu" "haswell")
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374 (and (eq_attr "memory" "none")
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375 (eq_attr "type" "mmxshft")))
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376 "hsw_decodern,hsw_p0")
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377
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378 (define_insn_reservation "hsw_mmx_shft_load" 2
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379 (and (eq_attr "cpu" "haswell")
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380 (and (eq_attr "memory" "load")
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381 (eq_attr "type" "mmxshft")))
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382 "hsw_decodern,hsw_p23+hsw_p0")
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383
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384 (define_insn_reservation "hsw_mmx_sse_shft" 1
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385 (and (eq_attr "cpu" "haswell")
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386 (and (eq_attr "memory" "none")
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387 (and (eq_attr "type" "sseishft")
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388 (eq_attr "length_immediate" "!0"))))
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389 "hsw_decodern,hsw_p01")
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390
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391 (define_insn_reservation "hsw_mmx_sse_shft_load" 2
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392 (and (eq_attr "cpu" "haswell")
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393 (and (eq_attr "memory" "load")
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394 (and (eq_attr "type" "sseishft")
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|
395 (eq_attr "length_immediate" "!0"))))
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|
396 "hsw_decodern,hsw_p01+hsw_p23")
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397
|
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|
398 (define_insn_reservation "hsw_mmx_sse_shft1" 2
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|
399 (and (eq_attr "cpu" "haswell")
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400 (and (eq_attr "memory" "none")
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|
|
401 (and (eq_attr "type" "sseishft")
|
|
|
402 (eq_attr "length_immediate" "0"))))
|
|
|
403 "hsw_decodern,hsw_p01")
|
|
|
404
|
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|
405 (define_insn_reservation "hsw_mmx_sse_shft1_load" 3
|
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|
406 (and (eq_attr "cpu" "haswell")
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|
|
407 (and (eq_attr "memory" "load")
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|
408 (and (eq_attr "type" "sseishft")
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|
|
409 (eq_attr "length_immediate" "0"))))
|
|
|
410 "hsw_decodern,hsw_p01+hsw_p23")
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|
|
411
|
|
|
412 (define_insn_reservation "hsw_mmx_mul" 5
|
|
|
413 (and (eq_attr "cpu" "haswell")
|
|
|
414 (and (eq_attr "memory" "none")
|
|
|
415 (eq_attr "type" "mmxmul,sseimul")))
|
|
|
416 "hsw_decodern,hsw_p01")
|
|
|
417
|
|
|
418 (define_insn_reservation "hsw_mmx_mul_load" 5
|
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|
419 (and (eq_attr "cpu" "haswell")
|
|
|
420 (and (eq_attr "memory" "none")
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|
|
421 (eq_attr "type" "mmxmul,sseimul")))
|
|
|
422 "hsw_decodern,hsw_p23+hsw_p01")
|
|
|
423
|
|
|
424 (define_insn_reservation "hsw_sse_mmxcvt" 4
|
|
|
425 (and (eq_attr "cpu" "haswell")
|
|
|
426 (and (eq_attr "mode" "DI")
|
|
|
427 (eq_attr "type" "mmxcvt")))
|
|
|
428 "hsw_decodern,hsw_p1")
|
|
|
429
|
|
|
430 ;; (define_insn_reservation "hsw_sse_mmxshft" 2
|
|
|
431 ;; (and (eq_attr "cpu" "haswell")
|
|
|
432 ;; (and (eq_attr "mode" "TI")
|
|
|
433 ;; (eq_attr "type" "mmxshft")))
|
|
|
434 ;; "hsw_decodern,hsw_p01")
|
|
|
435
|
|
|
436 ;; The sfence instruction.
|
|
|
437 (define_insn_reservation "hsw_sse_sfence" 2
|
|
|
438 (and (eq_attr "cpu" "haswell")
|
|
|
439 (and (eq_attr "memory" "unknown")
|
|
|
440 (eq_attr "type" "sse")))
|
|
|
441 "hsw_decoder0,hsw_p23+hsw_p4")
|
|
|
442
|
|
|
443 (define_insn_reservation "hsw_sse_SFDF" 3
|
|
|
444 (and (eq_attr "cpu" "haswell")
|
|
|
445 (and (eq_attr "mode" "SF,DF")
|
|
|
446 (eq_attr "type" "sse")))
|
|
|
447 "hsw_decodern,hsw_p01")
|
|
|
448
|
|
|
449 (define_insn_reservation "hsw_sse_V4SF" 4
|
|
|
450 (and (eq_attr "cpu" "haswell")
|
|
|
451 (and (eq_attr "mode" "V4SF")
|
|
|
452 (eq_attr "type" "sse")))
|
|
|
453 "hsw_decodern,hsw_p01")
|
|
|
454
|
|
|
455 (define_insn_reservation "hsw_sse_V8SF" 4
|
|
|
456 (and (eq_attr "cpu" "haswell")
|
|
|
457 (and (eq_attr "mode" "V8SF,V4DF")
|
|
|
458 (eq_attr "type" "sse")))
|
|
|
459 "hsw_decodern,hsw_p01")
|
|
|
460
|
|
|
461 (define_insn_reservation "hsw_sse_addcmp" 3
|
|
|
462 (and (eq_attr "cpu" "haswell")
|
|
|
463 (and (eq_attr "memory" "none")
|
|
|
464 (eq_attr "type" "sseadd1,ssecmp,ssecomi")))
|
|
|
465 "hsw_decodern,hsw_p01")
|
|
|
466
|
|
|
467 (define_insn_reservation "hsw_sse_addcmp_load" 3
|
|
|
468 (and (eq_attr "cpu" "haswell")
|
|
|
469 (and (eq_attr "memory" "load")
|
|
|
470 (eq_attr "type" "sseadd1,ssecmp,ssecomi")))
|
|
|
471 "hsw_decodern,hsw_p23+hsw_p01")
|
|
|
472
|
|
|
473 (define_insn_reservation "hsw_sse_logic" 1
|
|
|
474 (and (eq_attr "cpu" "haswell")
|
|
|
475 (and (eq_attr "memory" "none")
|
|
|
476 (eq_attr "type" "sselog,sselog1")))
|
|
|
477 "hsw_decodern,hsw_p015")
|
|
|
478
|
|
|
479 (define_insn_reservation "hsw_sse_logic_load" 2
|
|
|
480 (and (eq_attr "cpu" "haswell")
|
|
|
481 (and (eq_attr "memory" "load")
|
|
|
482 (eq_attr "type" "sselog,sselog1")))
|
|
|
483 "hsw_decodern,hsw_p015+hsw_p23")
|
|
|
484
|
|
|
485 (define_insn_reservation "hsw_sse_add" 3
|
|
|
486 (and (eq_attr "cpu" "haswell")
|
|
|
487 (and (eq_attr "memory" "none")
|
|
|
488 (eq_attr "type" "sseadd")))
|
|
|
489 "hsw_decodern,hsw_p1|hsw_p5")
|
|
|
490
|
|
|
491 (define_insn_reservation "hsw_sse_add_load" 3
|
|
|
492 (and (eq_attr "cpu" "haswell")
|
|
|
493 (and (eq_attr "memory" "load")
|
|
|
494 (eq_attr "type" "sseadd")))
|
|
|
495 "hsw_decodern,(hsw_p1|hsw_p5)+hsw_p23")
|
|
|
496
|
|
|
497 (define_insn_reservation "hsw_sse_mul" 5
|
|
|
498 (and (eq_attr "cpu" "haswell")
|
|
|
499 (and (eq_attr "memory" "none")
|
|
|
500 (eq_attr "type" "ssemul")))
|
|
|
501 "hsw_decodern,hsw_p0")
|
|
|
502
|
|
|
503 (define_insn_reservation "hsw_sse_mul_load" 5
|
|
|
504 (and (eq_attr "cpu" "haswell")
|
|
|
505 (and (eq_attr "memory" "load")
|
|
|
506 (eq_attr "type" "ssemul")))
|
|
|
507 "hsw_decodern,hsw_p0+hsw_p23")
|
|
|
508 ;; Use skylake pipeline.
|
|
|
509 (define_insn_reservation "hsw_sse_muladd" 5
|
|
|
510 (and (eq_attr "cpu" "haswell")
|
|
|
511 (and (eq_attr "memory" "none")
|
|
|
512 (eq_attr "type" "ssemuladd")))
|
|
|
513 "hsw_decodern,hsw_p01")
|
|
|
514
|
|
|
515 (define_insn_reservation "hsw_sse_muladd_load" 5
|
|
|
516 (and (eq_attr "cpu" "haswell")
|
|
|
517 (and (eq_attr "memory" "load")
|
|
|
518 (eq_attr "type" "ssemuladd")))
|
|
|
519 "hsw_decodern,hsw_p01+hsw_p23")
|
|
|
520
|
|
|
521 (define_insn_reservation "hsw_sse_div_SF" 18
|
|
|
522 (and (eq_attr "cpu" "haswell")
|
|
|
523 (and (eq_attr "memory" "none")
|
|
|
524 (and (eq_attr "mode" "SF,V4SF,V8SF")
|
|
|
525 (eq_attr "type" "ssediv"))))
|
|
|
526 "hsw_decodern,hsw_p0,hsw_ssediv*14")
|
|
|
527
|
|
|
528 (define_insn_reservation "hsw_sse_div_SF_load" 18
|
|
|
529 (and (eq_attr "cpu" "haswell")
|
|
|
530 (and (eq_attr "memory" "none")
|
|
|
531 (and (eq_attr "mode" "SF,V4SF,V8SF")
|
|
|
532 (eq_attr "type" "ssediv"))))
|
|
|
533 "hsw_decodern,(hsw_p23+hsw_p0),hsw_ssediv*14")
|
|
|
534
|
|
|
535 (define_insn_reservation "hsw_sse_div_DF" 28
|
|
|
536 (and (eq_attr "cpu" "haswell")
|
|
|
537 (and (eq_attr "memory" "none")
|
|
|
538 (and (eq_attr "mode" "DF,V2DF,V4DF")
|
|
|
539 (eq_attr "type" "ssediv"))))
|
|
|
540 "hsw_decodern,hsw_p0,hsw_ssediv*20")
|
|
|
541
|
|
|
542 (define_insn_reservation "hsw_sse_div_DF_load" 28
|
|
|
543 (and (eq_attr "cpu" "haswell")
|
|
|
544 (and (eq_attr "memory" "none")
|
|
|
545 (and (eq_attr "mode" "DF,V2DF,V4DF")
|
|
|
546 (eq_attr "type" "ssediv"))))
|
|
|
547 "hsw_decodern,(hsw_p23+hsw_p0),hsw_ssediv*20")
|
|
|
548
|
|
|
549 (define_insn_reservation "hsw_sse_icvt" 4
|
|
|
550 (and (eq_attr "cpu" "haswell")
|
|
|
551 (and (eq_attr "memory" "none")
|
|
|
552 (eq_attr "type" "sseicvt")))
|
|
|
553 "hsw_decodern,hsw_p1")
|
|
|
554
|
|
|
555 (define_insn_reservation "hsw_sse_icvt_load" 4
|
|
|
556 (and (eq_attr "cpu" "haswell")
|
|
|
557 (and (eq_attr "memory" "!none")
|
|
|
558 (eq_attr "type" "sseicvt")))
|
|
|
559 "hsw_decodern,hsw_p23+hsw_p1")
|
|
|
560
|
|
|
561
|
|
|
562 (define_insn_reservation "hsw_sse_icvt_SI" 3
|
|
|
563 (and (eq_attr "cpu" "haswell")
|
|
|
564 (and (eq_attr "memory" "none")
|
|
|
565 (and (eq_attr "mode" "SI")
|
|
|
566 (eq_attr "type" "sseicvt"))))
|
|
|
567 "hsw_decodern,hsw_p1")
|
|
|
568
|
|
|
569 (define_insn_reservation "hsw_sse_icvt_SI_load" 3
|
|
|
570 (and (eq_attr "cpu" "haswell")
|
|
|
571 (and (eq_attr "memory" "!none")
|
|
|
572 (and (eq_attr "mode" "SI")
|
|
|
573 (eq_attr "type" "sseicvt"))))
|
|
|
574 "hsw_decodern,hsw_p23+hsw_p1")
|
|
|
575
|
|
|
576 (define_insn_reservation "hsw_sse_mov" 1
|
|
|
577 (and (eq_attr "cpu" "haswell")
|
|
|
578 (and (eq_attr "memory" "none")
|
|
|
579 (eq_attr "type" "ssemov")))
|
|
|
580 "hsw_decodern,hsw_p015")
|
|
|
581
|
|
|
582 (define_insn_reservation "hsw_sse_mov_load" 2
|
|
|
583 (and (eq_attr "cpu" "haswell")
|
|
|
584 (and (eq_attr "memory" "load")
|
|
|
585 (eq_attr "type" "ssemov")))
|
|
|
586 "hsw_decodern,hsw_p23")
|
|
|
587
|
|
|
588 (define_insn_reservation "hsw_sse_mov_store" 1
|
|
|
589 (and (eq_attr "cpu" "haswell")
|
|
|
590 (and (eq_attr "memory" "store")
|
|
|
591 (eq_attr "type" "ssemov")))
|
|
|
592 "hsw_decodern,hsw_p4p7")
|
|
|
593
|
|
|
594 (define_insn_reservation "hsw_insn" 1
|
|
|
595 (and (eq_attr "cpu" "haswell")
|
|
|
596 (and (eq_attr "memory" "none,unknown")
|
|
|
597 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
|
|
|
598 "hsw_decodern,hsw_p0156")
|
|
|
599
|
|
|
600 (define_insn_reservation "hsw_insn_load" 1
|
|
|
601 (and (eq_attr "cpu" "haswell")
|
|
|
602 (and (eq_attr "memory" "load")
|
|
|
603 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
|
|
|
604 "hsw_decodern,hsw_p23+hsw_p0156")
|
|
|
605
|
|
|
606 (define_insn_reservation "hsw_insn_store" 1
|
|
|
607 (and (eq_attr "cpu" "haswell")
|
|
|
608 (and (eq_attr "memory" "store")
|
|
|
609 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
|
|
|
610 "hsw_decodern,hsw_p0156+hsw_p4p7")
|
|
|
611
|
|
|
612 ;; read-modify-store instructions produce 4 uops so they have to be
|
|
|
613 ;; decoded on hsw_decoder0 as well.
|
|
|
614 (define_insn_reservation "hsw_insn_both" 4
|
|
|
615 (and (eq_attr "cpu" "haswell")
|
|
|
616 (and (eq_attr "memory" "both")
|
|
|
617 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
|
|
|
618 "hsw_decodern,hsw_p23+hsw_p0156+hsw_p4p7")
|
