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111
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1 /* Scheduler hooks for IA-32 which implement atom+ specific logic.
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2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
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3
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4 This file is part of GCC.
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5
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6 GCC is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 3, or (at your option)
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9 any later version.
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10
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11 GCC is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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15
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16 You should have received a copy of the GNU General Public License
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17 along with GCC; see the file COPYING3. If not see
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18 <http://www.gnu.org/licenses/>. */
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19
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20 #include "config.h"
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21 #include "system.h"
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22 #include "coretypes.h"
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23 #include "backend.h"
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24 #include "rtl.h"
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25 #include "tree.h"
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26 #include "cfghooks.h"
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27 #include "tm_p.h"
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28 #include "insn-config.h"
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29 #include "insn-attr.h"
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30 #include "recog.h"
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31 #include "target.h"
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32 #include "rtl-iter.h"
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33 #include "regset.h"
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34 #include "sched-int.h"
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35
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36 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
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37 execution. It is applied if
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38 (1) IMUL instruction is on the top of list;
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39 (2) There exists the only producer of independent IMUL instruction in
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40 ready list.
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41 Return index of IMUL producer if it was found and -1 otherwise. */
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42 static int
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43 do_reorder_for_imul (rtx_insn **ready, int n_ready)
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44 {
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45 rtx_insn *insn;
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46 rtx set, insn1, insn2;
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47 sd_iterator_def sd_it;
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48 dep_t dep;
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49 int index = -1;
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50 int i;
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51
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52 if (!TARGET_BONNELL)
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53 return index;
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54
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55 /* Check that IMUL instruction is on the top of ready list. */
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56 insn = ready[n_ready - 1];
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57 set = single_set (insn);
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58 if (!set)
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59 return index;
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60 if (!(GET_CODE (SET_SRC (set)) == MULT
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61 && GET_MODE (SET_SRC (set)) == SImode))
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62 return index;
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63
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64 /* Search for producer of independent IMUL instruction. */
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65 for (i = n_ready - 2; i >= 0; i--)
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66 {
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67 insn = ready[i];
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68 if (!NONDEBUG_INSN_P (insn))
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69 continue;
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70 /* Skip IMUL instruction. */
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71 insn2 = PATTERN (insn);
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72 if (GET_CODE (insn2) == PARALLEL)
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73 insn2 = XVECEXP (insn2, 0, 0);
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74 if (GET_CODE (insn2) == SET
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75 && GET_CODE (SET_SRC (insn2)) == MULT
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76 && GET_MODE (SET_SRC (insn2)) == SImode)
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77 continue;
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78
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79 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
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80 {
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81 rtx con;
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82 con = DEP_CON (dep);
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83 if (!NONDEBUG_INSN_P (con))
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84 continue;
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85 insn1 = PATTERN (con);
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86 if (GET_CODE (insn1) == PARALLEL)
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87 insn1 = XVECEXP (insn1, 0, 0);
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88
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89 if (GET_CODE (insn1) == SET
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90 && GET_CODE (SET_SRC (insn1)) == MULT
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91 && GET_MODE (SET_SRC (insn1)) == SImode)
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92 {
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93 sd_iterator_def sd_it1;
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94 dep_t dep1;
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95 /* Check if there is no other dependee for IMUL. */
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96 index = i;
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97 FOR_EACH_DEP (con, SD_LIST_BACK, sd_it1, dep1)
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98 {
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99 rtx pro;
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100 pro = DEP_PRO (dep1);
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101 if (!NONDEBUG_INSN_P (pro))
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102 continue;
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103 if (pro != insn)
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104 index = -1;
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105 }
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106 if (index >= 0)
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107 break;
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108 }
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109 }
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110 if (index >= 0)
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111 break;
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112 }
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113 return index;
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114 }
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115
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116 /* Try to find the best candidate on the top of ready list if two insns
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117 have the same priority - candidate is best if its dependees were
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118 scheduled earlier. Applied for Silvermont only.
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119 Return true if top 2 insns must be interchanged. */
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120 static bool
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121 swap_top_of_ready_list (rtx_insn **ready, int n_ready)
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122 {
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123 rtx_insn *top = ready[n_ready - 1];
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124 rtx_insn *next = ready[n_ready - 2];
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125 rtx set;
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126 sd_iterator_def sd_it;
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127 dep_t dep;
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128 int clock1 = -1;
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129 int clock2 = -1;
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130 #define INSN_TICK(INSN) (HID (INSN)->tick)
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131
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132 if (!TARGET_SILVERMONT && !TARGET_INTEL)
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133 return false;
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134
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135 if (!NONDEBUG_INSN_P (top))
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136 return false;
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137 if (!NONJUMP_INSN_P (top))
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138 return false;
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139 if (!NONDEBUG_INSN_P (next))
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140 return false;
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141 if (!NONJUMP_INSN_P (next))
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142 return false;
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143 set = single_set (top);
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144 if (!set)
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145 return false;
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146 set = single_set (next);
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147 if (!set)
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148 return false;
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149
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150 if (INSN_PRIORITY_KNOWN (top) && INSN_PRIORITY_KNOWN (next))
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151 {
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152 if (INSN_PRIORITY (top) != INSN_PRIORITY (next))
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153 return false;
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154 /* Determine winner more precise. */
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155 FOR_EACH_DEP (top, SD_LIST_RES_BACK, sd_it, dep)
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156 {
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157 rtx pro;
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158 pro = DEP_PRO (dep);
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159 if (!NONDEBUG_INSN_P (pro))
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160 continue;
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161 if (INSN_TICK (pro) > clock1)
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162 clock1 = INSN_TICK (pro);
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163 }
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164 FOR_EACH_DEP (next, SD_LIST_RES_BACK, sd_it, dep)
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165 {
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166 rtx pro;
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167 pro = DEP_PRO (dep);
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168 if (!NONDEBUG_INSN_P (pro))
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169 continue;
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170 if (INSN_TICK (pro) > clock2)
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171 clock2 = INSN_TICK (pro);
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172 }
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173
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174 if (clock1 == clock2)
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175 {
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176 /* Determine winner - load must win. */
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177 enum attr_memory memory1, memory2;
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178 memory1 = get_attr_memory (top);
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179 memory2 = get_attr_memory (next);
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180 if (memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD)
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181 return true;
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182 }
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183 return (bool) (clock2 < clock1);
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184 }
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185 return false;
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186 #undef INSN_TICK
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187 }
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188
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189 /* Perform possible reodering of ready list for Atom/Silvermont only.
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190 Return issue rate. */
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191 int
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192 ix86_atom_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready,
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193 int *pn_ready, int clock_var)
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194 {
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195 int issue_rate = -1;
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196 int n_ready = *pn_ready;
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197 int i;
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198 rtx_insn *insn;
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199 int index = -1;
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200
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201 /* Set up issue rate. */
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202 issue_rate = ix86_issue_rate ();
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203
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204 /* Do reodering for BONNELL/SILVERMONT only. */
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205 if (!TARGET_BONNELL && !TARGET_SILVERMONT && !TARGET_INTEL)
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206 return issue_rate;
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207
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208 /* Nothing to do if ready list contains only 1 instruction. */
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209 if (n_ready <= 1)
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210 return issue_rate;
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211
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212 /* Do reodering for post-reload scheduler only. */
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213 if (!reload_completed)
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214 return issue_rate;
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215
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216 if ((index = do_reorder_for_imul (ready, n_ready)) >= 0)
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217 {
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218 if (sched_verbose > 1)
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219 fprintf (dump, ";;\tatom sched_reorder: put %d insn on top\n",
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220 INSN_UID (ready[index]));
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221
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222 /* Put IMUL producer (ready[index]) at the top of ready list. */
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223 insn = ready[index];
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224 for (i = index; i < n_ready - 1; i++)
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225 ready[i] = ready[i + 1];
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226 ready[n_ready - 1] = insn;
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227 return issue_rate;
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228 }
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229
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230 /* Skip selective scheduling since HID is not populated in it. */
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231 if (clock_var != 0
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232 && !sel_sched_p ()
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233 && swap_top_of_ready_list (ready, n_ready))
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234 {
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235 if (sched_verbose > 1)
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236 fprintf (dump, ";;\tslm sched_reorder: swap %d and %d insns\n",
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237 INSN_UID (ready[n_ready - 1]), INSN_UID (ready[n_ready - 2]));
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238 /* Swap 2 top elements of ready list. */
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239 insn = ready[n_ready - 1];
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240 ready[n_ready - 1] = ready[n_ready - 2];
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241 ready[n_ready - 2] = insn;
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242 }
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243 return issue_rate;
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244 }
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