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111
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1 /* Scheduler hooks for IA-32 which implement CPU specific logic.
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2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
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3
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4 This file is part of GCC.
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5
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6 GCC is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 3, or (at your option)
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9 any later version.
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10
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11 GCC is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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15
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16 You should have received a copy of the GNU General Public License
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17 along with GCC; see the file COPYING3. If not see
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18 <http://www.gnu.org/licenses/>. */
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19
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20 #include "config.h"
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21 #include "system.h"
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22 #include "coretypes.h"
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23 #include "backend.h"
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24 #include "rtl.h"
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25 #include "tree.h"
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26 #include "cfghooks.h"
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27 #include "tm_p.h"
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28 #include "insn-config.h"
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29 #include "insn-attr.h"
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30 #include "recog.h"
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31 #include "target.h"
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32
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33 /* Return the maximum number of instructions a cpu can issue. */
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34
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35 int
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36 ix86_issue_rate (void)
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37 {
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38 switch (ix86_tune)
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39 {
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40 case PROCESSOR_PENTIUM:
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41 case PROCESSOR_LAKEMONT:
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42 case PROCESSOR_BONNELL:
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43 case PROCESSOR_SILVERMONT:
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44 case PROCESSOR_KNL:
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45 case PROCESSOR_KNM:
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46 case PROCESSOR_INTEL:
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47 case PROCESSOR_K6:
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48 case PROCESSOR_BTVER2:
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49 case PROCESSOR_PENTIUM4:
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50 case PROCESSOR_NOCONA:
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51 return 2;
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52
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53 case PROCESSOR_PENTIUMPRO:
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54 case PROCESSOR_ATHLON:
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55 case PROCESSOR_K8:
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56 case PROCESSOR_AMDFAM10:
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57 case PROCESSOR_GENERIC:
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58 case PROCESSOR_BTVER1:
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59 return 3;
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60
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61 case PROCESSOR_BDVER1:
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62 case PROCESSOR_BDVER2:
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63 case PROCESSOR_BDVER3:
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64 case PROCESSOR_BDVER4:
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65 case PROCESSOR_ZNVER1:
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66 case PROCESSOR_CORE2:
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67 case PROCESSOR_NEHALEM:
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68 case PROCESSOR_SANDYBRIDGE:
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69 case PROCESSOR_HASWELL:
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70 return 4;
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71
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72 default:
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73 return 1;
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74 }
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75 }
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76
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77 /* Return true iff USE_INSN has a memory address with operands set by
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78 SET_INSN. */
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79
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80 bool
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81 ix86_agi_dependent (rtx_insn *set_insn, rtx_insn *use_insn)
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82 {
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83 int i;
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84 extract_insn_cached (use_insn);
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85 for (i = recog_data.n_operands - 1; i >= 0; --i)
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86 if (MEM_P (recog_data.operand[i]))
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87 {
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88 rtx addr = XEXP (recog_data.operand[i], 0);
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89 if (modified_in_p (addr, set_insn) != 0)
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90 {
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91 /* No AGI stall if SET_INSN is a push or pop and USE_INSN
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92 has SP based memory (unless index reg is modified in a pop). */
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93 rtx set = single_set (set_insn);
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94 if (set
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95 && (push_operand (SET_DEST (set), GET_MODE (SET_DEST (set)))
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96 || pop_operand (SET_SRC (set), GET_MODE (SET_SRC (set)))))
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97 {
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98 struct ix86_address parts;
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99 if (ix86_decompose_address (addr, &parts)
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100 && parts.base == stack_pointer_rtx
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101 && (parts.index == NULL_RTX
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102 || MEM_P (SET_DEST (set))
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103 || !modified_in_p (parts.index, set_insn)))
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104 return false;
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105 }
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106 return true;
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107 }
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108 return false;
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109 }
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110 return false;
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111 }
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112
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113 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
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114 by DEP_INSN and nothing set by DEP_INSN. */
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115
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116 static bool
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117 ix86_flags_dependent (rtx_insn *insn, rtx_insn *dep_insn, enum attr_type insn_type)
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118 {
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119 rtx set, set2;
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120
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121 /* Simplify the test for uninteresting insns. */
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122 if (insn_type != TYPE_SETCC
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123 && insn_type != TYPE_ICMOV
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124 && insn_type != TYPE_FCMOV
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125 && insn_type != TYPE_IBR)
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126 return false;
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127
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128 if ((set = single_set (dep_insn)) != 0)
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129 {
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130 set = SET_DEST (set);
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131 set2 = NULL_RTX;
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132 }
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133 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
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134 && XVECLEN (PATTERN (dep_insn), 0) == 2
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135 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
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136 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
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137 {
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138 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
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139 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
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140 }
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141 else
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142 return false;
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143
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144 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
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145 return false;
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146
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147 /* This test is true if the dependent insn reads the flags but
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148 not any other potentially set register. */
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149 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
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150 return false;
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151
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152 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
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153 return false;
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154
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155 return true;
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156 }
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157
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158 /* Helper function for exact_store_load_dependency.
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159 Return true if addr is found in insn. */
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160 static bool
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161 exact_dependency_1 (rtx addr, rtx insn)
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162 {
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163 enum rtx_code code;
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164 const char *format_ptr;
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165 int i, j;
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166
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167 code = GET_CODE (insn);
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168 switch (code)
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169 {
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170 case MEM:
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171 if (rtx_equal_p (addr, insn))
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172 return true;
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173 break;
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174 case REG:
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175 CASE_CONST_ANY:
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176 case SYMBOL_REF:
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177 case CODE_LABEL:
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178 case PC:
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179 case CC0:
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180 case EXPR_LIST:
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181 return false;
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182 default:
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183 break;
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184 }
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185
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186 format_ptr = GET_RTX_FORMAT (code);
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187 for (i = 0; i < GET_RTX_LENGTH (code); i++)
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188 {
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189 switch (*format_ptr++)
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190 {
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191 case 'e':
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192 if (exact_dependency_1 (addr, XEXP (insn, i)))
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193 return true;
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194 break;
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195 case 'E':
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196 for (j = 0; j < XVECLEN (insn, i); j++)
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197 if (exact_dependency_1 (addr, XVECEXP (insn, i, j)))
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198 return true;
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199 break;
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200 }
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201 }
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202 return false;
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203 }
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204
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205 /* Return true if there exists exact dependency for store & load, i.e.
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206 the same memory address is used in them. */
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207 static bool
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208 exact_store_load_dependency (rtx_insn *store, rtx_insn *load)
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209 {
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210 rtx set1, set2;
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211
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212 set1 = single_set (store);
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213 if (!set1)
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214 return false;
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215 if (!MEM_P (SET_DEST (set1)))
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216 return false;
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217 set2 = single_set (load);
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218 if (!set2)
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219 return false;
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220 if (exact_dependency_1 (SET_DEST (set1), SET_SRC (set2)))
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221 return true;
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222 return false;
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223 }
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224
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225
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226 /* This function corrects the value of COST (latency) based on the relationship
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227 between INSN and DEP_INSN through a dependence of type DEP_TYPE, and strength
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228 DW. It should return the new value.
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229
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230 On x86 CPUs this is most commonly used to model the fact that valus of
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231 registers used to compute address of memory operand needs to be ready
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232 earlier than values of registers used in the actual operation. */
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233
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234 int
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235 ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
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236 unsigned int)
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237 {
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238 enum attr_type insn_type, dep_insn_type;
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239 enum attr_memory memory;
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240 rtx set, set2;
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241 int dep_insn_code_number;
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242
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243 /* Anti and output dependencies have zero cost on all CPUs. */
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244 if (dep_type != 0)
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245 return 0;
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246
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247 dep_insn_code_number = recog_memoized (dep_insn);
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248
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249 /* If we can't recognize the insns, we can't really do anything. */
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250 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
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251 return cost;
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252
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253 insn_type = get_attr_type (insn);
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254 dep_insn_type = get_attr_type (dep_insn);
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255
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256 switch (ix86_tune)
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257 {
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258 case PROCESSOR_PENTIUM:
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259 case PROCESSOR_LAKEMONT:
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260 /* Address Generation Interlock adds a cycle of latency. */
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261 if (insn_type == TYPE_LEA)
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262 {
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263 rtx addr = PATTERN (insn);
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264
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265 if (GET_CODE (addr) == PARALLEL)
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266 addr = XVECEXP (addr, 0, 0);
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267
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268 gcc_assert (GET_CODE (addr) == SET);
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269
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270 addr = SET_SRC (addr);
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271 if (modified_in_p (addr, dep_insn))
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272 cost += 1;
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273 }
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274 else if (ix86_agi_dependent (dep_insn, insn))
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275 cost += 1;
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276
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277 /* ??? Compares pair with jump/setcc. */
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278 if (ix86_flags_dependent (insn, dep_insn, insn_type))
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279 cost = 0;
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280
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281 /* Floating point stores require value to be ready one cycle earlier. */
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282 if (insn_type == TYPE_FMOV
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283 && get_attr_memory (insn) == MEMORY_STORE
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284 && !ix86_agi_dependent (dep_insn, insn))
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285 cost += 1;
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286 break;
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287
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288 case PROCESSOR_PENTIUMPRO:
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289 /* INT->FP conversion is expensive. */
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290 if (get_attr_fp_int_src (dep_insn))
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291 cost += 5;
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292
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293 /* There is one cycle extra latency between an FP op and a store. */
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294 if (insn_type == TYPE_FMOV
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295 && (set = single_set (dep_insn)) != NULL_RTX
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296 && (set2 = single_set (insn)) != NULL_RTX
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297 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
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298 && MEM_P (SET_DEST (set2)))
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299 cost += 1;
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300
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301 memory = get_attr_memory (insn);
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302
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303 /* Show ability of reorder buffer to hide latency of load by executing
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304 in parallel with previous instruction in case
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305 previous instruction is not needed to compute the address. */
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306 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
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307 && !ix86_agi_dependent (dep_insn, insn))
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308 {
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309 /* Claim moves to take one cycle, as core can issue one load
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310 at time and the next load can start cycle later. */
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311 if (dep_insn_type == TYPE_IMOV
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312 || dep_insn_type == TYPE_FMOV)
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313 cost = 1;
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314 else if (cost > 1)
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315 cost--;
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316 }
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317 break;
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318
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319 case PROCESSOR_K6:
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320 /* The esp dependency is resolved before
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321 the instruction is really finished. */
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322 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
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323 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
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324 return 1;
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325
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326 /* INT->FP conversion is expensive. */
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327 if (get_attr_fp_int_src (dep_insn))
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328 cost += 5;
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329
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330 memory = get_attr_memory (insn);
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331
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332 /* Show ability of reorder buffer to hide latency of load by executing
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333 in parallel with previous instruction in case
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334 previous instruction is not needed to compute the address. */
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335 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
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336 && !ix86_agi_dependent (dep_insn, insn))
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337 {
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338 /* Claim moves to take one cycle, as core can issue one load
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339 at time and the next load can start cycle later. */
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340 if (dep_insn_type == TYPE_IMOV
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341 || dep_insn_type == TYPE_FMOV)
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342 cost = 1;
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343 else if (cost > 2)
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344 cost -= 2;
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345 else
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346 cost = 1;
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347 }
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348 break;
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349
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350 case PROCESSOR_AMDFAM10:
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351 case PROCESSOR_BDVER1:
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352 case PROCESSOR_BDVER2:
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353 case PROCESSOR_BDVER3:
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354 case PROCESSOR_BDVER4:
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355 case PROCESSOR_BTVER1:
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356 case PROCESSOR_BTVER2:
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357 case PROCESSOR_GENERIC:
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358 /* Stack engine allows to execute push&pop instructions in parall. */
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359 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
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360 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
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361 return 0;
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362 /* FALLTHRU */
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363
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364 case PROCESSOR_ATHLON:
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365 case PROCESSOR_K8:
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366 memory = get_attr_memory (insn);
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367
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368 /* Show ability of reorder buffer to hide latency of load by executing
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369 in parallel with previous instruction in case
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370 previous instruction is not needed to compute the address. */
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371 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
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372 && !ix86_agi_dependent (dep_insn, insn))
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373 {
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374 enum attr_unit unit = get_attr_unit (insn);
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375 int loadcost = 3;
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376
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377 /* Because of the difference between the length of integer and
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378 floating unit pipeline preparation stages, the memory operands
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379 for floating point are cheaper.
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380
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381 ??? For Athlon it the difference is most probably 2. */
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382 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
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383 loadcost = 3;
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384 else
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385 loadcost = TARGET_ATHLON ? 2 : 0;
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386
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387 if (cost >= loadcost)
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388 cost -= loadcost;
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389 else
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390 cost = 0;
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391 }
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392 break;
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393
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394 case PROCESSOR_ZNVER1:
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395 /* Stack engine allows to execute push&pop instructions in parall. */
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396 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
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397 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
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398 return 0;
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399
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400 memory = get_attr_memory (insn);
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401
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402 /* Show ability of reorder buffer to hide latency of load by executing
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403 in parallel with previous instruction in case
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404 previous instruction is not needed to compute the address. */
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405 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
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406 && !ix86_agi_dependent (dep_insn, insn))
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407 {
|
|
|
408 enum attr_unit unit = get_attr_unit (insn);
|
|
|
409 int loadcost;
|
|
|
410
|
|
|
411 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
|
|
|
412 loadcost = 4;
|
|
|
413 else
|
|
|
414 loadcost = 7;
|
|
|
415
|
|
|
416 if (cost >= loadcost)
|
|
|
417 cost -= loadcost;
|
|
|
418 else
|
|
|
419 cost = 0;
|
|
|
420 }
|
|
|
421 break;
|
|
|
422
|
|
|
423 case PROCESSOR_CORE2:
|
|
|
424 case PROCESSOR_NEHALEM:
|
|
|
425 case PROCESSOR_SANDYBRIDGE:
|
|
|
426 case PROCESSOR_HASWELL:
|
|
|
427 /* Stack engine allows to execute push&pop instructions in parall. */
|
|
|
428 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
|
|
|
429 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
|
|
|
430 return 0;
|
|
|
431
|
|
|
432 memory = get_attr_memory (insn);
|
|
|
433
|
|
|
434 /* Show ability of reorder buffer to hide latency of load by executing
|
|
|
435 in parallel with previous instruction in case
|
|
|
436 previous instruction is not needed to compute the address. */
|
|
|
437 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
|
|
|
438 && !ix86_agi_dependent (dep_insn, insn))
|
|
|
439 {
|
|
|
440 if (cost >= 4)
|
|
|
441 cost -= 4;
|
|
|
442 else
|
|
|
443 cost = 0;
|
|
|
444 }
|
|
|
445 break;
|
|
|
446
|
|
|
447 case PROCESSOR_SILVERMONT:
|
|
|
448 case PROCESSOR_KNL:
|
|
|
449 case PROCESSOR_KNM:
|
|
|
450 case PROCESSOR_INTEL:
|
|
|
451 if (!reload_completed)
|
|
|
452 return cost;
|
|
|
453
|
|
|
454 /* Increase cost of integer loads. */
|
|
|
455 memory = get_attr_memory (dep_insn);
|
|
|
456 if (memory == MEMORY_LOAD || memory == MEMORY_BOTH)
|
|
|
457 {
|
|
|
458 enum attr_unit unit = get_attr_unit (dep_insn);
|
|
|
459 if (unit == UNIT_INTEGER && cost == 1)
|
|
|
460 {
|
|
|
461 if (memory == MEMORY_LOAD)
|
|
|
462 cost = 3;
|
|
|
463 else
|
|
|
464 {
|
|
|
465 /* Increase cost of ld/st for short int types only
|
|
|
466 because of store forwarding issue. */
|
|
|
467 rtx set = single_set (dep_insn);
|
|
|
468 if (set && (GET_MODE (SET_DEST (set)) == QImode
|
|
|
469 || GET_MODE (SET_DEST (set)) == HImode))
|
|
|
470 {
|
|
|
471 /* Increase cost of store/load insn if exact
|
|
|
472 dependence exists and it is load insn. */
|
|
|
473 enum attr_memory insn_memory = get_attr_memory (insn);
|
|
|
474 if (insn_memory == MEMORY_LOAD
|
|
|
475 && exact_store_load_dependency (dep_insn, insn))
|
|
|
476 cost = 3;
|
|
|
477 }
|
|
|
478 }
|
|
|
479 }
|
|
|
480 }
|
|
|
481
|
|
|
482 default:
|
|
|
483 break;
|
|
|
484 }
|
|
|
485
|
|
|
486 return cost;
|
|
|
487 }
|
|
|
488
|
|
|
489 /* How many alternative schedules to try. This should be as wide as the
|
|
|
490 scheduling freedom in the DFA, but no wider. Making this value too
|
|
|
491 large results extra work for the scheduler. */
|
|
|
492
|
|
|
493 int
|
|
|
494 ia32_multipass_dfa_lookahead (void)
|
|
|
495 {
|
|
|
496 /* Generally, we want haifa-sched:max_issue() to look ahead as far
|
|
|
497 as many instructions can be executed on a cycle, i.e.,
|
|
|
498 issue_rate. */
|
|
|
499 if (reload_completed)
|
|
|
500 return ix86_issue_rate ();
|
|
|
501 /* Don't use lookahead for pre-reload schedule to save compile time. */
|
|
|
502 return 0;
|
|
|
503 }
|
|
|
504
|
|
|
505 /* Return true if target platform supports macro-fusion. */
|
|
|
506
|
|
|
507 bool
|
|
|
508 ix86_macro_fusion_p ()
|
|
|
509 {
|
|
|
510 return TARGET_FUSE_CMP_AND_BRANCH;
|
|
|
511 }
|
|
|
512
|
|
|
513 /* Check whether current microarchitecture support macro fusion
|
|
|
514 for insn pair "CONDGEN + CONDJMP". Refer to
|
|
|
515 "Intel Architectures Optimization Reference Manual". */
|
|
|
516
|
|
|
517 bool
|
|
|
518 ix86_macro_fusion_pair_p (rtx_insn *condgen, rtx_insn *condjmp)
|
|
|
519 {
|
|
|
520 rtx src, dest;
|
|
|
521 enum rtx_code ccode;
|
|
|
522 rtx compare_set = NULL_RTX, test_if, cond;
|
|
|
523 rtx alu_set = NULL_RTX, addr = NULL_RTX;
|
|
|
524
|
|
|
525 if (!any_condjump_p (condjmp))
|
|
|
526 return false;
|
|
|
527
|
|
|
528 unsigned int condreg1, condreg2;
|
|
|
529 rtx cc_reg_1;
|
|
|
530 targetm.fixed_condition_code_regs (&condreg1, &condreg2);
|
|
|
531 cc_reg_1 = gen_rtx_REG (CCmode, condreg1);
|
|
|
532 if (!reg_referenced_p (cc_reg_1, PATTERN (condjmp))
|
|
|
533 || !condgen
|
|
|
534 || !modified_in_p (cc_reg_1, condgen))
|
|
|
535 return false;
|
|
|
536
|
|
|
537 if (get_attr_type (condgen) != TYPE_TEST
|
|
|
538 && get_attr_type (condgen) != TYPE_ICMP
|
|
|
539 && get_attr_type (condgen) != TYPE_INCDEC
|
|
|
540 && get_attr_type (condgen) != TYPE_ALU)
|
|
|
541 return false;
|
|
|
542
|
|
|
543 compare_set = single_set (condgen);
|
|
|
544 if (compare_set == NULL_RTX
|
|
|
545 && !TARGET_FUSE_ALU_AND_BRANCH)
|
|
|
546 return false;
|
|
|
547
|
|
|
548 if (compare_set == NULL_RTX)
|
|
|
549 {
|
|
|
550 int i;
|
|
|
551 rtx pat = PATTERN (condgen);
|
|
|
552 for (i = 0; i < XVECLEN (pat, 0); i++)
|
|
|
553 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
|
|
|
554 {
|
|
|
555 rtx set_src = SET_SRC (XVECEXP (pat, 0, i));
|
|
|
556 if (GET_CODE (set_src) == COMPARE)
|
|
|
557 compare_set = XVECEXP (pat, 0, i);
|
|
|
558 else
|
|
|
559 alu_set = XVECEXP (pat, 0, i);
|
|
|
560 }
|
|
|
561 }
|
|
|
562 if (compare_set == NULL_RTX)
|
|
|
563 return false;
|
|
|
564 src = SET_SRC (compare_set);
|
|
|
565 if (GET_CODE (src) != COMPARE)
|
|
|
566 return false;
|
|
|
567
|
|
|
568 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
|
|
|
569 supported. */
|
|
|
570 if ((MEM_P (XEXP (src, 0))
|
|
|
571 && CONST_INT_P (XEXP (src, 1)))
|
|
|
572 || (MEM_P (XEXP (src, 1))
|
|
|
573 && CONST_INT_P (XEXP (src, 0))))
|
|
|
574 return false;
|
|
|
575
|
|
|
576 /* No fusion for RIP-relative address. */
|
|
|
577 if (MEM_P (XEXP (src, 0)))
|
|
|
578 addr = XEXP (XEXP (src, 0), 0);
|
|
|
579 else if (MEM_P (XEXP (src, 1)))
|
|
|
580 addr = XEXP (XEXP (src, 1), 0);
|
|
|
581
|
|
|
582 if (addr) {
|
|
|
583 ix86_address parts;
|
|
|
584 int ok = ix86_decompose_address (addr, &parts);
|
|
|
585 gcc_assert (ok);
|
|
|
586
|
|
|
587 if (ix86_rip_relative_addr_p (&parts))
|
|
|
588 return false;
|
|
|
589 }
|
|
|
590
|
|
|
591 test_if = SET_SRC (pc_set (condjmp));
|
|
|
592 cond = XEXP (test_if, 0);
|
|
|
593 ccode = GET_CODE (cond);
|
|
|
594 /* Check whether conditional jump use Sign or Overflow Flags. */
|
|
|
595 if (!TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS
|
|
|
596 && (ccode == GE
|
|
|
597 || ccode == GT
|
|
|
598 || ccode == LE
|
|
|
599 || ccode == LT))
|
|
|
600 return false;
|
|
|
601
|
|
|
602 /* Return true for TYPE_TEST and TYPE_ICMP. */
|
|
|
603 if (get_attr_type (condgen) == TYPE_TEST
|
|
|
604 || get_attr_type (condgen) == TYPE_ICMP)
|
|
|
605 return true;
|
|
|
606
|
|
|
607 /* The following is the case that macro-fusion for alu + jmp. */
|
|
|
608 if (!TARGET_FUSE_ALU_AND_BRANCH || !alu_set)
|
|
|
609 return false;
|
|
|
610
|
|
|
611 /* No fusion for alu op with memory destination operand. */
|
|
|
612 dest = SET_DEST (alu_set);
|
|
|
613 if (MEM_P (dest))
|
|
|
614 return false;
|
|
|
615
|
|
|
616 /* Macro-fusion for inc/dec + unsigned conditional jump is not
|
|
|
617 supported. */
|
|
|
618 if (get_attr_type (condgen) == TYPE_INCDEC
|
|
|
619 && (ccode == GEU
|
|
|
620 || ccode == GTU
|
|
|
621 || ccode == LEU
|
|
|
622 || ccode == LTU))
|
|
|
623 return false;
|
|
|
624
|
|
|
625 return true;
|
|
|
626 }
|
|
|
627
|
