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1 ;; Predicate definitions for Motorola MCore.
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2 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Nonzero if OP is a normal arithmetic register.
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21
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22 (define_predicate "mcore_arith_reg_operand"
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23 (match_code "reg,subreg")
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24 {
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25 if (! register_operand (op, mode))
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26 return 0;
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27
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28 if (GET_CODE (op) == SUBREG)
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29 op = SUBREG_REG (op);
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30
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31 if (GET_CODE (op) == REG)
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32 return REGNO (op) != CC_REG;
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33
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34 return 1;
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35 })
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36
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37 ;; Nonzero if OP can be source of a simple move operation.
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38
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39 (define_predicate "mcore_general_movsrc_operand"
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40 (match_code "mem,const_int,reg,subreg,symbol_ref,label_ref,const")
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41 {
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42 /* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
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43 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
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44 return 1;
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45
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46 return general_operand (op, mode);
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47 })
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48
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49 ;; Nonzero if OP can be destination of a simple move operation.
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50
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51 (define_predicate "mcore_general_movdst_operand"
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52 (match_code "mem,reg,subreg")
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53 {
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54 if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
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55 return 0;
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56
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57 return general_operand (op, mode);
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58 })
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59
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60 ;; Nonzero if OP should be recognized during reload for an ixh/ixw
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61 ;; operand. See the ixh/ixw patterns.
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62
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63 (define_predicate "mcore_reload_operand"
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64 (match_code "mem,reg,subreg")
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65 {
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66 if (mcore_arith_reg_operand (op, mode))
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67 return 1;
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68
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69 if (! reload_in_progress)
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70 return 0;
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71
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72 return GET_CODE (op) == MEM;
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73 })
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74
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75 ;; Nonzero if OP is a valid source operand for an arithmetic insn.
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76
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77 (define_predicate "mcore_arith_J_operand"
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78 (match_code "const_int,reg,subreg")
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79 {
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80 if (register_operand (op, mode))
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81 return 1;
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82
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83 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
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84 return 1;
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85
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86 return 0;
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87 })
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88
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89 ;; Nonzero if OP is a valid source operand for an arithmetic insn.
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90
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91 (define_predicate "mcore_arith_K_operand"
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92 (match_code "const_int,reg,subreg")
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93 {
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94 if (register_operand (op, mode))
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95 return 1;
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96
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97 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
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98 return 1;
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99
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100 return 0;
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101 })
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102
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103 ;; Nonzero if OP is a valid source operand for a shift or rotate insn.
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104
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105 (define_predicate "mcore_arith_K_operand_not_0"
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106 (match_code "const_int,reg,subreg")
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107 {
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108 if (register_operand (op, mode))
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109 return 1;
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110
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111 if ( GET_CODE (op) == CONST_INT
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112 && CONST_OK_FOR_K (INTVAL (op))
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113 && INTVAL (op) != 0)
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114 return 1;
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115
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116 return 0;
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117 })
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118
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119 ;; TODO: Add a comment here.
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120
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121 (define_predicate "mcore_arith_M_operand"
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122 (match_code "const_int,reg,subreg")
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123 {
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124 if (register_operand (op, mode))
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125 return 1;
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126
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127 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
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128 return 1;
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129
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130 return 0;
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131 })
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132
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133 ;; TODO: Add a comment here.
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134
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135 (define_predicate "mcore_arith_K_S_operand"
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136 (match_code "const_int,reg,subreg")
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137 {
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138 if (register_operand (op, mode))
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139 return 1;
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140
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141 if (GET_CODE (op) == CONST_INT)
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142 {
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143 if (CONST_OK_FOR_K (INTVAL (op)) || (mcore_num_zeros (INTVAL (op)) <= 2))
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144 return 1;
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145 }
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146
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147 return 0;
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148 })
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149
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150 ;; Nonzero if OP is a valid source operand for a cmov with two consts
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151 ;; +/- 1.
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152
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153 (define_predicate "mcore_arith_O_operand"
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154 (match_code "const_int,reg,subreg")
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155 {
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156 if (register_operand (op, mode))
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157 return 1;
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158
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159 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
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160 return 1;
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161
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162 return 0;
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163 })
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164
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165 ;; Nonzero if OP is a valid source operand for loading.
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166
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167 (define_predicate "mcore_arith_imm_operand"
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168 (match_code "const_int,reg,subreg")
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169 {
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170 if (register_operand (op, mode))
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171 return 1;
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172
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173 if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
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174 return 1;
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175
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176 return 0;
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177 })
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178
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179 ;; TODO: Add a comment here.
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180
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181 (define_predicate "mcore_arith_any_imm_operand"
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182 (match_code "const_int,reg,subreg")
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183 {
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184 if (register_operand (op, mode))
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185 return 1;
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186
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187 if (GET_CODE (op) == CONST_INT)
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188 return 1;
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189
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190 return 0;
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191 })
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192
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193 ;; Nonzero if OP is a valid source operand for a btsti.
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194
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195 (define_predicate "mcore_literal_K_operand"
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196 (match_code "const_int")
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197 {
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198 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
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199 return 1;
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200
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201 return 0;
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202 })
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203
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204 ;; Nonzero if OP is a valid source operand for an add/sub insn.
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205
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206 (define_predicate "mcore_addsub_operand"
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207 (match_code "const_int,reg,subreg")
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208 {
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209 if (register_operand (op, mode))
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210 return 1;
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211
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212 if (GET_CODE (op) == CONST_INT)
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213 {
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214 /* The following has been removed because it precludes large constants from being
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215 returned as valid source operands for and add/sub insn. While large
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216 constants may not directly be used in an add/sub, they may if first loaded
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217 into a register. Thus, this predicate should indicate that they are valid,
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218 and the constraint in mcore.md should control whether an additional load to
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219 register is needed. (see mcore.md, addsi). -- DAC 4/2/1998
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220
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221 if (CONST_OK_FOR_J (INTVAL (op)) || CONST_OK_FOR_L (INTVAL (op)))
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222 return 1;
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223
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224 However we do still need to check to make sure that the constant is not too
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225 big, especially if we are running on a 64-bit OS... Nickc 8/1/07. */
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226
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227 if (trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
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228 return 0;
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229
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230 return 1;
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231
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232 }
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233
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234 return 0;
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235 })
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236
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237 ;; Nonzero if OP is a valid source operand for a compare operation.
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238
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239 (define_predicate "mcore_compare_operand"
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240 (match_code "const_int,reg,subreg")
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241 {
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242 if (register_operand (op, mode))
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243 return 1;
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244
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245 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
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246 return 1;
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247
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248 return 0;
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249 })
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250
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251 ;; Return 1 if OP is a load multiple operation. It is known to be a
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252 ;; PARALLEL and the first section will be tested.
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253
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254 (define_predicate "mcore_load_multiple_operation"
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255 (match_code "parallel")
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256 {
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257 int count = XVECLEN (op, 0);
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258 int dest_regno;
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259 rtx src_addr;
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260 int i;
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261
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262 /* Perform a quick check so we don't blow up below. */
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263 if (count <= 1
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264 || GET_CODE (XVECEXP (op, 0, 0)) != SET
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265 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
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266 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
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267 return 0;
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268
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269 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
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270 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
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271
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272 for (i = 1; i < count; i++)
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273 {
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274 rtx elt = XVECEXP (op, 0, i);
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275
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276 if (GET_CODE (elt) != SET
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277 || GET_CODE (SET_DEST (elt)) != REG
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278 || GET_MODE (SET_DEST (elt)) != SImode
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279 || REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
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280 || GET_CODE (SET_SRC (elt)) != MEM
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281 || GET_MODE (SET_SRC (elt)) != SImode
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282 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
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283 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
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284 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
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285 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
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286 return 0;
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287 }
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288
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289 return 1;
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290 })
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291
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292 ;; Similar, but tests for store multiple.
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293
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294 (define_predicate "mcore_store_multiple_operation"
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295 (match_code "parallel")
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296 {
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297 int count = XVECLEN (op, 0);
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298 int src_regno;
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299 rtx dest_addr;
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300 int i;
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301
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302 /* Perform a quick check so we don't blow up below. */
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303 if (count <= 1
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304 || GET_CODE (XVECEXP (op, 0, 0)) != SET
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305 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
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306 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
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307 return 0;
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308
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309 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
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310 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
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311
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312 for (i = 1; i < count; i++)
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313 {
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314 rtx elt = XVECEXP (op, 0, i);
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315
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316 if (GET_CODE (elt) != SET
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317 || GET_CODE (SET_SRC (elt)) != REG
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318 || GET_MODE (SET_SRC (elt)) != SImode
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319 || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
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320 || GET_CODE (SET_DEST (elt)) != MEM
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321 || GET_MODE (SET_DEST (elt)) != SImode
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322 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
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323 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
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324 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
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325 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
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326 return 0;
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327 }
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328
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329 return 1;
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330 })
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331
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332 ;; TODO: Add a comment here.
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333
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334 (define_predicate "mcore_call_address_operand"
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335 (match_code "reg,subreg,const_int,symbol_ref")
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336 {
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337 return register_operand (op, mode) || CONSTANT_P (op);
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338 })
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