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annotate gcc/config/mips/i6400.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents
children 84e7813d76e9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
111
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1 ;; DFA-based pipeline description for I6400.
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2 ;;
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3 ;; Copyright (C) 2015-2017 Free Software Foundation, Inc.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "i6400_int_pipe, i6400_mdu_pipe, i6400_fpu_short_pipe,
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22 i6400_fpu_long_pipe")
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23
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24 (define_cpu_unit "i6400_gpmuldiv" "i6400_mdu_pipe")
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25 (define_cpu_unit "i6400_agen, i6400_alu1, i6400_lsu" "i6400_int_pipe")
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26 (define_cpu_unit "i6400_control, i6400_ctu, i6400_alu0" "i6400_int_pipe")
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27
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28 ;; Short FPU pipeline.
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29 (define_cpu_unit "i6400_fpu_short, i6400_fpu_intadd, i6400_fpu_logic,
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30 i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float,
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31 i6400_fpu_store" "i6400_fpu_short_pipe")
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32
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33 ;; Long FPU pipeline.
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34 (define_cpu_unit "i6400_fpu_long, i6400_fpu_logic_l, i6400_fpu_float_l,
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35 i6400_fpu_mult, i6400_fpu_apu" "i6400_fpu_long_pipe")
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36
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37 (define_reservation "i6400_control_ctu" "i6400_control, i6400_ctu")
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38 (define_reservation "i6400_control_alu0" "i6400_control, i6400_alu0")
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39 (define_reservation "i6400_agen_lsu" "i6400_agen, i6400_lsu")
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40 (define_reservation "i6400_agen_alu1" "i6400_agen, i6400_alu1")
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41
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42 ;;
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43 ;; FPU-MSA pipe
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44 ;;
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45
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46 ;; Short pipe
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47
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48 ;; addv, subv
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49 (define_insn_reservation "i6400_msa_add_d" 1
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50 (and (eq_attr "cpu" "i6400")
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51 (and (eq_attr "mode" "!V2DI")
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52 (eq_attr "alu_type" "simd_add")))
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53 "i6400_fpu_short, i6400_fpu_intadd")
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54
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55 ;; add, hadd, sub, hsub, average, min, max, compare
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56 (define_insn_reservation "i6400_msa_int_add" 2
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57 (and (eq_attr "cpu" "i6400")
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58 (eq_attr "type" "simd_int_arith"))
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59 "i6400_fpu_short, i6400_fpu_intadd")
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60
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61 ;; sat, pcnt
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62 (define_insn_reservation "i6400_msa_short_logic3" 3
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63 (and (eq_attr "cpu" "i6400")
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64 (eq_attr "type" "simd_sat,simd_pcnt"))
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65 "i6400_fpu_short, i6400_fpu_logic")
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66
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67 ;; shifts, nloc, nlzc, bneg, bclr, shf
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68 (define_insn_reservation "i6400_msa_short_logic2" 2
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69 (and (eq_attr "cpu" "i6400")
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70 (eq_attr "type" "simd_shift,simd_shf,simd_bit"))
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71 "i6400_fpu_short, i6400_fpu_logic")
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72
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73 ;; and, or, xor, ilv, pck, fill, splat
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74 (define_insn_reservation "i6400_msa_short_logic" 1
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75 (and (eq_attr "cpu" "i6400")
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76 (eq_attr "type" "simd_permute,simd_logic,simd_splat,simd_fill"))
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77 "i6400_fpu_short, i6400_fpu_logic")
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78
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79 ;; move.v, ldi
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80 (define_insn_reservation "i6400_msa_move" 1
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81 (and (eq_attr "cpu" "i6400")
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82 (eq_attr "type" "simd_move"))
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83 "i6400_fpu_short, i6400_fpu_logic")
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84
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85 ;; Float compare New: CMP.cond.fmt
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86 (define_insn_reservation "i6400_msa_cmp" 2
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87 (and (eq_attr "cpu" "i6400")
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88 (eq_attr "type" "simd_fcmp"))
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89 "i6400_fpu_short, i6400_fpu_cmp")
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90
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91 ;; Float min, max, class
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92 (define_insn_reservation "i6400_msa_short_float2" 2
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93 (and (eq_attr "cpu" "i6400")
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94 (eq_attr "type" "simd_fminmax,simd_fclass"))
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95 "i6400_fpu_short, i6400_fpu_float")
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96
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97 ;; div.d, mod.d (non-pipelined)
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98 (define_insn_reservation "i6400_msa_div_d" 36
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99 (and (eq_attr "cpu" "i6400")
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100 (and (eq_attr "mode" "V2DI")
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101 (eq_attr "type" "simd_div")))
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102 "i6400_fpu_short+i6400_fpu_div*36")
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103
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104 ;; div.w, mod.w (non-pipelined)
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105 (define_insn_reservation "i6400_msa_div_w" 20
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106 (and (eq_attr "cpu" "i6400")
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107 (and (eq_attr "mode" "V4SI")
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108 (eq_attr "type" "simd_div")))
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109 "i6400_fpu_short+i6400_fpu_div*20")
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110
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111 ;; div.h, mod.h (non-pipelined)
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112 (define_insn_reservation "i6400_msa_div_h" 12
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113 (and (eq_attr "cpu" "i6400")
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114 (and (eq_attr "mode" "V8HI")
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115 (eq_attr "type" "simd_div")))
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116 "i6400_fpu_short+i6400_fpu_div*12")
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117
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118 ;; div.b, mod.b (non-pipelined)
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119 (define_insn_reservation "i6400_msa_div_b" 8
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120 (and (eq_attr "cpu" "i6400")
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121 (and (eq_attr "mode" "V16QI")
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122 (eq_attr "type" "simd_div")))
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123 "i6400_fpu_short+i6400_fpu_div*8")
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124
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125 ;; Vector copy
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126 (define_insn_reservation "i6400_msa_copy" 1
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127 (and (eq_attr "cpu" "i6400")
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128 (eq_attr "type" "simd_copy"))
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129 "i6400_fpu_short, i6400_fpu_store")
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130
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131 ;; Vector bz, bnz
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132 (define_insn_reservation "i6400_msa_branch" 1
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133 (and (eq_attr "cpu" "i6400")
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134 (eq_attr "type" "simd_branch"))
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135 "i6400_control_ctu")
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136
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137 ;; Vector store
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138 (define_insn_reservation "i6400_fpu_msa_store" 1
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139 (and (eq_attr "cpu" "i6400")
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140 (eq_attr "type" "simd_store"))
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141 "i6400_agen_lsu")
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142
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143 ;; Vector load
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144 (define_insn_reservation "i6400_fpu_msa_load" 3
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145 (and (eq_attr "cpu" "i6400")
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146 (eq_attr "type" "simd_load"))
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147 "i6400_agen_lsu")
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148
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149 ;; cfcmsa, ctcmsa
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150 (define_insn_reservation "i6400_fpu_msa_move" 1
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151 (and (eq_attr "cpu" "i6400")
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152 (eq_attr "type" "simd_cmsa"))
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153 "i6400_control_alu0 | i6400_agen_alu1")
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154
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155 ;; Long pipe
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156
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157 ;; bmz, bmnz, bsel, insert, insve
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158 (define_insn_reservation "i6400_msa_long_logic1" 1
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159 (and (eq_attr "cpu" "i6400")
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160 (eq_attr "type" "simd_bitmov,simd_insert"))
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161 "i6400_fpu_long, i6400_fpu_logic_l")
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162
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163 ;; binsl, binsr, vshf, sld
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164 (define_insn_reservation "i6400_msa_long_logic2" 2
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165 (and (eq_attr "cpu" "i6400")
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166 (eq_attr "type" "simd_bitins,simd_sld"))
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167 "i6400_fpu_long, i6400_fpu_logic_l")
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168
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169 ;; Vector mul, dotp, madd, msub
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170 (define_insn_reservation "i6400_msa_mult" 5
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171 (and (eq_attr "cpu" "i6400")
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172 (eq_attr "type" "simd_mul"))
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173 "i6400_fpu_long, i6400_fpu_mult")
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174
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175 ;; Float flog2
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176 (define_insn_reservation "i6400_msa_long_float2" 2
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177 (and (eq_attr "cpu" "i6400")
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178 (eq_attr "type" "simd_flog2"))
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179 "i6400_fpu_long, i6400_fpu_float_l")
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180
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181 ;; fadd, fsub
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182 (define_insn_reservation "i6400_msa_long_float4" 4
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183 (and (eq_attr "cpu" "i6400")
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184 (eq_attr "type" "simd_fadd,simd_fcvt"))
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185 "i6400_fpu_long, i6400_fpu_float_l")
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186
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187 ;; fmul, fexp2
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188 (define_insn_reservation "i6400_msa_long_float5" 5
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189 (and (eq_attr "cpu" "i6400")
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190 (eq_attr "type" "simd_fmul,simd_fexp2"))
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191 "i6400_fpu_long, i6400_fpu_float_l")
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192
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193 ;; fmadd, fmsub
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194 (define_insn_reservation "i6400_msa_long_float8" 8
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195 (and (eq_attr "cpu" "i6400")
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196 (eq_attr "type" "simd_fmadd"))
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197 "i6400_fpu_long, i6400_fpu_float_l")
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198
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199 ;; fdiv.d
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200 (define_insn_reservation "i6400_msa_fdiv_df" 30
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201 (and (eq_attr "cpu" "i6400")
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202 (and (eq_attr "mode" "V2DF")
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203 (eq_attr "type" "simd_fdiv")))
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204 "i6400_fpu_long+i6400_fpu_float_l*30")
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205
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206 ;; fdiv.w
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207 (define_insn_reservation "i6400_msa_fdiv_sf" 22
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208 (and (eq_attr "cpu" "i6400")
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209 (eq_attr "type" "simd_fdiv"))
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210 "i6400_fpu_long+i6400_fpu_float_l*22")
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211
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212 ;;
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213 ;; FPU pipe
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214 ;;
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215
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216 ;; fabs, fneg
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217 (define_insn_reservation "i6400_fpu_fabs" 1
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218 (and (eq_attr "cpu" "i6400")
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219 (eq_attr "type" "fabs,fneg,fmove"))
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220 "i6400_fpu_short, i6400_fpu_apu")
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221
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222 ;; fadd, fsub, fcvt
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223 (define_insn_reservation "i6400_fpu_fadd" 4
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224 (and (eq_attr "cpu" "i6400")
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225 (eq_attr "type" "fadd, fcvt"))
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226 "i6400_fpu_long, i6400_fpu_apu")
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227
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228 ;; fmul
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229 (define_insn_reservation "i6400_fpu_fmul" 5
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230 (and (eq_attr "cpu" "i6400")
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231 (eq_attr "type" "fmul"))
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232 "i6400_fpu_long, i6400_fpu_apu")
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233
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234 ;; div, sqrt (Double Precision)
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235 (define_insn_reservation "i6400_fpu_div_df" 30
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236 (and (eq_attr "cpu" "i6400")
kono
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237 (and (eq_attr "mode" "DF")
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parents:
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238 (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")))
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239 "i6400_fpu_long+i6400_fpu_apu*30")
kono
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240
kono
parents:
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241 ;; div, sqrt (Single Precision)
kono
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242 (define_insn_reservation "i6400_fpu_div_sf" 22
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243 (and (eq_attr "cpu" "i6400")
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parents:
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244 (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt"))
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245 "i6400_fpu_long+i6400_fpu_apu*22")
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246
kono
parents:
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247 ;;
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parents:
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248 ;; Integer pipe
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parents:
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249 ;;
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250
kono
parents:
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251 ;; and, lui, shifts, seb, seh
kono
parents:
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252 (define_insn_reservation "i6400_int_logical" 1
kono
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253 (and (eq_attr "cpu" "i6400")
kono
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254 (eq_attr "move_type" "logical,const,andi,sll0,signext"))
kono
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255 "i6400_control_alu0 | i6400_agen_alu1")
kono
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256
kono
parents:
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257 ;; addi, addiu, ori, xori, add, addu, sub, nor
kono
parents:
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258 (define_insn_reservation "i6400_int_add" 1
kono
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259 (and (eq_attr "cpu" "i6400")
kono
parents:
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260 (eq_attr "alu_type" "add,sub,or,xor,nor"))
kono
parents:
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261 "i6400_control_alu0 | i6400_agen_alu1")
kono
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262
kono
parents:
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263 ;; shifts, clo, clz, cond move, arith
kono
parents:
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264 (define_insn_reservation "i6400_int_arith" 1
kono
parents:
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265 (and (eq_attr "cpu" "i6400")
kono
parents:
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266 (eq_attr "type" "shift,slt,move,clz,condmove,arith"))
kono
parents:
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267 "i6400_control_alu0 | i6400_agen_alu1")
kono
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268
kono
parents:
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269 ;; nop
kono
parents:
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270 (define_insn_reservation "i6400_int_nop" 0
kono
parents:
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271 (and (eq_attr "cpu" "i6400")
kono
parents:
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272 (eq_attr "type" "nop"))
kono
parents:
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273 "nothing")
kono
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274
kono
parents:
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275 ;; mult, multu, mul
kono
parents:
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276 (define_insn_reservation "i6400_int_mult" 4
kono
parents:
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277 (and (eq_attr "cpu" "i6400")
kono
parents:
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278 (eq_attr "type" "imul3,imul"))
kono
parents:
diff changeset
279 "i6400_gpmuldiv")
kono
parents:
diff changeset
280
kono
parents:
diff changeset
281 ;; divide
kono
parents:
diff changeset
282 (define_insn_reservation "i6400_int_div" 32
kono
parents:
diff changeset
283 (and (eq_attr "cpu" "i6400")
kono
parents:
diff changeset
284 (eq_attr "type" "idiv"))
kono
parents:
diff changeset
285 "i6400_gpmuldiv*32")
kono
parents:
diff changeset
286
kono
parents:
diff changeset
287 ;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs
kono
parents:
diff changeset
288 (define_insn_reservation "i6400_int_load" 3
kono
parents:
diff changeset
289 (and (eq_attr "cpu" "i6400")
kono
parents:
diff changeset
290 (eq_attr "move_type" "load"))
kono
parents:
diff changeset
291 "i6400_agen_lsu")
kono
parents:
diff changeset
292
kono
parents:
diff changeset
293 ;; store
kono
parents:
diff changeset
294 (define_insn_reservation "i6400_int_store" 1
kono
parents:
diff changeset
295 (and (eq_attr "cpu" "i6400")
kono
parents:
diff changeset
296 (eq_attr "move_type" "store"))
kono
parents:
diff changeset
297 "i6400_agen_lsu")
kono
parents:
diff changeset
298
kono
parents:
diff changeset
299 ;; prefetch
kono
parents:
diff changeset
300 (define_insn_reservation "i6400_int_prefetch" 3
kono
parents:
diff changeset
301 (and (eq_attr "cpu" "i6400")
kono
parents:
diff changeset
302 (eq_attr "type" "prefetch"))
kono
parents:
diff changeset
303 "i6400_agen_lsu")
kono
parents:
diff changeset
304
kono
parents:
diff changeset
305 ;; branch and jump
kono
parents:
diff changeset
306 (define_insn_reservation "i6400_int_branch" 1
kono
parents:
diff changeset
307 (and (eq_attr "cpu" "i6400")
kono
parents:
diff changeset
308 (eq_attr "type" "branch,jump"))
kono
parents:
diff changeset
309 "i6400_control_ctu")
kono
parents:
diff changeset
310
kono
parents:
diff changeset
311 ;; call
kono
parents:
diff changeset
312 (define_insn_reservation "i6400_int_call" 1
kono
parents:
diff changeset
313 (and (eq_attr "cpu" "i6400")
kono
parents:
diff changeset
314 (eq_attr "jal" "indirect,direct"))
kono
parents:
diff changeset
315 "i6400_control_ctu")