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annotate gcc/config/mips/m5100.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents
children 84e7813d76e9
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111
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1 ;; DFA-based pipeline description for MIPS32 models M5100.
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2 ;;
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3 ;; Copyright (C) 2015-2017 Free Software Foundation, Inc.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "m51_alu_pipe, m51_mdu_pipe, m51_fpu_pipe")
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22 (define_cpu_unit "m51_mul" "m51_mdu_pipe")
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23 (define_cpu_unit "m51_alu" "m51_alu_pipe")
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24 (define_cpu_unit "m51_fpu" "m51_fpu_pipe")
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25
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26 ;; --------------------------------------------------------------
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27 ;; ALU Instructions
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28 ;; --------------------------------------------------------------
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29
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30 ;; ALU: Logicals
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31 (define_insn_reservation "m51_int_logical" 1
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32 (and (eq_attr "cpu" "m5100")
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33 (eq_attr "type" "logical,move,signext,slt"))
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34 "m51_alu")
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35
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36 ;; Arithmetics
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37 (define_insn_reservation "m51_int" 1
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38 (and (eq_attr "cpu" "m5100")
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39 (eq_attr "type" "arith,const,shift,clz"))
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40 "m51_alu")
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41
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42 (define_insn_reservation "m51_int_nop" 0
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43 (and (eq_attr "cpu" "m5100")
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44 (eq_attr "type" "nop"))
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45 "nothing")
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46
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47 ;; Conditional move
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48 (define_insn_reservation "m51_int_cmove" 1
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49 (and (eq_attr "cpu" "m5100")
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50 (and (eq_attr "type" "condmove")
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51 (eq_attr "mode" "SI,DI")))
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52 "m51_alu")
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53
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54 ;; Call
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55 (define_insn_reservation "m51_int_call" 1
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56 (and (eq_attr "cpu" "m5100")
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57 (eq_attr "type" "call"))
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58 "m51_alu")
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59
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60 ;; branch/jump
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61 (define_insn_reservation "m51_int_jump" 1
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62 (and (eq_attr "cpu" "m5100")
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63 (eq_attr "type" "branch,jump"))
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64 "m51_alu")
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65
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66 ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
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67 ;; prefetch: prefetch, prefetchx
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68 (define_insn_reservation "m51_int_load" 2
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69 (and (eq_attr "cpu" "m5100")
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70 (eq_attr "type" "load,prefetch,prefetchx"))
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71 "m51_alu")
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72
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73 ;; stores
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74 (define_insn_reservation "m51_int_store" 1
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75 (and (eq_attr "cpu" "m5100")
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76 (eq_attr "type" "store"))
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77 "m51_alu")
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78
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79 ;; --------------------------------------------------------------
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80 ;; MDU Instructions
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81 ;; --------------------------------------------------------------
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82
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83 ;; High performance fully pipelined multiplier
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84 ;; MULT to HI/LO
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85 (define_insn_reservation "m51_int_mult" 2
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86 (and (eq_attr "cpu" "m5100")
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87 (eq_attr "type" "imul,imadd"))
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88 "m51_alu+m51_mul*2")
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89
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90 ;; MUL to GPR
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91 (define_insn_reservation "m51_int_mul3" 2
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92 (and (eq_attr "cpu" "m5100")
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93 (eq_attr "type" "imul3"))
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94 "(m51_alu*2)+(m51_mul*2)")
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95
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96 ;; mfhi, mflo
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97 (define_insn_reservation "m51_int_mfhilo" 1
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98 (and (eq_attr "cpu" "m5100")
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99 (eq_attr "type" "mfhi,mflo"))
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100 "m51_mul")
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101
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102 ;; mthi, mtlo
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103 (define_insn_reservation "m51_int_mthilo" 1
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104 (and (eq_attr "cpu" "m5100")
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105 (eq_attr "type" "mthi,mtlo"))
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106 "m51_mul")
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107
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108 ;; div
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109 (define_insn_reservation "m51_int_div_si" 34
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110 (and (eq_attr "cpu" "m5100")
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111 (eq_attr "type" "idiv"))
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112 "m51_alu+m51_mul*34")
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113
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114 ;; --------------------------------------------------------------
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115 ;; Floating Point Instructions
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116 ;; --------------------------------------------------------------
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117
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118 ;; fadd, fabs, fneg
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119 (define_insn_reservation "m51_fadd" 4
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120 (and (eq_attr "cpu" "m5100")
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121 (eq_attr "type" "fadd,fabs,fneg"))
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122 "m51_fpu")
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123
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124 ;; fmove
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125 (define_insn_reservation "m51_fmove" 4
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126 (and (eq_attr "cpu" "m5100")
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127 (eq_attr "type" "fmove"))
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128 "m51_fpu")
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129
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130 ;; conditional move
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131 (define_insn_reservation "m51_fp_cmove" 4
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132 (and (eq_attr "cpu" "m5100")
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133 (and (eq_attr "type" "condmove")
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134 (eq_attr "mode" "SF,DF")))
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135 "m51_fpu")
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136
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137 ;; fload
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138 (define_insn_reservation "m51_fload" 3
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139 (and (eq_attr "cpu" "m5100")
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140 (eq_attr "type" "fpload,fpidxload"))
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141 "m51_fpu")
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142
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143 ;; fstore
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144 (define_insn_reservation "m51_fstore" 1
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145 (and (eq_attr "cpu" "m5100")
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146 (eq_attr "type" "fpstore,fpidxstore"))
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147 "m51_fpu")
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148
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149 ;; fmul, fmadd
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150 (define_insn_reservation "m51_fmul_sf" 4
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151 (and (eq_attr "cpu" "m5100")
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152 (and (eq_attr "type" "fmul,fmadd")
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153 (eq_attr "mode" "SF")))
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154 "m51_fpu")
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155
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156 (define_insn_reservation "m51_fmul_df" 5
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157 (and (eq_attr "cpu" "m5100")
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158 (and (eq_attr "type" "fmul,fmadd")
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159 (eq_attr "mode" "DF")))
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160 "m51_fpu*2")
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161
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162 ;; fdiv, fsqrt
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163 (define_insn_reservation "m51_fdiv_sf" 17
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164 (and (eq_attr "cpu" "m5100")
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165 (and (eq_attr "type" "fdiv,fsqrt")
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166 (eq_attr "mode" "SF")))
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167 "m51_fpu*14")
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168
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169 (define_insn_reservation "m51_fdiv_df" 32
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170 (and (eq_attr "cpu" "m5100")
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171 (and (eq_attr "type" "fdiv,fsqrt")
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172 (eq_attr "mode" "DF")))
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173 "m51_fpu*29")
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174
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175 ;; frsqrt
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176 (define_insn_reservation "m51_frsqrt_sf" 17
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177 (and (eq_attr "cpu" "m5100")
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178 (and (eq_attr "type" "frsqrt")
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179 (eq_attr "mode" "SF")))
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180 "m51_fpu*14")
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181
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182 (define_insn_reservation "m51_frsqrt_df" 35
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183 (and (eq_attr "cpu" "m5100")
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184 (and (eq_attr "type" "frsqrt")
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185 (eq_attr "mode" "DF")))
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186 "m51_fpu*31")
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187
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188 ;; fcmp
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189 (define_insn_reservation "m51_fcmp" 4
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190 (and (eq_attr "cpu" "m5100")
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191 (eq_attr "type" "fcmp"))
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192 "m51_fpu")
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193
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194 ;; fcvt
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195 ;; cvt.s.d
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196 (define_insn_reservation "m51_fcvt_6" 6
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197 (and (eq_attr "cpu" "m5100")
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198 (and (eq_attr "type" "fcvt")
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199 (eq_attr "cnv_mode" "D2S")))
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200 "m51_fpu")
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201
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202 ;; trunc
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203 (define_insn_reservation "m51_fcvt_5" 5
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204 (and (eq_attr "cpu" "m5100")
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205 (and (eq_attr "type" "fcvt")
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206 (eq_attr "cnv_mode" "D2I,S2I")))
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207 "m51_fpu")
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208
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209 ;; cvt
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210 (define_insn_reservation "m51_fcvt_4" 4
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211 (and (eq_attr "cpu" "m5100")
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212 (and (eq_attr "type" "fcvt")
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213 (eq_attr "cnv_mode" "S2D,I2D,I2S")))
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214 "m51_fpu")
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215
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216 ;; mtc, mfc
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217 (define_insn_reservation "m51_move_to_from_c1" 2
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218 (and (eq_attr "cpu" "m5100")
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219 (eq_attr "type" "mtc, mfc"))
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220 "m51_fpu")