Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/mips/predicates.md @ 111:04ced10e8804
gcc 7
author | kono |
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date | Fri, 27 Oct 2017 22:46:09 +0900 |
parents | 77e2b8dfacca |
children | 84e7813d76e9 |
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0 | 1 ;; Predicate definitions for MIPS. |
111 | 2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc. |
0 | 3 ;; |
4 ;; This file is part of GCC. | |
5 ;; | |
6 ;; GCC is free software; you can redistribute it and/or modify | |
7 ;; it under the terms of the GNU General Public License as published by | |
8 ;; the Free Software Foundation; either version 3, or (at your option) | |
9 ;; any later version. | |
10 ;; | |
11 ;; GCC is distributed in the hope that it will be useful, | |
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 ;; GNU General Public License for more details. | |
15 ;; | |
16 ;; You should have received a copy of the GNU General Public License | |
17 ;; along with GCC; see the file COPYING3. If not see | |
18 ;; <http://www.gnu.org/licenses/>. | |
19 | |
20 (define_predicate "const_uns_arith_operand" | |
21 (and (match_code "const_int") | |
22 (match_test "SMALL_OPERAND_UNSIGNED (INTVAL (op))"))) | |
23 | |
24 (define_predicate "uns_arith_operand" | |
25 (ior (match_operand 0 "const_uns_arith_operand") | |
26 (match_operand 0 "register_operand"))) | |
27 | |
28 (define_predicate "const_arith_operand" | |
29 (and (match_code "const_int") | |
30 (match_test "SMALL_OPERAND (INTVAL (op))"))) | |
31 | |
32 (define_predicate "arith_operand" | |
33 (ior (match_operand 0 "const_arith_operand") | |
34 (match_operand 0 "register_operand"))) | |
35 | |
111 | 36 (define_predicate "const_immlsa_operand" |
37 (and (match_code "const_int") | |
38 (match_test "IN_RANGE (INTVAL (op), 1, 4)"))) | |
39 | |
40 (define_predicate "const_msa_branch_operand" | |
41 (and (match_code "const_int") | |
42 (match_test "IN_RANGE (INTVAL (op), -1024, 1023)"))) | |
43 | |
44 (define_predicate "const_uimm3_operand" | |
45 (and (match_code "const_int") | |
46 (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) | |
47 | |
48 (define_predicate "const_uimm4_operand" | |
49 (and (match_code "const_int") | |
50 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) | |
51 | |
52 (define_predicate "const_uimm5_operand" | |
53 (and (match_code "const_int") | |
54 (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) | |
55 | |
0 | 56 (define_predicate "const_uimm6_operand" |
57 (and (match_code "const_int") | |
58 (match_test "UIMM6_OPERAND (INTVAL (op))"))) | |
59 | |
111 | 60 (define_predicate "const_uimm8_operand" |
61 (and (match_code "const_int") | |
62 (match_test "IN_RANGE (INTVAL (op), 0, 255)"))) | |
63 | |
64 (define_predicate "const_imm5_operand" | |
65 (and (match_code "const_int") | |
66 (match_test "IN_RANGE (INTVAL (op), -16, 15)"))) | |
67 | |
0 | 68 (define_predicate "const_imm10_operand" |
69 (and (match_code "const_int") | |
70 (match_test "IMM10_OPERAND (INTVAL (op))"))) | |
71 | |
72 (define_predicate "reg_imm10_operand" | |
73 (ior (match_operand 0 "const_imm10_operand") | |
74 (match_operand 0 "register_operand"))) | |
75 | |
111 | 76 (define_predicate "aq10b_operand" |
77 (and (match_code "const_int") | |
78 (match_test "mips_signed_immediate_p (INTVAL (op), 10, 0)"))) | |
79 | |
80 (define_predicate "aq10h_operand" | |
81 (and (match_code "const_int") | |
82 (match_test "mips_signed_immediate_p (INTVAL (op), 10, 1)"))) | |
83 | |
84 (define_predicate "aq10w_operand" | |
85 (and (match_code "const_int") | |
86 (match_test "mips_signed_immediate_p (INTVAL (op), 10, 2)"))) | |
87 | |
88 (define_predicate "aq10d_operand" | |
89 (and (match_code "const_int") | |
90 (match_test "mips_signed_immediate_p (INTVAL (op), 10, 3)"))) | |
91 | |
0 | 92 (define_predicate "sle_operand" |
93 (and (match_code "const_int") | |
94 (match_test "SMALL_OPERAND (INTVAL (op) + 1)"))) | |
95 | |
96 (define_predicate "sleu_operand" | |
97 (and (match_operand 0 "sle_operand") | |
98 (match_test "INTVAL (op) + 1 != 0"))) | |
99 | |
100 (define_predicate "const_0_operand" | |
101 (and (match_code "const_int,const_double,const_vector") | |
102 (match_test "op == CONST0_RTX (GET_MODE (op))"))) | |
103 | |
111 | 104 (define_predicate "const_m1_operand" |
105 (and (match_code "const_int,const_double,const_vector") | |
106 (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) | |
107 | |
108 (define_predicate "reg_or_m1_operand" | |
109 (ior (match_operand 0 "const_m1_operand") | |
110 (match_operand 0 "register_operand"))) | |
111 | |
0 | 112 (define_predicate "reg_or_0_operand" |
113 (ior (and (match_operand 0 "const_0_operand") | |
111 | 114 (not (match_test "TARGET_MIPS16"))) |
0 | 115 (match_operand 0 "register_operand"))) |
116 | |
117 (define_predicate "const_1_operand" | |
118 (and (match_code "const_int,const_double,const_vector") | |
119 (match_test "op == CONST1_RTX (GET_MODE (op))"))) | |
120 | |
121 (define_predicate "reg_or_1_operand" | |
122 (ior (match_operand 0 "const_1_operand") | |
123 (match_operand 0 "register_operand"))) | |
124 | |
111 | 125 ;; These are used in vec_merge, hence accept bitmask as const_int. |
126 (define_predicate "const_exp_2_operand" | |
127 (and (match_code "const_int") | |
128 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 1)"))) | |
129 | |
130 (define_predicate "const_exp_4_operand" | |
131 (and (match_code "const_int") | |
132 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 3)"))) | |
133 | |
134 (define_predicate "const_exp_8_operand" | |
135 (and (match_code "const_int") | |
136 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 7)"))) | |
137 | |
138 (define_predicate "const_exp_16_operand" | |
139 (and (match_code "const_int") | |
140 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 15)"))) | |
141 | |
0 | 142 ;; This is used for indexing into vectors, and hence only accepts const_int. |
143 (define_predicate "const_0_or_1_operand" | |
144 (and (match_code "const_int") | |
111 | 145 (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) |
146 | |
147 (define_predicate "const_2_or_3_operand" | |
148 (and (match_code "const_int") | |
149 (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) | |
150 | |
151 (define_predicate "const_0_to_3_operand" | |
152 (and (match_code "const_int") | |
153 (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) | |
0 | 154 |
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155 (define_predicate "qi_mask_operand" |
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156 (and (match_code "const_int") |
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157 (match_test "UINTVAL (op) == 0xff"))) |
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158 |
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159 (define_predicate "hi_mask_operand" |
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160 (and (match_code "const_int") |
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161 (match_test "UINTVAL (op) == 0xffff"))) |
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162 |
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163 (define_predicate "si_mask_operand" |
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164 (and (match_code "const_int") |
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165 (match_test "UINTVAL (op) == 0xffffffff"))) |
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166 |
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167 (define_predicate "and_load_operand" |
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168 (ior (match_operand 0 "qi_mask_operand") |
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169 (match_operand 0 "hi_mask_operand") |
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170 (match_operand 0 "si_mask_operand"))) |
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171 |
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172 (define_predicate "low_bitmask_operand" |
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173 (and (match_test "ISA_HAS_EXT_INS") |
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174 (match_code "const_int") |
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175 (match_test "low_bitmask_len (mode, INTVAL (op)) > 16"))) |
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176 |
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177 (define_predicate "and_reg_operand" |
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178 (ior (match_operand 0 "register_operand") |
111 | 179 (and (not (match_test "TARGET_MIPS16")) |
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180 (match_operand 0 "const_uns_arith_operand")) |
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181 (match_operand 0 "low_bitmask_operand") |
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182 (match_operand 0 "si_mask_operand"))) |
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183 |
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184 (define_predicate "and_operand" |
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185 (ior (match_operand 0 "and_load_operand") |
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186 (match_operand 0 "and_reg_operand"))) |
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187 |
0 | 188 (define_predicate "d_operand" |
189 (and (match_code "reg") | |
190 (match_test "TARGET_MIPS16 | |
191 ? M16_REG_P (REGNO (op)) | |
192 : GP_REG_P (REGNO (op))"))) | |
193 | |
111 | 194 (define_predicate "lwsp_swsp_operand" |
195 (and (match_code "mem") | |
196 (match_test "lwsp_swsp_address_p (XEXP (op, 0), mode)"))) | |
197 | |
198 (define_predicate "lw16_sw16_operand" | |
199 (and (match_code "mem") | |
200 (match_test "m16_based_address_p (XEXP (op, 0), mode, uw4_operand)"))) | |
201 | |
202 (define_predicate "lhu16_sh16_operand" | |
203 (and (match_code "mem") | |
204 (match_test "m16_based_address_p (XEXP (op, 0), mode, uh4_operand)"))) | |
205 | |
206 (define_predicate "lbu16_operand" | |
207 (and (match_code "mem") | |
208 (match_test "m16_based_address_p (XEXP (op, 0), mode, db4_operand)"))) | |
209 | |
210 (define_predicate "sb16_operand" | |
211 (and (match_code "mem") | |
212 (match_test "m16_based_address_p (XEXP (op, 0), mode, ub4_operand)"))) | |
213 | |
214 (define_predicate "db4_operand" | |
215 (and (match_code "const_int") | |
216 (match_test "mips_unsigned_immediate_p (INTVAL (op) + 1, 4, 0)"))) | |
217 | |
218 (define_predicate "db7_operand" | |
219 (and (match_code "const_int") | |
220 (match_test "mips_unsigned_immediate_p (INTVAL (op) + 1, 7, 0)"))) | |
221 | |
222 (define_predicate "db8_operand" | |
223 (and (match_code "const_int") | |
224 (match_test "mips_unsigned_immediate_p (INTVAL (op) + 1, 8, 0)"))) | |
225 | |
226 (define_predicate "ib3_operand" | |
227 (and (match_code "const_int") | |
228 (match_test "mips_unsigned_immediate_p (INTVAL (op) - 1, 3, 0)"))) | |
229 | |
230 (define_predicate "sb4_operand" | |
231 (and (match_code "const_int") | |
232 (match_test "mips_signed_immediate_p (INTVAL (op), 4, 0)"))) | |
233 | |
234 (define_predicate "sb5_operand" | |
235 (and (match_code "const_int") | |
236 (match_test "mips_signed_immediate_p (INTVAL (op), 5, 0)"))) | |
237 | |
238 (define_predicate "sb8_operand" | |
239 (and (match_code "const_int") | |
240 (match_test "mips_signed_immediate_p (INTVAL (op), 8, 0)"))) | |
241 | |
242 (define_predicate "sd8_operand" | |
243 (and (match_code "const_int") | |
244 (match_test "mips_signed_immediate_p (INTVAL (op), 8, 3)"))) | |
245 | |
246 (define_predicate "ub4_operand" | |
247 (and (match_code "const_int") | |
248 (match_test "mips_unsigned_immediate_p (INTVAL (op), 4, 0)"))) | |
249 | |
250 (define_predicate "ub8_operand" | |
251 (and (match_code "const_int") | |
252 (match_test "mips_unsigned_immediate_p (INTVAL (op), 8, 0)"))) | |
253 | |
254 (define_predicate "uh4_operand" | |
255 (and (match_code "const_int") | |
256 (match_test "mips_unsigned_immediate_p (INTVAL (op), 4, 1)"))) | |
257 | |
258 (define_predicate "uw4_operand" | |
259 (and (match_code "const_int") | |
260 (match_test "mips_unsigned_immediate_p (INTVAL (op), 4, 2)"))) | |
261 | |
262 (define_predicate "uw5_operand" | |
263 (and (match_code "const_int") | |
264 (match_test "mips_unsigned_immediate_p (INTVAL (op), 5, 2)"))) | |
265 | |
266 (define_predicate "uw6_operand" | |
267 (and (match_code "const_int") | |
268 (match_test "mips_unsigned_immediate_p (INTVAL (op), 6, 2)"))) | |
269 | |
270 (define_predicate "uw8_operand" | |
271 (and (match_code "const_int") | |
272 (match_test "mips_unsigned_immediate_p (INTVAL (op), 8, 2)"))) | |
273 | |
274 (define_predicate "addiur2_operand" | |
275 (and (match_code "const_int") | |
276 (ior (match_test "INTVAL (op) == -1") | |
277 (match_test "INTVAL (op) == 1") | |
278 (match_test "INTVAL (op) == 4") | |
279 (match_test "INTVAL (op) == 8") | |
280 (match_test "INTVAL (op) == 12") | |
281 (match_test "INTVAL (op) == 16") | |
282 (match_test "INTVAL (op) == 20") | |
283 (match_test "INTVAL (op) == 24")))) | |
284 | |
285 (define_predicate "addiusp_operand" | |
286 (and (match_code "const_int") | |
287 (ior (match_test "(IN_RANGE (INTVAL (op), 2, 257))") | |
288 (match_test "(IN_RANGE (INTVAL (op), -258, -3))")))) | |
289 | |
290 (define_predicate "andi16_operand" | |
291 (and (match_code "const_int") | |
292 (ior (match_test "IN_RANGE (INTVAL (op), 1, 4)") | |
293 (match_test "IN_RANGE (INTVAL (op), 7, 8)") | |
294 (match_test "IN_RANGE (INTVAL (op), 15, 16)") | |
295 (match_test "IN_RANGE (INTVAL (op), 31, 32)") | |
296 (match_test "IN_RANGE (INTVAL (op), 63, 64)") | |
297 (match_test "INTVAL (op) == 255") | |
298 (match_test "INTVAL (op) == 32768") | |
299 (match_test "INTVAL (op) == 65535")))) | |
300 | |
301 (define_predicate "movep_src_register" | |
302 (and (match_code "reg") | |
303 (ior (match_test ("IN_RANGE (REGNO (op), 2, 3)")) | |
304 (match_test ("IN_RANGE (REGNO (op), 16, 20)"))))) | |
305 | |
306 (define_predicate "movep_src_operand" | |
307 (ior (match_operand 0 "const_0_operand") | |
308 (match_operand 0 "movep_src_register"))) | |
309 | |
0 | 310 (define_predicate "lo_operand" |
311 (and (match_code "reg") | |
312 (match_test "REGNO (op) == LO_REGNUM"))) | |
313 | |
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314 (define_predicate "hilo_operand" |
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315 (and (match_code "reg") |
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316 (match_test "MD_REG_P (REGNO (op))"))) |
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317 |
0 | 318 (define_predicate "fcc_reload_operand" |
319 (and (match_code "reg,subreg") | |
320 (match_test "ST_REG_P (true_regnum (op))"))) | |
321 | |
111 | 322 (define_predicate "muldiv_target_operand" |
323 (if_then_else (match_test "TARGET_MIPS16") | |
324 (match_operand 0 "hilo_operand") | |
325 (match_operand 0 "register_operand"))) | |
0 | 326 |
327 (define_predicate "const_call_insn_operand" | |
328 (match_code "const,symbol_ref,label_ref") | |
329 { | |
330 enum mips_symbol_type symbol_type; | |
331 | |
332 if (!mips_symbolic_constant_p (op, SYMBOL_CONTEXT_CALL, &symbol_type)) | |
333 return false; | |
334 | |
335 switch (symbol_type) | |
336 { | |
337 case SYMBOL_ABSOLUTE: | |
338 /* We can only use direct calls if we're sure that the target | |
339 function does not need $25 to be valid on entry. */ | |
340 if (mips_use_pic_fn_addr_reg_p (op)) | |
341 return false; | |
342 | |
343 /* If -mlong-calls or if this function has an explicit long_call | |
344 attribute, we must use register addressing. The | |
345 SYMBOL_FLAG_LONG_CALL bit is set by mips_encode_section_info. */ | |
346 return !(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LONG_CALL_P (op)); | |
347 | |
348 case SYMBOL_GOT_DISP: | |
349 /* Without explicit relocs, there is no special syntax for | |
350 loading the address of a call destination into a register. | |
351 Using "la $25,foo; jal $25" would prevent the lazy binding | |
352 of "foo", so keep the address of global symbols with the | |
353 jal macro. */ | |
354 return !TARGET_EXPLICIT_RELOCS; | |
355 | |
356 default: | |
357 return false; | |
358 } | |
359 }) | |
360 | |
361 (define_predicate "call_insn_operand" | |
362 (ior (match_operand 0 "const_call_insn_operand") | |
363 (match_operand 0 "register_operand"))) | |
364 | |
365 ;; A legitimate CONST_INT operand that takes more than one instruction | |
366 ;; to load. | |
367 (define_predicate "splittable_const_int_operand" | |
368 (match_code "const_int") | |
369 { | |
111 | 370 /* When generating mips16 code, TARGET_LEGITIMATE_CONSTANT_P rejects |
0 | 371 CONST_INTs that can't be loaded using simple insns. */ |
372 if (TARGET_MIPS16) | |
373 return false; | |
374 | |
375 /* Don't handle multi-word moves this way; we don't want to introduce | |
376 the individual word-mode moves until after reload. */ | |
377 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
378 return false; | |
379 | |
380 /* Otherwise check whether the constant can be loaded in a single | |
381 instruction. */ | |
382 return !LUI_INT (op) && !SMALL_INT (op) && !SMALL_INT_UNSIGNED (op); | |
383 }) | |
384 | |
385 (define_predicate "move_operand" | |
111 | 386 ;; Allow HI and LO to be used as the source of a MIPS16 move. |
387 (ior (match_operand 0 "general_operand") | |
388 (match_operand 0 "hilo_operand")) | |
0 | 389 { |
390 enum mips_symbol_type symbol_type; | |
391 | |
392 /* The thinking here is as follows: | |
393 | |
394 (1) The move expanders should split complex load sequences into | |
395 individual instructions. Those individual instructions can | |
396 then be optimized by all rtl passes. | |
397 | |
398 (2) The target of pre-reload load sequences should not be used | |
399 to store temporary results. If the target register is only | |
400 assigned one value, reload can rematerialize that value | |
401 on demand, rather than spill it to the stack. | |
402 | |
403 (3) If we allowed pre-reload passes like combine and cse to recreate | |
404 complex load sequences, we would want to be able to split the | |
405 sequences before reload as well, so that the pre-reload scheduler | |
406 can see the individual instructions. This falls foul of (2); | |
407 the splitter would be forced to reuse the target register for | |
408 intermediate results. | |
409 | |
410 (4) We want to define complex load splitters for combine. These | |
411 splitters can request a temporary scratch register, which avoids | |
412 the problem in (2). They allow things like: | |
413 | |
414 (set (reg T1) (high SYM)) | |
415 (set (reg T2) (low (reg T1) SYM)) | |
416 (set (reg X) (plus (reg T2) (const_int OFFSET))) | |
417 | |
418 to be combined into: | |
419 | |
420 (set (reg T3) (high SYM+OFFSET)) | |
421 (set (reg X) (lo_sum (reg T3) SYM+OFFSET)) | |
422 | |
423 if T2 is only used this once. */ | |
424 switch (GET_CODE (op)) | |
425 { | |
426 case CONST_INT: | |
427 return !splittable_const_int_operand (op, mode); | |
428 | |
429 case CONST: | |
430 case SYMBOL_REF: | |
431 case LABEL_REF: | |
432 if (CONST_GP_P (op)) | |
433 return true; | |
434 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &symbol_type) | |
435 && !mips_split_p[symbol_type]); | |
436 | |
437 case HIGH: | |
438 op = XEXP (op, 0); | |
439 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &symbol_type) | |
440 && !mips_split_hi_p[symbol_type]); | |
441 | |
442 default: | |
443 return true; | |
444 } | |
445 }) | |
446 | |
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447 (define_predicate "cprestore_save_slot_operand" |
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448 (and (match_code "mem") |
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449 (match_test "mips_cprestore_address_p (XEXP (op, 0), false)"))) |
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450 |
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451 (define_predicate "cprestore_load_slot_operand" |
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452 (and (match_code "mem") |
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453 (match_test "mips_cprestore_address_p (XEXP (op, 0), true)"))) |
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454 |
0 | 455 (define_predicate "consttable_operand" |
456 (match_test "CONSTANT_P (op)")) | |
457 | |
458 (define_predicate "symbolic_operand" | |
459 (match_code "const,symbol_ref,label_ref") | |
460 { | |
461 enum mips_symbol_type type; | |
462 return mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type); | |
463 }) | |
464 | |
465 (define_predicate "absolute_symbolic_operand" | |
466 (match_code "const,symbol_ref,label_ref") | |
467 { | |
468 enum mips_symbol_type type; | |
469 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type) | |
470 && type == SYMBOL_ABSOLUTE); | |
471 }) | |
472 | |
111 | 473 (define_predicate "symbolic_operand_with_high" |
474 (match_code "const,symbol_ref,label_ref") | |
475 { | |
476 enum mips_symbol_type type; | |
477 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type) | |
478 && mips_hi_relocs[(int) type]); | |
479 }) | |
480 | |
0 | 481 (define_predicate "force_to_mem_operand" |
482 (match_code "const,symbol_ref,label_ref") | |
483 { | |
484 enum mips_symbol_type symbol_type; | |
485 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &symbol_type) | |
111 | 486 && mips_use_pcrel_pool_p[(int) symbol_type]); |
0 | 487 }) |
488 | |
489 (define_predicate "got_disp_operand" | |
490 (match_code "const,symbol_ref,label_ref") | |
491 { | |
492 enum mips_symbol_type type; | |
493 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type) | |
494 && type == SYMBOL_GOT_DISP); | |
495 }) | |
496 | |
497 (define_predicate "got_page_ofst_operand" | |
498 (match_code "const,symbol_ref,label_ref") | |
499 { | |
500 enum mips_symbol_type type; | |
501 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type) | |
502 && type == SYMBOL_GOT_PAGE_OFST); | |
503 }) | |
504 | |
111 | 505 (define_predicate "tls_reloc_operand" |
506 (match_code "const,symbol_ref,label_ref") | |
507 { | |
508 enum mips_symbol_type type; | |
509 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type) | |
510 && (type == SYMBOL_DTPREL || type == SYMBOL_TPREL)); | |
511 }) | |
512 | |
0 | 513 (define_predicate "symbol_ref_operand" |
514 (match_code "symbol_ref")) | |
515 | |
516 (define_predicate "stack_operand" | |
517 (and (match_code "mem") | |
518 (match_test "mips_stack_address_p (XEXP (op, 0), GET_MODE (op))"))) | |
519 | |
520 (define_predicate "macc_msac_operand" | |
521 (ior (and (match_code "plus") (match_test "ISA_HAS_MACC")) | |
522 (and (match_code "minus") (match_test "ISA_HAS_MSAC"))) | |
523 { | |
524 rtx mult = XEXP (op, GET_CODE (op) == PLUS ? 0 : 1); | |
525 rtx accum = XEXP (op, GET_CODE (op) == PLUS ? 1 : 0); | |
526 return (GET_CODE (mult) == MULT | |
527 && REG_P (XEXP (mult, 0)) | |
528 && REG_P (XEXP (mult, 1)) | |
529 && REG_P (accum)); | |
530 }) | |
531 | |
532 | |
533 (define_predicate "equality_operator" | |
534 (match_code "eq,ne")) | |
535 | |
536 (define_predicate "extend_operator" | |
537 (match_code "zero_extend,sign_extend")) | |
538 | |
539 (define_predicate "trap_comparison_operator" | |
540 (match_code "eq,ne,lt,ltu,ge,geu")) | |
541 | |
542 (define_predicate "order_operator" | |
111 | 543 (match_code "lt,ltu,le,leu,ge,geu,gt,gtu") |
544 { | |
545 if (XEXP (op, 1) == const0_rtx) | |
546 return true; | |
547 | |
548 if (TARGET_CB_MAYBE | |
549 && (GET_CODE (op) == LT || GET_CODE (op) == LTU | |
550 || GET_CODE (op) == GE || GET_CODE (op) == GEU)) | |
551 return true; | |
552 | |
553 return false; | |
554 }) | |
0 | 555 |
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556 ;; For NE, cstore uses sltu instructions in which the first operand is $0. |
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557 ;; This isn't possible in mips16 code. |
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558 |
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559 (define_predicate "mips_cstore_operator" |
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560 (ior (match_code "eq,gt,gtu,ge,geu,lt,ltu,le,leu") |
111 | 561 (and (match_code "ne") (not (match_test "TARGET_MIPS16"))))) |
0 | 562 |
563 (define_predicate "small_data_pattern" | |
564 (and (match_code "set,parallel,unspec,unspec_volatile,prefetch") | |
565 (match_test "mips_small_data_pattern_p (op)"))) | |
111 | 566 |
567 (define_predicate "mem_noofs_operand" | |
568 (and (match_code "mem") | |
569 (match_code "reg" "0"))) | |
570 | |
571 ;; Return 1 if the operand is in non-volatile memory. | |
572 (define_predicate "non_volatile_mem_operand" | |
573 (and (match_operand 0 "memory_operand") | |
574 (not (match_test "MEM_VOLATILE_P (op)")))) | |
575 | |
576 (define_predicate "const_vector_same_val_operand" | |
577 (match_code "const_vector") | |
578 { | |
579 return mips_const_vector_same_val_p (op, mode); | |
580 }) | |
581 | |
582 (define_predicate "const_vector_same_simm5_operand" | |
583 (match_code "const_vector") | |
584 { | |
585 return mips_const_vector_same_int_p (op, mode, -16, 15); | |
586 }) | |
587 | |
588 (define_predicate "const_vector_same_uimm5_operand" | |
589 (match_code "const_vector") | |
590 { | |
591 return mips_const_vector_same_int_p (op, mode, 0, 31); | |
592 }) | |
593 | |
594 (define_predicate "const_vector_same_ximm5_operand" | |
595 (match_code "const_vector") | |
596 { | |
597 return mips_const_vector_same_int_p (op, mode, -31, 31); | |
598 }) | |
599 | |
600 (define_predicate "const_vector_same_uimm6_operand" | |
601 (match_code "const_vector") | |
602 { | |
603 return mips_const_vector_same_int_p (op, mode, 0, 63); | |
604 }) | |
605 | |
606 (define_predicate "const_vector_same_uimm8_operand" | |
607 (match_code "const_vector") | |
608 { | |
609 return mips_const_vector_same_int_p (op, mode, 0, 255); | |
610 }) | |
611 | |
612 (define_predicate "par_const_vector_shf_set_operand" | |
613 (match_code "parallel") | |
614 { | |
615 return mips_const_vector_shuffle_set_p (op, mode); | |
616 }) | |
617 | |
618 (define_predicate "reg_or_vector_same_val_operand" | |
619 (ior (match_operand 0 "register_operand") | |
620 (match_operand 0 "const_vector_same_val_operand"))) | |
621 | |
622 (define_predicate "reg_or_vector_same_simm5_operand" | |
623 (ior (match_operand 0 "register_operand") | |
624 (match_operand 0 "const_vector_same_simm5_operand"))) | |
625 | |
626 (define_predicate "reg_or_vector_same_uimm5_operand" | |
627 (ior (match_operand 0 "register_operand") | |
628 (match_operand 0 "const_vector_same_uimm5_operand"))) | |
629 | |
630 (define_predicate "reg_or_vector_same_ximm5_operand" | |
631 (ior (match_operand 0 "register_operand") | |
632 (match_operand 0 "const_vector_same_ximm5_operand"))) | |
633 | |
634 (define_predicate "reg_or_vector_same_uimm6_operand" | |
635 (ior (match_operand 0 "register_operand") | |
636 (match_operand 0 "const_vector_same_uimm6_operand"))) |