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1 ;; DFA-based pipeline description for the XLP.
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2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; xlp.md Machine Description for the Broadcom XLP Microprocessor
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "xlp_cpu")
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22
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23 ;; CPU function units.
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24 (define_cpu_unit "xlp_ex0" "xlp_cpu")
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25 (define_cpu_unit "xlp_ex1" "xlp_cpu")
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26 (define_cpu_unit "xlp_ex2" "xlp_cpu")
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27 (define_cpu_unit "xlp_ex3" "xlp_cpu")
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28
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29 ;; Integer Multiply Unit
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30 (define_cpu_unit "xlp_div" "xlp_cpu")
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31
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32 ;; ALU2 completion port.
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33 (define_cpu_unit "xlp_ex2_wrb" "xlp_cpu")
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34
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35 (define_automaton "xlp_fpu")
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36
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37 ;; Floating-point units.
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38 (define_cpu_unit "xlp_fp" "xlp_fpu")
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39
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40 ;; Floating Point Sqrt/Divide
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41 (define_cpu_unit "xlp_divsq" "xlp_fpu")
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42
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43 ;; FPU completion port.
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44 (define_cpu_unit "xlp_fp_wrb" "xlp_fpu")
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45
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46 ;; Define reservations for common combinations.
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47
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48 ;;
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49 ;; The ordering of the instruction-execution-path/resource-usage
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50 ;; descriptions (also known as reservation RTL) is roughly ordered
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51 ;; based on the define attribute RTL for the "type" classification.
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52 ;; When modifying, remember that the first test that matches is the
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53 ;; reservation used!
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54 ;;
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55 (define_insn_reservation "ir_xlp_unknown" 1
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56 (and (eq_attr "cpu" "xlp")
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57 (eq_attr "type" "unknown,multi"))
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58 "xlp_ex0+xlp_ex1+xlp_ex2+xlp_ex3")
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59
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60 (define_insn_reservation "ir_xlp_branch" 1
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61 (and (eq_attr "cpu" "xlp")
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62 (eq_attr "type" "branch,jump,call"))
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63 "xlp_ex3")
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64
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65 (define_insn_reservation "ir_xlp_prefetch" 1
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66 (and (eq_attr "cpu" "xlp")
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67 (eq_attr "type" "prefetch,prefetchx"))
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68 "xlp_ex0|xlp_ex1")
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69
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70 (define_insn_reservation "ir_xlp_load" 4
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71 (and (eq_attr "cpu" "xlp")
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72 (eq_attr "type" "load"))
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73 "xlp_ex0|xlp_ex1")
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74
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75 (define_insn_reservation "ir_xlp_fpload" 5
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76 (and (eq_attr "cpu" "xlp")
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77 (eq_attr "type" "fpload,fpidxload"))
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78 "xlp_ex0|xlp_ex1")
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79
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80 (define_insn_reservation "ir_xlp_alu" 1
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81 (and (eq_attr "cpu" "xlp")
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82 (eq_attr "type" "const,arith,shift,slt,clz,signext,logical,move,trap,nop"))
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83 "xlp_ex0|xlp_ex1|(xlp_ex2,xlp_ex2_wrb)|xlp_ex3")
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84
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85 (define_insn_reservation "ir_xlp_condmov" 1
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86 (and (eq_attr "cpu" "xlp")
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87 (eq_attr "type" "condmove")
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88 (eq_attr "mode" "SI,DI"))
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89 "xlp_ex2,xlp_ex2_wrb")
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90
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91 (define_insn_reservation "ir_xlp_mul" 5
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92 (and (eq_attr "cpu" "xlp")
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93 (eq_attr "type" "imul,imadd"))
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94 "xlp_ex2,nothing*4,xlp_ex2_wrb")
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95
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96 (define_insn_reservation "ir_xlp_mul3" 3
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97 (and (eq_attr "cpu" "xlp")
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98 (eq_attr "type" "imul3"))
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99 "xlp_ex2,nothing*2,xlp_ex2_wrb")
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100
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101 (define_insn_reservation "ir_xlp_div" 24
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102 (and (eq_attr "cpu" "xlp")
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103 (eq_attr "mode" "SI")
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104 (eq_attr "type" "idiv"))
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105 "xlp_ex2+xlp_div,xlp_div*23,xlp_ex2_wrb")
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106
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107 (define_insn_reservation "ir_xlp_ddiv" 48
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108 (and (eq_attr "cpu" "xlp")
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109 (eq_attr "mode" "DI")
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110 (eq_attr "type" "idiv"))
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111 "xlp_ex2+xlp_div,xlp_div*47,xlp_ex2_wrb")
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112
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113 (define_insn_reservation "ir_xlp_store" 1
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114 (and (eq_attr "cpu" "xlp")
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115 (eq_attr "type" "store,fpstore,fpidxstore"))
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116 "xlp_ex0|xlp_ex1")
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117
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118 (define_insn_reservation "ir_xlp_fpmove" 2
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119 (and (eq_attr "cpu" "xlp")
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120 (eq_attr "type" "mfc"))
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121 "xlp_ex3,xlp_fp,xlp_fp_wrb")
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122
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123 (define_insn_reservation "ir_xlp_mfhi" 1
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124 (and (eq_attr "cpu" "xlp")
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125 (eq_attr "type" "mfhi"))
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126 "xlp_ex2,xlp_ex2_wrb")
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127
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128 (define_insn_reservation "ir_xlp_mflo" 1
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129 (and (eq_attr "cpu" "xlp")
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130 (eq_attr "type" "mflo"))
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131 "xlp_ex2,xlp_ex2_wrb")
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132
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133 (define_insn_reservation "ir_xlp_mthi" 1
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134 (and (eq_attr "cpu" "xlp")
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135 (eq_attr "type" "mthi"))
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136 "xlp_ex2,xlp_ex2_wrb")
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137
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138 (define_insn_reservation "ir_xlp_mtlo" 3
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139 (and (eq_attr "cpu" "xlp")
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140 (eq_attr "type" "mtlo"))
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141 "xlp_ex2,nothing*2,xlp_ex2_wrb")
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142
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143 (define_insn_reservation "ir_xlp_fp2" 2
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144 (and (eq_attr "cpu" "xlp")
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145 (eq_attr "type" "fmove,fneg,fabs,condmove"))
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146 "xlp_fp,nothing,xlp_fp_wrb")
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147
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148 (define_insn_reservation "ir_xlp_fp3" 3
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149 (and (eq_attr "cpu" "xlp")
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150 (eq_attr "type" "fcmp"))
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151 "xlp_fp,nothing*2,xlp_fp_wrb")
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152
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153 (define_insn_reservation "ir_xlp_fp4" 4
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154 (and (eq_attr "cpu" "xlp")
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155 (eq_attr "type" "fcvt"))
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156 "xlp_fp,nothing*3,xlp_fp_wrb")
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157
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158 (define_insn_reservation "ir_xlp_fp5" 5
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159 (and (eq_attr "cpu" "xlp")
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160 (eq_attr "mode" "SF")
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161 (eq_attr "type" "fadd,fmul"))
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162 "xlp_fp,nothing*4,xlp_fp_wrb")
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163
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164 (define_insn_reservation "ir_xlp_fp6" 6
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165 (and (eq_attr "cpu" "xlp")
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166 (eq_attr "mode" "DF")
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167 (eq_attr "type" "fadd,fmul"))
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168 "xlp_fp,nothing*5,xlp_fp_wrb")
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169
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170 (define_insn_reservation "ir_xlp_fp9" 9
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171 (and (eq_attr "cpu" "xlp")
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172 (eq_attr "mode" "SF")
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173 (eq_attr "type" "fmadd"))
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174 "xlp_fp,nothing*3,xlp_fp,nothing*3,xlp_fp_wrb")
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175
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176 (define_insn_reservation "ir_xlp_fp11" 11
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177 (and (eq_attr "cpu" "xlp")
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178 (eq_attr "mode" "DF")
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179 (eq_attr "type" "fmadd"))
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180 "xlp_fp,nothing*4,xlp_fp,nothing*4,xlp_fp_wrb")
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181
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182 (define_insn_reservation "ir_xlp_fpcomplex_s" 23
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183 (and (eq_attr "cpu" "xlp")
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184 (eq_attr "mode" "SF")
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185 (eq_attr "type" "fdiv,frdiv,frdiv1,frdiv2,fsqrt,frsqrt,frsqrt1,frsqrt2"))
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186 "xlp_fp+xlp_divsq,xlp_divsq*22,xlp_fp_wrb")
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187
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188 (define_insn_reservation "ir_xlp_fpcomplex_d" 38
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189 (and (eq_attr "cpu" "xlp")
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190 (eq_attr "mode" "DF")
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191 (eq_attr "type" "fdiv,frdiv,frdiv1,frdiv2,fsqrt,frsqrt,frsqrt1,frsqrt2"))
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192 "xlp_fp+xlp_divsq,xlp_divsq*37,xlp_fp_wrb")
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193
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194 (define_bypass 3 "ir_xlp_mul" "ir_xlp_mfhi")
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195
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196 (define_insn_reservation "ir_xlp_atomic" 15
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197 (and (eq_attr "cpu" "xlp")
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198 (eq_attr "type" "atomic"))
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199 "xlp_ex0|xlp_ex1")
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200
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201 ;; Sync loop consists of (in order)
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202 ;; (1) optional sync,
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203 ;; (2) LL instruction,
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204 ;; (3) branch and 1-2 ALU instructions,
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205 ;; (4) SC instruction,
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206 ;; (5) optional sync,
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207 ;; (6) branch and ALU instruction.
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208 ;; The net result of this reservation is a big delay with flush of
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209 ;; ALU pipeline and outgoing reservations discouraging use of EX3.
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210 (define_insn_reservation "ir_xlp_sync_loop" 40
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211 (and (eq_attr "cpu" "xlp")
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212 (eq_attr "type" "syncloop"))
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213 "(xlp_ex0+xlp_ex1+xlp_ex2+xlp_ex3)*39,xlp_ex3+(xlp_ex0|xlp_ex1|(xlp_ex2,xlp_ex2_wrb))")
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