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111
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1 ;; Constraint definitions of Andes NDS32 cpu for GNU compiler
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2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
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3 ;; Contributed by Andes Technology Corporation.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Check 16.8.7 Defining Machine-Specific Constraints for detail.
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22
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23 ;; NO contrains can be prefixed with: E F V X g i m n o p r s
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24 ;; Machine-dependent integer: I J K L M N O P
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25 ;; Machine-dependent floating: G H
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26
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27
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28 (define_register_constraint "w" "(TARGET_ISA_V3 || TARGET_ISA_V3M) ? LOW_REGS : NO_REGS"
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29 "LOW register class $r0 ~ $r7 constraint for V3/V3M ISA")
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30
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31 (define_register_constraint "l" "LOW_REGS"
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32 "LOW register class $r0 ~ $r7")
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33
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34 (define_register_constraint "d" "MIDDLE_REGS"
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35 "MIDDLE register class $r0 ~ $r11, $r16 ~ $r19")
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36
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37 (define_register_constraint "h" "HIGH_REGS"
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38 "HIGH register class $r12 ~ $r14, $r20 ~ $r31")
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39
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40
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41 (define_register_constraint "t" "R15_TA_REG"
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42 "Temporary Assist register $ta (i.e. $r15)")
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43
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44 (define_register_constraint "k" "STACK_REG"
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45 "Stack register $sp")
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46
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47
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48 (define_constraint "Iu03"
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49 "Unsigned immediate 3-bit value"
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50 (and (match_code "const_int")
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51 (match_test "ival < (1 << 3) && ival >= 0")))
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52
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53 (define_constraint "In03"
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54 "Negative immediate 3-bit value in the range of -7 to 0"
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55 (and (match_code "const_int")
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56 (match_test "IN_RANGE (ival, -7, 0)")))
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57
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58 (define_constraint "Iu04"
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59 "Unsigned immediate 4-bit value"
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60 (and (match_code "const_int")
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61 (match_test "ival < (1 << 4) && ival >= 0")))
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62
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63 (define_constraint "Is05"
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64 "Signed immediate 5-bit value"
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65 (and (match_code "const_int")
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66 (match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
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67
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68 (define_constraint "Iu05"
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69 "Unsigned immediate 5-bit value"
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70 (and (match_code "const_int")
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71 (match_test "ival < (1 << 5) && ival >= 0")))
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72
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73 (define_constraint "In05"
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74 "Negative immediate 5-bit value in the range of -31 to 0"
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75 (and (match_code "const_int")
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76 (match_test "IN_RANGE (ival, -31, 0)")))
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77
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78 ;; Ip05 is special and dedicated for v3 movpi45 instruction.
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79 ;; movpi45 has imm5u field but the range is 16 ~ 47.
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80 (define_constraint "Ip05"
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81 "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
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82 (and (match_code "const_int")
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83 (match_test "ival < ((1 << 5) + 16)
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84 && ival >= (0 + 16)
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85 && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
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86
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87 (define_constraint "Iu06"
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88 "Unsigned immediate 6-bit value constraint for addri36.sp instruction"
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89 (and (match_code "const_int")
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90 (match_test "ival < (1 << 6)
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91 && ival >= 0
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92 && (ival % 4 == 0)
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93 && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
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94
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95 (define_constraint "Iu08"
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96 "Unsigned immediate 8-bit value"
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97 (and (match_code "const_int")
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98 (match_test "ival < (1 << 8) && ival >= 0")))
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99
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100 (define_constraint "Iu09"
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101 "Unsigned immediate 9-bit value"
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102 (and (match_code "const_int")
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103 (match_test "ival < (1 << 9) && ival >= 0")))
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104
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105
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106 (define_constraint "Is10"
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107 "Signed immediate 10-bit value"
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108 (and (match_code "const_int")
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109 (match_test "ival < (1 << 9) && ival >= -(1 << 9)")))
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110
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111 (define_constraint "Is11"
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112 "Signed immediate 11-bit value"
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113 (and (match_code "const_int")
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114 (match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
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115
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116
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117 (define_constraint "Is15"
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118 "Signed immediate 15-bit value"
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119 (and (match_code "const_int")
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120 (match_test "ival < (1 << 14) && ival >= -(1 << 14)")))
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121
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122 (define_constraint "Iu15"
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123 "Unsigned immediate 15-bit value"
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124 (and (match_code "const_int")
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125 (match_test "ival < (1 << 15) && ival >= 0")))
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126
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127
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128 ;; Ic15 is special and dedicated for performance extension
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129 ;; 'bclr' (single-bit-clear) instruction.
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130 ;; It is used in andsi3 pattern and recognized for the immediate
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131 ;; which is NOT in the range of imm15u but OK for 'bclr' instruction.
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132 ;; (If the immediate value IS in the range of imm15u,
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133 ;; we can directly use 'andi' instruction.)
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134 (define_constraint "Ic15"
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135 "A constant which is not in the range of imm15u but ok for bclr instruction"
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136 (and (match_code "const_int")
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137 (match_test "(ival & 0xffff8000) && nds32_can_use_bclr_p (ival)")))
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138
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139 ;; Ie15 is special and dedicated for performance extension
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140 ;; 'bset' (single-bit-set) instruction.
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141 ;; It is used in iorsi3 pattern and recognized for the immediate
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142 ;; which is NOT in the range of imm15u but OK for 'bset' instruction.
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143 ;; (If the immediate value IS in the range of imm15u,
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144 ;; we can directly use 'ori' instruction.)
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145 (define_constraint "Ie15"
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146 "A constant which is not in the range of imm15u but ok for bset instruction"
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147 (and (match_code "const_int")
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148 (match_test "(ival & 0xffff8000) && nds32_can_use_bset_p (ival)")))
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149
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150 ;; It15 is special and dedicated for performance extension
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151 ;; 'btgl' (single-bit-toggle) instruction.
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152 ;; It is used in xorsi3 pattern and recognized for the immediate
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153 ;; which is NOT in the range of imm15u but OK for 'btgl' instruction.
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154 ;; (If the immediate value IS in the range of imm15u,
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155 ;; we can directly use 'xori' instruction.)
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156 (define_constraint "It15"
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157 "A constant which is not in the range of imm15u but ok for btgl instruction"
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158 (and (match_code "const_int")
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159 (match_test "(ival & 0xffff8000) && nds32_can_use_btgl_p (ival)")))
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160
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161
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162 ;; Ii15 is special and dedicated for v3 isa
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163 ;; 'bitci' (bit-clear-immediate) instruction.
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164 ;; It is used in andsi3 pattern and recognized for the immediate whose
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165 ;; (~ival) value is in the range of imm15u and OK for 'bitci' instruction.
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166 ;; For example, 'andi $r0,$r0,0xfffffffc' can be presented
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167 ; with 'bitci $r0,$r0,3'.
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168 (define_constraint "Ii15"
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169 "A constant whose compliment value is in the range of imm15u
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170 and ok for bitci instruction"
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171 (and (match_code "const_int")
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172 (match_test "nds32_can_use_bitci_p (ival)")))
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173
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174
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175 (define_constraint "Is16"
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176 "Signed immediate 16-bit value"
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177 (and (match_code "const_int")
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178 (match_test "ival < (1 << 15) && ival >= -(1 << 15)")))
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179
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180 (define_constraint "Is17"
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181 "Signed immediate 17-bit value"
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182 (and (match_code "const_int")
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183 (match_test "ival < (1 << 16) && ival >= -(1 << 16)")))
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184
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185
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186 (define_constraint "Is19"
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187 "Signed immediate 19-bit value"
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188 (and (match_code "const_int")
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189 (match_test "ival < (1 << 18) && ival >= -(1 << 18)")))
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190
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191
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192 (define_constraint "Is20"
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193 "Signed immediate 20-bit value"
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194 (and (match_code "const_int")
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195 (match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
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196
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197
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198 (define_constraint "Ihig"
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199 "The immediate value that can be simply set high 20-bit"
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200 (and (match_code "const_int")
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201 (match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
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202
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203 (define_constraint "Izeb"
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204 "The immediate value 0xff"
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205 (and (match_code "const_int")
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206 (match_test "(ival == 0xff)")))
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207
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208 (define_constraint "Izeh"
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209 "The immediate value 0xffff"
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210 (and (match_code "const_int")
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211 (match_test "(ival == 0xffff)")))
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212
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213 (define_constraint "Ixls"
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214 "The immediate value 0x01"
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215 (and (match_code "const_int")
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216 (match_test "TARGET_PERF_EXT && (ival == 0x1)")))
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217
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218 (define_constraint "Ix11"
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219 "The immediate value 0x7ff"
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220 (and (match_code "const_int")
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221 (match_test "TARGET_PERF_EXT && (ival == 0x7ff)")))
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222
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223 (define_constraint "Ibms"
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224 "The immediate value with power of 2"
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225 (and (match_code "const_int")
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226 (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
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227 && (IN_RANGE (exact_log2 (ival), 0, 7))")))
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228
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229 (define_constraint "Ifex"
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230 "The immediate value with power of 2 minus 1"
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231 (and (match_code "const_int")
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232 (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
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233 && (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
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234
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235
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236 (define_memory_constraint "U33"
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237 "Memory constraint for 333 format"
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238 (and (match_code "mem")
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239 (match_test "nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
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240
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241 (define_memory_constraint "U45"
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242 "Memory constraint for 45 format"
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243 (and (match_code "mem")
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244 (match_test "(nds32_mem_format (op) == ADDRESS_REG)
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245 && (GET_MODE (op) == SImode)")))
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246
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247 (define_memory_constraint "U37"
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248 "Memory constraint for 37 format"
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249 (and (match_code "mem")
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250 (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
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251 || nds32_mem_format (op) == ADDRESS_FP_IMM7U)
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252 && (GET_MODE (op) == SImode)")))
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253
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254 ;; ------------------------------------------------------------------------
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