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1 ;; Load/Store Multiple patterns description of Andes NDS32 cpu for GNU compiler
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2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
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3 ;; Contributed by Andes Technology Corporation.for NDS32.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21
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22 ;; Load Multiple Insns.
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23 ;;
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24 ;; operands[0] is the first of the consecutive registers.
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25 ;; operands[1] is the first memory location.
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26 ;; operands[2] is the number of consecutive registers.
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27
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28 (define_expand "load_multiple"
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29 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
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30 (match_operand:SI 1 "" ""))
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31 (use (match_operand:SI 2 "" ""))])]
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32 ""
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33 {
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34 int maximum;
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35
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36 /* Because reduced-set regsiters has few registers
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37 (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot
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38 be used for register allocation),
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39 using 8 registers for load_multiple may easily consume all of them.
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40 It makes register allocation/spilling hard to work.
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41 So we only allow maximum=4 registers for load_multiple
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42 under reduced-set registers. */
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43 if (TARGET_REDUCED_REGS)
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44 maximum = 4;
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45 else
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46 maximum = 8;
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47
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48 /* Here are the conditions that must be all passed,
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49 otherwise we have to FAIL this rtx generation:
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50 1. The number of consecutive registers must be integer.
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51 2. Maximum 4 or 8 registers for lmw.bi instruction
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52 (based on this nds32-multiple.md design).
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53 3. Minimum 2 registers for lmw.bi instruction
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54 (based on this nds32-multiple.md design).
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55 4. operands[0] must be register for sure.
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56 5. operands[1] must be memory for sure.
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57 6. Do not cross $r15 register because it is not allocatable. */
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58 if (GET_CODE (operands[2]) != CONST_INT
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59 || INTVAL (operands[2]) > maximum
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60 || INTVAL (operands[2]) < 2
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61 || GET_CODE (operands[0]) != REG
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62 || GET_CODE (operands[1]) != MEM
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63 || REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM)
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64 FAIL;
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65
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66 /* For (mem addr), we force_reg on addr here,
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67 so that nds32_expand_load_multiple can easily use it. */
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68 operands[3] = nds32_expand_load_multiple (REGNO (operands[0]),
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69 INTVAL (operands[2]),
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70 force_reg (SImode,
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71 XEXP (operands[1], 0)),
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72 operands[1]);
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73 })
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74
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75 ;; Ordinary Load Multiple.
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76
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77 (define_insn "*lmwsi8"
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78 [(match_parallel 0 "nds32_load_multiple_operation"
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79 [(set (match_operand:SI 2 "register_operand" "")
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80 (mem:SI (match_operand:SI 1 "register_operand" "r")))
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81 (set (match_operand:SI 3 "register_operand" "")
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82 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
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83 (set (match_operand:SI 4 "register_operand" "")
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84 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
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85 (set (match_operand:SI 5 "register_operand" "")
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86 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
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87 (set (match_operand:SI 6 "register_operand" "")
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88 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
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89 (set (match_operand:SI 7 "register_operand" "")
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90 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
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91 (set (match_operand:SI 8 "register_operand" "")
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92 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
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93 (set (match_operand:SI 9 "register_operand" "")
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94 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
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95 "(XVECLEN (operands[0], 0) == 8)"
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96 "lmw.bi\t%2, [%1], %9, 0x0"
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97 [(set_attr "type" "load")
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98 (set_attr "length" "4")]
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99 )
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100
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101 (define_insn "*lmwsi7"
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102 [(match_parallel 0 "nds32_load_multiple_operation"
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103 [(set (match_operand:SI 2 "register_operand" "")
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104 (mem:SI (match_operand:SI 1 "register_operand" "r")))
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105 (set (match_operand:SI 3 "register_operand" "")
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106 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
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107 (set (match_operand:SI 4 "register_operand" "")
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108 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
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109 (set (match_operand:SI 5 "register_operand" "")
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110 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
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111 (set (match_operand:SI 6 "register_operand" "")
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112 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
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113 (set (match_operand:SI 7 "register_operand" "")
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114 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
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115 (set (match_operand:SI 8 "register_operand" "")
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116 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
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117 "(XVECLEN (operands[0], 0) == 7)"
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118 "lmw.bi\t%2, [%1], %8, 0x0"
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119 [(set_attr "type" "load")
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120 (set_attr "length" "4")]
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121 )
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122
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123 (define_insn "*lmwsi6"
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124 [(match_parallel 0 "nds32_load_multiple_operation"
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125 [(set (match_operand:SI 2 "register_operand" "")
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126 (mem:SI (match_operand:SI 1 "register_operand" "r")))
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127 (set (match_operand:SI 3 "register_operand" "")
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128 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
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129 (set (match_operand:SI 4 "register_operand" "")
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130 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
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131 (set (match_operand:SI 5 "register_operand" "")
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132 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
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133 (set (match_operand:SI 6 "register_operand" "")
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134 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
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135 (set (match_operand:SI 7 "register_operand" "")
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136 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
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137 "(XVECLEN (operands[0], 0) == 6)"
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138 "lmw.bi\t%2, [%1], %7, 0x0"
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139 [(set_attr "type" "load")
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140 (set_attr "length" "4")]
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141 )
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142
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143 (define_insn "*lmwsi5"
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144 [(match_parallel 0 "nds32_load_multiple_operation"
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145 [(set (match_operand:SI 2 "register_operand" "")
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146 (mem:SI (match_operand:SI 1 "register_operand" "r")))
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147 (set (match_operand:SI 3 "register_operand" "")
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148 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
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149 (set (match_operand:SI 4 "register_operand" "")
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150 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
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151 (set (match_operand:SI 5 "register_operand" "")
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152 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
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153 (set (match_operand:SI 6 "register_operand" "")
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154 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
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155 "(XVECLEN (operands[0], 0) == 5)"
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156 "lmw.bi\t%2, [%1], %6, 0x0"
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157 [(set_attr "type" "load")
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158 (set_attr "length" "4")]
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159 )
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160
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161 (define_insn "*lmwsi4"
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162 [(match_parallel 0 "nds32_load_multiple_operation"
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163 [(set (match_operand:SI 2 "register_operand" "")
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164 (mem:SI (match_operand:SI 1 "register_operand" "r")))
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165 (set (match_operand:SI 3 "register_operand" "")
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166 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
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167 (set (match_operand:SI 4 "register_operand" "")
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168 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
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169 (set (match_operand:SI 5 "register_operand" "")
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170 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
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171 "(XVECLEN (operands[0], 0) == 4)"
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172 "lmw.bi\t%2, [%1], %5, 0x0"
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173 [(set_attr "type" "load")
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174 (set_attr "length" "4")]
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175 )
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176
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177 (define_insn "*lmwsi3"
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178 [(match_parallel 0 "nds32_load_multiple_operation"
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179 [(set (match_operand:SI 2 "register_operand" "")
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180 (mem:SI (match_operand:SI 1 "register_operand" "r")))
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181 (set (match_operand:SI 3 "register_operand" "")
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182 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
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183 (set (match_operand:SI 4 "register_operand" "")
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184 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
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185 "(XVECLEN (operands[0], 0) == 3)"
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186 "lmw.bi\t%2, [%1], %4, 0x0"
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187 [(set_attr "type" "load")
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188 (set_attr "length" "4")]
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189 )
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190
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191 (define_insn "*lmwsi2"
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192 [(match_parallel 0 "nds32_load_multiple_operation"
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193 [(set (match_operand:SI 2 "register_operand" "")
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194 (mem:SI (match_operand:SI 1 "register_operand" "r")))
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195 (set (match_operand:SI 3 "register_operand" "")
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196 (mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
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197 "(XVECLEN (operands[0], 0) == 2)"
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198 "lmw.bi\t%2, [%1], %3, 0x0"
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199 [(set_attr "type" "load")
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200 (set_attr "length" "4")]
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201 )
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202
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203
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204 ;; Store Multiple Insns.
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205 ;;
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206 ;; operands[0] is the first memory location.
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207 ;; opernads[1] is the first of the consecutive registers.
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208 ;; operands[2] is the number of consecutive registers.
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209
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210 (define_expand "store_multiple"
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211 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
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212 (match_operand:SI 1 "" ""))
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213 (use (match_operand:SI 2 "" ""))])]
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214 ""
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215 {
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216 int maximum;
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217
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218 /* Because reduced-set regsiters has few registers
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219 (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot
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220 be used for register allocation),
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221 using 8 registers for store_multiple may easily consume all of them.
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222 It makes register allocation/spilling hard to work.
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223 So we only allow maximum=4 registers for store_multiple
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224 under reduced-set registers. */
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225 if (TARGET_REDUCED_REGS)
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226 maximum = 4;
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227 else
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228 maximum = 8;
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229
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230 /* Here are the conditions that must be all passed,
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231 otherwise we have to FAIL this rtx generation:
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232 1. The number of consecutive registers must be integer.
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233 2. Maximum 4 or 8 registers for smw.bi instruction
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234 (based on this nds32-multiple.md design).
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235 3. Minimum 2 registers for smw.bi instruction
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236 (based on this nds32-multiple.md design).
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237 4. operands[0] must be memory for sure.
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238 5. operands[1] must be register for sure.
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239 6. Do not cross $r15 register because it is not allocatable. */
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240 if (GET_CODE (operands[2]) != CONST_INT
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241 || INTVAL (operands[2]) > maximum
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242 || INTVAL (operands[2]) < 2
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243 || GET_CODE (operands[0]) != MEM
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244 || GET_CODE (operands[1]) != REG
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245 || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
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246 FAIL;
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247
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248 /* For (mem addr), we force_reg on addr here,
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249 so that nds32_expand_store_multiple can easily use it. */
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250 operands[3] = nds32_expand_store_multiple (REGNO (operands[1]),
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251 INTVAL (operands[2]),
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252 force_reg (SImode,
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253 XEXP (operands[0], 0)),
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254 operands[0]);
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255 })
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256
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257 ;; Ordinary Store Multiple.
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258
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259 (define_insn "*stmsi8"
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260 [(match_parallel 0 "nds32_store_multiple_operation"
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261 [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
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262 (match_operand:SI 2 "register_operand" ""))
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263 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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264 (match_operand:SI 3 "register_operand" ""))
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265 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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266 (match_operand:SI 4 "register_operand" ""))
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267 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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268 (match_operand:SI 5 "register_operand" ""))
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269 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
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270 (match_operand:SI 6 "register_operand" ""))
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271 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
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272 (match_operand:SI 7 "register_operand" ""))
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273 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
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274 (match_operand:SI 8 "register_operand" ""))
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275 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
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276 (match_operand:SI 9 "register_operand" ""))])]
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277 "(XVECLEN (operands[0], 0) == 8)"
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278 "smw.bi\t%2, [%1], %9, 0x0"
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279 [(set_attr "type" "store")
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280 (set_attr "length" "4")]
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281 )
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282
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283 (define_insn "*stmsi7"
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284 [(match_parallel 0 "nds32_store_multiple_operation"
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285 [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
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286 (match_operand:SI 2 "register_operand" ""))
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287 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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288 (match_operand:SI 3 "register_operand" ""))
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289 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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290 (match_operand:SI 4 "register_operand" ""))
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291 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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292 (match_operand:SI 5 "register_operand" ""))
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293 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
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294 (match_operand:SI 6 "register_operand" ""))
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295 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
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296 (match_operand:SI 7 "register_operand" ""))
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297 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
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298 (match_operand:SI 8 "register_operand" ""))])]
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299 "(XVECLEN (operands[0], 0) == 7)"
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300 "smw.bi\t%2, [%1], %8, 0x0"
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301 [(set_attr "type" "store")
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302 (set_attr "length" "4")]
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303 )
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304
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305 (define_insn "*stmsi6"
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306 [(match_parallel 0 "nds32_store_multiple_operation"
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307 [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
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308 (match_operand:SI 2 "register_operand" ""))
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309 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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310 (match_operand:SI 3 "register_operand" ""))
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311 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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312 (match_operand:SI 4 "register_operand" ""))
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313 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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314 (match_operand:SI 5 "register_operand" ""))
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315 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
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316 (match_operand:SI 6 "register_operand" ""))
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317 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
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318 (match_operand:SI 7 "register_operand" ""))])]
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319 "(XVECLEN (operands[0], 0) == 6)"
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320 "smw.bi\t%2, [%1], %7, 0x0"
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321 [(set_attr "type" "store")
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322 (set_attr "length" "4")]
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323 )
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324
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325 (define_insn "*stmsi5"
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326 [(match_parallel 0 "nds32_store_multiple_operation"
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327 [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
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328 (match_operand:SI 2 "register_operand" ""))
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329 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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330 (match_operand:SI 3 "register_operand" ""))
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331 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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332 (match_operand:SI 4 "register_operand" ""))
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333 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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334 (match_operand:SI 5 "register_operand" ""))
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335 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
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336 (match_operand:SI 6 "register_operand" ""))])]
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337 "(XVECLEN (operands[0], 0) == 5)"
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338 "smw.bi\t%2, [%1], %6, 0x0"
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339 [(set_attr "type" "store")
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340 (set_attr "length" "4")]
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341 )
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342
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343 (define_insn "*stmsi4"
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344 [(match_parallel 0 "nds32_store_multiple_operation"
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345 [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
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346 (match_operand:SI 2 "register_operand" ""))
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347 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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348 (match_operand:SI 3 "register_operand" ""))
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349 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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350 (match_operand:SI 4 "register_operand" ""))
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351 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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352 (match_operand:SI 5 "register_operand" ""))])]
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353 "(XVECLEN (operands[0], 0) == 4)"
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354 "smw.bi\t%2, [%1], %5, 0x0"
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355 [(set_attr "type" "store")
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356 (set_attr "length" "4")]
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357 )
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358
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359 (define_insn "*stmsi3"
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360 [(match_parallel 0 "nds32_store_multiple_operation"
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361 [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
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362 (match_operand:SI 2 "register_operand" ""))
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363 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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364 (match_operand:SI 3 "register_operand" ""))
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365 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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366 (match_operand:SI 4 "register_operand" ""))])]
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367 "(XVECLEN (operands[0], 0) == 3)"
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368 "smw.bi\t%2, [%1], %4, 0x0"
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369 [(set_attr "type" "store")
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370 (set_attr "length" "4")]
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371 )
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372
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373 (define_insn "*stmsi2"
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374 [(match_parallel 0 "nds32_store_multiple_operation"
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375 [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
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376 (match_operand:SI 2 "register_operand" ""))
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377 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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378 (match_operand:SI 3 "register_operand" ""))])]
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379 "(XVECLEN (operands[0], 0) == 2)"
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380 "smw.bi\t%2, [%1], %3, 0x0"
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381 [(set_attr "type" "store")
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382 (set_attr "length" "4")]
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383 )
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384
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385 ;; Move a block of memory if it is word aligned and MORE than 2 words long.
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386 ;; We could let this apply for blocks of less than this, but it clobbers so
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387 ;; many registers that there is then probably a better way.
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388 ;;
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389 ;; operands[0] is the destination block of memory.
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390 ;; operands[1] is the source block of memory.
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391 ;; operands[2] is the number of bytes to move.
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392 ;; operands[3] is the known shared alignment.
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393
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394 (define_expand "movmemqi"
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395 [(match_operand:BLK 0 "general_operand" "")
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396 (match_operand:BLK 1 "general_operand" "")
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397 (match_operand:SI 2 "const_int_operand" "")
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398 (match_operand:SI 3 "const_int_operand" "")]
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399 ""
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400 {
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401 if (nds32_expand_movmemqi (operands[0],
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402 operands[1],
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403 operands[2],
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404 operands[3]))
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405 DONE;
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406
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407 FAIL;
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408 })
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409
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410 ;; ------------------------------------------------------------------------
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