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111
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1 /* Predicate functions of Andes NDS32 cpu for GNU compiler
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2 Copyright (C) 2012-2017 Free Software Foundation, Inc.
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3 Contributed by Andes Technology Corporation.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* ------------------------------------------------------------------------ */
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22
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23 #include "config.h"
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24 #include "system.h"
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25 #include "coretypes.h"
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26 #include "backend.h"
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27 #include "target.h"
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28 #include "rtl.h"
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29 #include "tree.h"
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30 #include "memmodel.h"
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31 #include "tm_p.h"
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32 #include "optabs.h" /* For GEN_FCN. */
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33 #include "emit-rtl.h"
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34 #include "recog.h"
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35 #include "tm-constrs.h"
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36
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37 /* ------------------------------------------------------------------------ */
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38
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39 /* A subroutine that checks multiple load and store
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40 using consecutive registers.
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41 OP is a parallel rtx we would like to check.
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42 LOAD_P indicates whether we are checking load operation.
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43 PAR_INDEX is starting element of parallel rtx.
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44 FIRST_ELT_REGNO is used to tell starting register number.
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45 COUNT helps us to check consecutive register numbers. */
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46 static bool
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47 nds32_consecutive_registers_load_store_p (rtx op,
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48 bool load_p,
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49 int par_index,
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50 int first_elt_regno,
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51 int count)
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52 {
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53 int i;
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54 int check_regno;
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55 rtx elt;
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56 rtx elt_reg;
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57 rtx elt_mem;
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58
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59 for (i = 0; i < count; i++)
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60 {
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61 /* Pick up each element from parallel rtx. */
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62 elt = XVECEXP (op, 0, i + par_index);
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63
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64 /* If this element is not a 'set' rtx, return false immediately. */
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65 if (GET_CODE (elt) != SET)
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66 return false;
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67
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68 /* Pick up reg and mem of this element. */
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69 elt_reg = load_p ? SET_DEST (elt) : SET_SRC (elt);
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70 elt_mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
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71
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72 /* If elt_reg is not a expected reg rtx, return false. */
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73 if (GET_CODE (elt_reg) != REG || GET_MODE (elt_reg) != SImode)
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74 return false;
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75 /* If elt_mem is not a expected mem rtx, return false. */
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76 if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
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77 return false;
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78
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79 /* The consecutive registers should be in (Rb,Rb+1...Re) order. */
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80 check_regno = first_elt_regno + i;
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81
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82 /* If the register number is not continuous, return false. */
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83 if (REGNO (elt_reg) != (unsigned int) check_regno)
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84 return false;
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85 }
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86
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87 return true;
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88 }
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89
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90 /* Function to check whether the OP is a valid load/store operation.
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91 This is a helper function for the predicates:
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92 'nds32_load_multiple_operation' and 'nds32_store_multiple_operation'
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93 in predicates.md file.
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94
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95 The OP is supposed to be a parallel rtx.
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96 For each element within this parallel rtx:
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97 (set (reg) (mem addr)) is the form for load operation.
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98 (set (mem addr) (reg)) is the form for store operation.
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99 We have to extract reg and mem of every element and
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100 check if the information is valid for multiple load/store operation. */
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101 bool
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102 nds32_valid_multiple_load_store (rtx op, bool load_p)
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103 {
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104 int count;
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105 int first_elt_regno;
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106 rtx elt;
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107
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108 /* Get the counts of elements in the parallel rtx. */
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109 count = XVECLEN (op, 0);
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110 /* Pick up the first element. */
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111 elt = XVECEXP (op, 0, 0);
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112
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113 /* Perform some quick check for the first element in the parallel rtx. */
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114 if (GET_CODE (elt) != SET
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115 || count <= 1
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116 || count > 8)
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117 return false;
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118
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119 /* Pick up regno of first element for further detail checking.
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120 Note that the form is different between load and store operation. */
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121 if (load_p)
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122 {
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123 if (GET_CODE (SET_DEST (elt)) != REG
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124 || GET_CODE (SET_SRC (elt)) != MEM)
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125 return false;
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126
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127 first_elt_regno = REGNO (SET_DEST (elt));
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128 }
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129 else
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130 {
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131 if (GET_CODE (SET_SRC (elt)) != REG
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132 || GET_CODE (SET_DEST (elt)) != MEM)
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133 return false;
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134
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135 first_elt_regno = REGNO (SET_SRC (elt));
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136 }
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137
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138 /* Perform detail check for each element.
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139 Refer to nds32-multiple.md for more information
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140 about following checking.
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141 The starting element of parallel rtx is index 0. */
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142 if (!nds32_consecutive_registers_load_store_p (op, load_p, 0,
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143 first_elt_regno,
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144 count))
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145 return false;
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146
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147 /* Pass all test, this is a valid rtx. */
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148 return true;
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149 }
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150
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151 /* Function to check whether the OP is a valid stack push/pop operation.
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152 For a valid stack operation, it must satisfy following conditions:
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153 1. Consecutive registers push/pop operations.
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154 2. Valid $fp/$gp/$lp push/pop operations.
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155 3. The last element must be stack adjustment rtx.
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156 See the prologue/epilogue implementation for details. */
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157 bool
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158 nds32_valid_stack_push_pop_p (rtx op, bool push_p)
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159 {
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160 int index;
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161 int total_count;
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162 int rest_count;
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163 int first_regno;
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164 int save_fp, save_gp, save_lp;
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165 rtx elt;
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166 rtx elt_reg;
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167 rtx elt_mem;
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168 rtx elt_plus;
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169
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170 /* Get the counts of elements in the parallel rtx. */
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171 total_count = XVECLEN (op, 0);
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172
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173 /* Perform some quick check for that every element should be 'set'. */
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174 for (index = 0; index < total_count; index++)
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175 {
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176 elt = XVECEXP (op, 0, index);
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177 if (GET_CODE (elt) != SET)
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178 return false;
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179 }
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180
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181 /* For push operation, the parallel rtx looks like:
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182 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
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183 (reg:SI Rb))
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184 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
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185 (reg:SI Rb+1))
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186 ...
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187 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
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188 (reg:SI Re))
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189 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
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190 (reg:SI FP_REGNUM))
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191 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
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192 (reg:SI GP_REGNUM))
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193 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
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194 (reg:SI LP_REGNUM))
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195 (set (reg:SI SP_REGNUM)
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196 (plus (reg:SI SP_REGNUM) (const_int -32)))])
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197
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198 For pop operation, the parallel rtx looks like:
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199 (parallel [(set (reg:SI Rb)
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200 (mem (reg:SI SP_REGNUM)))
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201 (set (reg:SI Rb+1)
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202 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
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203 ...
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204 (set (reg:SI Re)
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205 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
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206 (set (reg:SI FP_REGNUM)
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207 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
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208 (set (reg:SI GP_REGNUM)
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209 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
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210 (set (reg:SI LP_REGNUM)
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211 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
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212 (set (reg:SI SP_REGNUM)
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213 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
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214
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215 /* 1. Consecutive registers push/pop operations.
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216 We need to calculate how many registers should be consecutive.
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217 The $sp adjustment rtx, $fp push rtx, $gp push rtx,
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218 and $lp push rtx are excluded. */
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219
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220 /* Detect whether we have $fp, $gp, or $lp in the parallel rtx. */
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221 save_fp = reg_mentioned_p (gen_rtx_REG (SImode, FP_REGNUM), op);
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222 save_gp = reg_mentioned_p (gen_rtx_REG (SImode, GP_REGNUM), op);
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223 save_lp = reg_mentioned_p (gen_rtx_REG (SImode, LP_REGNUM), op);
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224 /* Exclude last $sp adjustment rtx. */
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225 rest_count = total_count - 1;
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226 /* Exclude $fp, $gp, and $lp if they are in the parallel rtx. */
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227 if (save_fp)
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228 rest_count--;
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229 if (save_gp)
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230 rest_count--;
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231 if (save_lp)
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232 rest_count--;
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233
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234 if (rest_count > 0)
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235 {
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236 elt = XVECEXP (op, 0, 0);
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237 /* Pick up register element. */
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238 elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
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239 first_regno = REGNO (elt_reg);
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240
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241 /* The 'push' operation is a kind of store operation.
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242 The 'pop' operation is a kind of load operation.
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243 Pass corresponding false/true as second argument (bool load_p).
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244 The par_index is supposed to start with index 0. */
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245 if (!nds32_consecutive_registers_load_store_p (op,
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246 !push_p ? true : false,
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247 0,
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248 first_regno,
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249 rest_count))
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250 return false;
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251 }
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252
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253 /* 2. Valid $fp/$gp/$lp push/pop operations.
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254 Remember to set start index for checking them. */
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255
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256 /* The rest_count is the start index for checking $fp/$gp/$lp. */
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257 index = rest_count;
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258 /* If index < 0, this parallel rtx is definitely
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259 not a valid stack push/pop operation. */
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260 if (index < 0)
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261 return false;
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262
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263 /* Check $fp/$gp/$lp one by one.
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264 We use 'push_p' to pick up reg rtx and mem rtx. */
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265 if (save_fp)
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266 {
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267 elt = XVECEXP (op, 0, index);
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268 elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
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269 elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
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270 index++;
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271
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272 if (GET_CODE (elt_mem) != MEM
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273 || GET_CODE (elt_reg) != REG
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274 || REGNO (elt_reg) != FP_REGNUM)
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275 return false;
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276 }
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277 if (save_gp)
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278 {
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279 elt = XVECEXP (op, 0, index);
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280 elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
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281 elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
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282 index++;
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283
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284 if (GET_CODE (elt_mem) != MEM
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285 || GET_CODE (elt_reg) != REG
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286 || REGNO (elt_reg) != GP_REGNUM)
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287 return false;
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288 }
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289 if (save_lp)
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290 {
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291 elt = XVECEXP (op, 0, index);
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292 elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
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293 elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
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294 index++;
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295
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296 if (GET_CODE (elt_mem) != MEM
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297 || GET_CODE (elt_reg) != REG
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298 || REGNO (elt_reg) != LP_REGNUM)
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299 return false;
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300 }
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301
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302 /* 3. The last element must be stack adjustment rtx.
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303 Its form of rtx should be:
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304 (set (reg:SI SP_REGNUM)
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305 (plus (reg:SI SP_REGNUM) (const_int X)))
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306 The X could be positive or negative value. */
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307
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308 /* Pick up the last element. */
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309 elt = XVECEXP (op, 0, total_count - 1);
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310
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311 /* Extract its destination and source rtx. */
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312 elt_reg = SET_DEST (elt);
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313 elt_plus = SET_SRC (elt);
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314
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315 /* Check this is (set (stack_reg) (plus stack_reg const)) pattern. */
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316 if (GET_CODE (elt_reg) != REG
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317 || GET_CODE (elt_plus) != PLUS
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318 || REGNO (elt_reg) != SP_REGNUM)
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319 return false;
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320
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321 /* Pass all test, this is a valid rtx. */
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322 return true;
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323 }
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324
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325 /* Function to check if 'bclr' instruction can be used with IVAL. */
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326 int
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327 nds32_can_use_bclr_p (int ival)
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328 {
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329 int one_bit_count;
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330
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331 /* Calculate the number of 1-bit of (~ival), if there is only one 1-bit,
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332 it means the original ival has only one 0-bit,
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333 So it is ok to perform 'bclr' operation. */
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334
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335 one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival));
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336
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337 /* 'bclr' is a performance extension instruction. */
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338 return (TARGET_PERF_EXT && (one_bit_count == 1));
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339 }
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340
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341 /* Function to check if 'bset' instruction can be used with IVAL. */
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342 int
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343 nds32_can_use_bset_p (int ival)
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344 {
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345 int one_bit_count;
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346
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347 /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
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348 it is ok to perform 'bset' operation. */
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349
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350 one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
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351
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352 /* 'bset' is a performance extension instruction. */
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353 return (TARGET_PERF_EXT && (one_bit_count == 1));
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354 }
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355
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356 /* Function to check if 'btgl' instruction can be used with IVAL. */
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357 int
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358 nds32_can_use_btgl_p (int ival)
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359 {
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360 int one_bit_count;
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361
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362 /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
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363 it is ok to perform 'btgl' operation. */
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364
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365 one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
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366
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367 /* 'btgl' is a performance extension instruction. */
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368 return (TARGET_PERF_EXT && (one_bit_count == 1));
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369 }
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370
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371 /* Function to check if 'bitci' instruction can be used with IVAL. */
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372 int
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373 nds32_can_use_bitci_p (int ival)
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374 {
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375 /* If we are using V3 ISA, we have 'bitci' instruction.
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376 Try to see if we can present 'andi' semantic with
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377 such 'bit-clear-immediate' operation.
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378 For example, 'andi $r0,$r0,0xfffffffc' can be
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379 presented with 'bitci $r0,$r0,3'. */
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380 return (TARGET_ISA_V3
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381 && (ival < 0)
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382 && satisfies_constraint_Iu15 (gen_int_mode (~ival, SImode)));
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383 }
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384
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385 /* ------------------------------------------------------------------------ */
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