Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/pdp11/pdp11.c @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | f6334be47118 |
| children | 84e7813d76e9 |
| rev | line source |
|---|---|
| 0 | 1 /* Subroutines for gcc2 for pdp11. |
| 111 | 2 Copyright (C) 1994-2017 Free Software Foundation, Inc. |
| 0 | 3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). |
| 4 | |
| 5 This file is part of GCC. | |
| 6 | |
| 7 GCC is free software; you can redistribute it and/or modify | |
| 8 it under the terms of the GNU General Public License as published by | |
| 9 the Free Software Foundation; either version 3, or (at your option) | |
| 10 any later version. | |
| 11 | |
| 12 GCC is distributed in the hope that it will be useful, | |
| 13 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 GNU General Public License for more details. | |
| 16 | |
| 17 You should have received a copy of the GNU General Public License | |
| 18 along with GCC; see the file COPYING3. If not see | |
| 19 <http://www.gnu.org/licenses/>. */ | |
| 20 | |
| 21 #include "config.h" | |
| 22 #include "system.h" | |
| 23 #include "coretypes.h" | |
| 111 | 24 #include "backend.h" |
| 25 #include "target.h" | |
| 0 | 26 #include "rtl.h" |
| 111 | 27 #include "tree.h" |
| 28 #include "stringpool.h" | |
| 29 #include "attribs.h" | |
| 30 #include "df.h" | |
| 31 #include "memmodel.h" | |
| 32 #include "tm_p.h" | |
| 33 #include "insn-config.h" | |
| 0 | 34 #include "regs.h" |
| 111 | 35 #include "emit-rtl.h" |
| 36 #include "recog.h" | |
| 0 | 37 #include "conditions.h" |
| 38 #include "output.h" | |
| 111 | 39 #include "stor-layout.h" |
| 40 #include "varasm.h" | |
| 41 #include "calls.h" | |
| 0 | 42 #include "expr.h" |
| 111 | 43 #include "builtins.h" |
| 44 #include "dbxout.h" | |
| 45 | |
| 46 /* This file should be included last. */ | |
| 0 | 47 #include "target-def.h" |
| 48 | |
| 49 /* this is the current value returned by the macro FIRST_PARM_OFFSET | |
| 50 defined in tm.h */ | |
| 51 int current_first_parm_offset; | |
| 52 | |
| 53 /* Routines to encode/decode pdp11 floats */ | |
| 54 static void encode_pdp11_f (const struct real_format *fmt, | |
| 55 long *, const REAL_VALUE_TYPE *); | |
| 56 static void decode_pdp11_f (const struct real_format *, | |
| 57 REAL_VALUE_TYPE *, const long *); | |
| 58 static void encode_pdp11_d (const struct real_format *fmt, | |
| 59 long *, const REAL_VALUE_TYPE *); | |
| 60 static void decode_pdp11_d (const struct real_format *, | |
| 61 REAL_VALUE_TYPE *, const long *); | |
| 62 | |
| 63 /* These two are taken from the corresponding vax descriptors | |
| 64 in real.c, changing only the encode/decode routine pointers. */ | |
| 65 const struct real_format pdp11_f_format = | |
| 66 { | |
| 67 encode_pdp11_f, | |
| 68 decode_pdp11_f, | |
| 69 2, | |
| 70 24, | |
| 71 24, | |
| 72 -127, | |
| 73 127, | |
| 74 15, | |
|
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75 15, |
| 111 | 76 0, |
| 0 | 77 false, |
| 78 false, | |
| 79 false, | |
| 80 false, | |
| 81 false, | |
| 82 false, | |
| 83 false, | |
| 111 | 84 false, |
| 85 "pdp11_f" | |
| 0 | 86 }; |
| 87 | |
| 88 const struct real_format pdp11_d_format = | |
| 89 { | |
| 90 encode_pdp11_d, | |
| 91 decode_pdp11_d, | |
| 92 2, | |
| 93 56, | |
| 94 56, | |
| 95 -127, | |
| 96 127, | |
| 97 15, | |
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98 15, |
| 111 | 99 0, |
| 0 | 100 false, |
| 101 false, | |
| 102 false, | |
| 103 false, | |
| 104 false, | |
| 105 false, | |
| 106 false, | |
| 111 | 107 false, |
| 108 "pdp11_d" | |
| 0 | 109 }; |
| 110 | |
| 111 static void | |
| 112 encode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf, | |
| 113 const REAL_VALUE_TYPE *r) | |
| 114 { | |
| 115 (*vax_f_format.encode) (fmt, buf, r); | |
| 116 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); | |
| 117 } | |
| 118 | |
| 119 static void | |
| 120 decode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, | |
| 121 REAL_VALUE_TYPE *r, const long *buf) | |
| 122 { | |
| 123 long tbuf; | |
| 124 tbuf = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); | |
| 125 (*vax_f_format.decode) (fmt, r, &tbuf); | |
| 126 } | |
| 127 | |
| 128 static void | |
| 129 encode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf, | |
| 130 const REAL_VALUE_TYPE *r) | |
| 131 { | |
| 132 (*vax_d_format.encode) (fmt, buf, r); | |
| 133 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); | |
| 134 buf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16); | |
| 135 } | |
| 136 | |
| 137 static void | |
| 138 decode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, | |
| 139 REAL_VALUE_TYPE *r, const long *buf) | |
| 140 { | |
| 141 long tbuf[2]; | |
| 142 tbuf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); | |
| 143 tbuf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16); | |
| 144 (*vax_d_format.decode) (fmt, r, tbuf); | |
| 145 } | |
| 146 | |
| 147 /* This is where the condition code register lives. */ | |
| 148 /* rtx cc0_reg_rtx; - no longer needed? */ | |
| 149 | |
| 150 static const char *singlemove_string (rtx *); | |
| 151 static bool pdp11_assemble_integer (rtx, unsigned int, int); | |
| 111 | 152 static bool pdp11_rtx_costs (rtx, machine_mode, int, int, int *, bool); |
| 0 | 153 static bool pdp11_return_in_memory (const_tree, const_tree); |
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154 static rtx pdp11_function_value (const_tree, const_tree, bool); |
| 111 | 155 static rtx pdp11_libcall_value (machine_mode, const_rtx); |
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156 static bool pdp11_function_value_regno_p (const unsigned int); |
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157 static void pdp11_trampoline_init (rtx, tree, rtx); |
| 111 | 158 static rtx pdp11_function_arg (cumulative_args_t, machine_mode, |
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159 const_tree, bool); |
| 111 | 160 static void pdp11_function_arg_advance (cumulative_args_t, |
| 161 machine_mode, const_tree, bool); | |
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162 static void pdp11_conditional_register_usage (void); |
| 111 | 163 static bool pdp11_legitimate_constant_p (machine_mode, rtx); |
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164 |
| 111 | 165 static bool pdp11_scalar_mode_supported_p (scalar_mode); |
| 0 | 166 |
| 167 /* Initialize the GCC target structure. */ | |
| 168 #undef TARGET_ASM_BYTE_OP | |
| 169 #define TARGET_ASM_BYTE_OP NULL | |
| 170 #undef TARGET_ASM_ALIGNED_HI_OP | |
| 171 #define TARGET_ASM_ALIGNED_HI_OP NULL | |
| 172 #undef TARGET_ASM_ALIGNED_SI_OP | |
| 173 #define TARGET_ASM_ALIGNED_SI_OP NULL | |
| 174 #undef TARGET_ASM_INTEGER | |
| 175 #define TARGET_ASM_INTEGER pdp11_assemble_integer | |
| 176 | |
| 177 #undef TARGET_ASM_OPEN_PAREN | |
| 178 #define TARGET_ASM_OPEN_PAREN "[" | |
| 179 #undef TARGET_ASM_CLOSE_PAREN | |
| 180 #define TARGET_ASM_CLOSE_PAREN "]" | |
| 181 | |
| 182 #undef TARGET_RTX_COSTS | |
| 183 #define TARGET_RTX_COSTS pdp11_rtx_costs | |
| 184 | |
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185 #undef TARGET_FUNCTION_ARG |
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186 #define TARGET_FUNCTION_ARG pdp11_function_arg |
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187 #undef TARGET_FUNCTION_ARG_ADVANCE |
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188 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance |
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189 |
| 0 | 190 #undef TARGET_RETURN_IN_MEMORY |
| 191 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory | |
| 192 | |
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193 #undef TARGET_FUNCTION_VALUE |
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194 #define TARGET_FUNCTION_VALUE pdp11_function_value |
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195 #undef TARGET_LIBCALL_VALUE |
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196 #define TARGET_LIBCALL_VALUE pdp11_libcall_value |
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197 #undef TARGET_FUNCTION_VALUE_REGNO_P |
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198 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p |
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199 |
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200 #undef TARGET_TRAMPOLINE_INIT |
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201 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init |
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202 |
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203 #undef TARGET_SECONDARY_RELOAD |
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204 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload |
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205 |
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206 #undef TARGET_REGISTER_MOVE_COST |
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207 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost |
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208 |
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209 #undef TARGET_PREFERRED_RELOAD_CLASS |
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210 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class |
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211 |
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212 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS |
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213 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class |
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214 |
| 111 | 215 #undef TARGET_LRA_P |
| 216 #define TARGET_LRA_P hook_bool_void_false | |
| 217 | |
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218 #undef TARGET_LEGITIMATE_ADDRESS_P |
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219 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p |
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220 |
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221 #undef TARGET_CONDITIONAL_REGISTER_USAGE |
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222 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage |
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223 |
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224 #undef TARGET_ASM_FUNCTION_SECTION |
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225 #define TARGET_ASM_FUNCTION_SECTION pdp11_function_section |
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226 |
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227 #undef TARGET_PRINT_OPERAND |
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228 #define TARGET_PRINT_OPERAND pdp11_asm_print_operand |
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229 |
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230 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P |
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231 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p |
| 111 | 232 |
| 233 #undef TARGET_LEGITIMATE_CONSTANT_P | |
| 234 #define TARGET_LEGITIMATE_CONSTANT_P pdp11_legitimate_constant_p | |
| 0 | 235 |
| 111 | 236 #undef TARGET_SCALAR_MODE_SUPPORTED_P |
| 237 #define TARGET_SCALAR_MODE_SUPPORTED_P pdp11_scalar_mode_supported_p | |
| 238 | |
| 239 #undef TARGET_HARD_REGNO_NREGS | |
| 240 #define TARGET_HARD_REGNO_NREGS pdp11_hard_regno_nregs | |
| 241 #undef TARGET_HARD_REGNO_MODE_OK | |
| 242 #define TARGET_HARD_REGNO_MODE_OK pdp11_hard_regno_mode_ok | |
| 0 | 243 |
| 111 | 244 #undef TARGET_MODES_TIEABLE_P |
| 245 #define TARGET_MODES_TIEABLE_P pdp11_modes_tieable_p | |
| 0 | 246 |
| 111 | 247 #undef TARGET_SECONDARY_MEMORY_NEEDED |
| 248 #define TARGET_SECONDARY_MEMORY_NEEDED pdp11_secondary_memory_needed | |
| 0 | 249 |
| 111 | 250 #undef TARGET_CAN_CHANGE_MODE_CLASS |
| 251 #define TARGET_CAN_CHANGE_MODE_CLASS pdp11_can_change_mode_class | |
| 252 | |
| 253 /* A helper function to determine if REGNO should be saved in the | |
| 254 current function's stack frame. */ | |
| 255 | |
| 256 static inline bool | |
| 257 pdp11_saved_regno (unsigned regno) | |
| 0 | 258 { |
| 111 | 259 return !call_used_regs[regno] && df_regs_ever_live_p (regno); |
| 0 | 260 } |
| 261 | |
| 111 | 262 /* Expand the function prologue. */ |
| 0 | 263 |
| 111 | 264 void |
| 265 pdp11_expand_prologue (void) | |
| 0 | 266 { |
| 111 | 267 HOST_WIDE_INT fsize = get_frame_size (); |
| 268 unsigned regno; | |
| 269 rtx x, via_ac = NULL; | |
| 0 | 270 |
| 111 | 271 /* If we are outputting code for main, the switch FPU to the |
| 272 right mode if TARGET_FPU. */ | |
| 273 if (MAIN_NAME_P (DECL_NAME (current_function_decl)) && TARGET_FPU) | |
| 0 | 274 { |
| 111 | 275 emit_insn (gen_setd ()); |
| 276 emit_insn (gen_seti ()); | |
| 0 | 277 } |
| 278 | |
| 111 | 279 if (frame_pointer_needed) |
| 0 | 280 { |
| 111 | 281 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); |
| 282 x = gen_frame_mem (Pmode, x); | |
| 283 emit_move_insn (x, hard_frame_pointer_rtx); | |
| 284 | |
| 285 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
| 0 | 286 } |
| 287 | |
| 111 | 288 /* Make frame. */ |
| 289 if (fsize) | |
| 0 | 290 { |
| 111 | 291 emit_insn (gen_addhi3 (stack_pointer_rtx, stack_pointer_rtx, |
| 292 GEN_INT (-fsize))); | |
| 293 | |
| 294 /* Prevent frame references via the frame pointer from being | |
| 295 scheduled before the frame is allocated. */ | |
| 296 if (frame_pointer_needed) | |
| 297 emit_insn (gen_blockage ()); | |
| 0 | 298 } |
| 299 | |
| 111 | 300 /* Save CPU registers. */ |
| 301 for (regno = R0_REGNUM; regno <= PC_REGNUM; regno++) | |
| 302 if (pdp11_saved_regno (regno) | |
| 303 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) | |
| 304 { | |
| 305 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); | |
| 306 x = gen_frame_mem (Pmode, x); | |
| 307 emit_move_insn (x, gen_rtx_REG (Pmode, regno)); | |
| 308 } | |
| 309 | |
| 310 /* Save FPU registers. */ | |
| 311 for (regno = AC0_REGNUM; regno <= AC3_REGNUM; regno++) | |
| 312 if (pdp11_saved_regno (regno)) | |
| 313 { | |
| 314 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); | |
| 315 x = gen_frame_mem (DFmode, x); | |
| 316 via_ac = gen_rtx_REG (DFmode, regno); | |
| 317 emit_move_insn (x, via_ac); | |
| 318 } | |
| 319 | |
| 320 /* ??? Maybe make ac4, ac5 call used regs?? */ | |
| 321 for (regno = AC4_REGNUM; regno <= AC5_REGNUM; regno++) | |
| 322 if (pdp11_saved_regno (regno)) | |
| 323 { | |
| 324 gcc_assert (via_ac != NULL); | |
| 325 emit_move_insn (via_ac, gen_rtx_REG (DFmode, regno)); | |
| 326 | |
| 327 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); | |
| 328 x = gen_frame_mem (DFmode, x); | |
| 329 emit_move_insn (x, via_ac); | |
| 330 } | |
| 0 | 331 } |
| 332 | |
| 111 | 333 /* The function epilogue should not depend on the current stack pointer! |
| 0 | 334 It should use the frame pointer only. This is mandatory because |
| 335 of alloca; we also take advantage of it to omit stack adjustments | |
| 336 before returning. */ | |
| 337 | |
| 111 | 338 /* Maybe we can make leaf functions faster by switching to the |
| 0 | 339 second register file - this way we don't have to save regs! |
| 340 leaf functions are ~ 50% of all functions (dynamically!) | |
| 341 | |
| 342 set/clear bit 11 (dec. 2048) of status word for switching register files - | |
| 343 but how can we do this? the pdp11/45 manual says bit may only | |
| 344 be set (p.24), but not cleared! | |
| 345 | |
| 346 switching to kernel is probably more expensive, so we'll leave it | |
| 347 like this and not use the second set of registers... | |
| 348 | |
| 349 maybe as option if you want to generate code for kernel mode? */ | |
| 350 | |
| 111 | 351 void |
| 352 pdp11_expand_epilogue (void) | |
| 0 | 353 { |
| 111 | 354 HOST_WIDE_INT fsize = get_frame_size (); |
| 355 unsigned regno; | |
| 356 rtx x, reg, via_ac = NULL; | |
| 357 | |
| 358 if (pdp11_saved_regno (AC4_REGNUM) || pdp11_saved_regno (AC5_REGNUM)) | |
| 359 { | |
| 360 /* Find a temporary with which to restore AC4/5. */ | |
| 361 for (regno = AC0_REGNUM; regno <= AC3_REGNUM; regno++) | |
| 362 if (pdp11_saved_regno (regno)) | |
| 363 { | |
| 364 via_ac = gen_rtx_REG (DFmode, regno); | |
| 365 break; | |
| 366 } | |
| 367 } | |
| 0 | 368 |
| 111 | 369 /* If possible, restore registers via pops. */ |
| 370 if (!frame_pointer_needed || crtl->sp_is_unchanging) | |
| 371 { | |
| 372 /* Restore registers via pops. */ | |
| 373 | |
| 374 for (regno = AC5_REGNUM; regno >= AC0_REGNUM; regno--) | |
| 375 if (pdp11_saved_regno (regno)) | |
| 376 { | |
| 377 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
| 378 x = gen_frame_mem (DFmode, x); | |
| 379 reg = gen_rtx_REG (DFmode, regno); | |
| 380 | |
| 381 if (LOAD_FPU_REG_P (regno)) | |
| 382 emit_move_insn (reg, x); | |
| 383 else | |
| 384 { | |
| 385 emit_move_insn (via_ac, x); | |
| 386 emit_move_insn (reg, via_ac); | |
| 387 } | |
| 388 } | |
| 0 | 389 |
| 111 | 390 for (regno = PC_REGNUM; regno >= R0_REGNUM + 2; regno--) |
| 391 if (pdp11_saved_regno (regno) | |
| 392 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) | |
| 393 { | |
| 394 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
| 395 x = gen_frame_mem (Pmode, x); | |
| 396 emit_move_insn (gen_rtx_REG (Pmode, regno), x); | |
| 397 } | |
| 398 } | |
| 399 else | |
| 400 { | |
| 401 /* Restore registers via moves. */ | |
| 402 /* ??? If more than a few registers need to be restored, it's smaller | |
| 403 to generate a pointer through which we can emit pops. Consider | |
| 404 that moves cost 2*NREG words and pops cost NREG+3 words. This | |
| 405 means that the crossover is NREG=3. | |
| 406 | |
| 407 Possible registers to use are: | |
| 408 (1) The first call-saved general register. This register will | |
| 409 be restored with the last pop. | |
| 410 (2) R1, if it's not used as a return register. | |
| 411 (3) FP itself. This option may result in +4 words, since we | |
| 412 may need two add imm,rn instructions instead of just one. | |
| 413 This also has the downside that we're not representing | |
| 414 the unwind info in any way, so during the epilogue the | |
| 415 debugger may get lost. */ | |
| 416 | |
| 417 HOST_WIDE_INT ofs = -pdp11_sp_frame_offset (); | |
| 0 | 418 |
| 111 | 419 for (regno = AC5_REGNUM; regno >= AC0_REGNUM; regno--) |
| 420 if (pdp11_saved_regno (regno)) | |
| 421 { | |
| 422 x = plus_constant (Pmode, hard_frame_pointer_rtx, ofs); | |
| 423 x = gen_frame_mem (DFmode, x); | |
| 424 reg = gen_rtx_REG (DFmode, regno); | |
| 425 | |
| 426 if (LOAD_FPU_REG_P (regno)) | |
| 427 emit_move_insn (reg, x); | |
| 428 else | |
| 429 { | |
| 430 emit_move_insn (via_ac, x); | |
| 431 emit_move_insn (reg, via_ac); | |
| 432 } | |
| 433 ofs += 8; | |
| 434 } | |
| 435 | |
| 436 for (regno = PC_REGNUM; regno >= R0_REGNUM + 2; regno--) | |
| 437 if (pdp11_saved_regno (regno) | |
| 438 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) | |
| 439 { | |
| 440 x = plus_constant (Pmode, hard_frame_pointer_rtx, ofs); | |
| 441 x = gen_frame_mem (Pmode, x); | |
| 442 emit_move_insn (gen_rtx_REG (Pmode, regno), x); | |
| 443 ofs += 2; | |
| 444 } | |
| 445 } | |
| 446 | |
| 447 /* Deallocate the stack frame. */ | |
| 448 if (fsize) | |
| 449 { | |
| 450 /* Prevent frame references via any pointer from being | |
| 451 scheduled after the frame is deallocated. */ | |
| 452 emit_insn (gen_blockage ()); | |
| 453 | |
| 454 if (frame_pointer_needed) | |
| 0 | 455 { |
| 111 | 456 /* We can deallocate the frame with a single move. */ |
| 457 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); | |
| 0 | 458 } |
| 111 | 459 else |
| 460 emit_insn (gen_addhi3 (stack_pointer_rtx, stack_pointer_rtx, | |
| 461 GEN_INT (fsize))); | |
| 462 } | |
| 0 | 463 |
| 111 | 464 if (frame_pointer_needed) |
| 465 { | |
| 466 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
| 467 x = gen_frame_mem (Pmode, x); | |
| 468 emit_move_insn (hard_frame_pointer_rtx, x); | |
| 469 } | |
| 470 | |
| 471 emit_jump_insn (gen_return ()); | |
| 0 | 472 } |
| 473 | |
| 474 /* Return the best assembler insn template | |
| 475 for moving operands[1] into operands[0] as a fullword. */ | |
| 476 static const char * | |
| 477 singlemove_string (rtx *operands) | |
| 478 { | |
| 479 if (operands[1] != const0_rtx) | |
| 480 return "mov %1,%0"; | |
| 481 | |
| 482 return "clr %0"; | |
| 483 } | |
| 484 | |
| 485 | |
|
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486 /* Expand multi-word operands (SImode or DImode) into the 2 or 4 |
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487 corresponding HImode operands. The number of operands is given |
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488 as the third argument, and the required order of the parts as |
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489 the fourth argument. */ |
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490 bool |
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491 pdp11_expand_operands (rtx *operands, rtx exops[][2], int opcount, |
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492 pdp11_action *action, pdp11_partorder order) |
| 0 | 493 { |
|
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494 int words, op, w, i, sh; |
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495 pdp11_partorder useorder; |
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496 bool sameoff = false; |
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497 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype; |
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498 long sval[2]; |
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499 |
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500 words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; |
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501 |
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502 /* If either piece order is accepted and one is pre-decrement |
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503 while the other is post-increment, set order to be high order |
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504 word first. That will force the pre-decrement to be turned |
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505 into a pointer adjust, then offset addressing. |
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506 Otherwise, if either operand uses pre-decrement, that means |
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507 the order is low order first. |
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508 Otherwise, if both operands are registers and destination is |
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509 higher than source and they overlap, do low order word (highest |
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510 register number) first. */ |
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511 useorder = either; |
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512 if (opcount == 2) |
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513 { |
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514 if (!REG_P (operands[0]) && !REG_P (operands[1]) && |
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515 !(CONSTANT_P (operands[1]) || |
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516 GET_CODE (operands[1]) == CONST_DOUBLE) && |
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517 ((GET_CODE (XEXP (operands[0], 0)) == POST_INC && |
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518 GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) || |
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519 (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC && |
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520 GET_CODE (XEXP (operands[1], 0)) == POST_INC))) |
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521 useorder = big; |
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522 else if ((!REG_P (operands[0]) && |
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523 GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) || |
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524 (!REG_P (operands[1]) && |
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525 !(CONSTANT_P (operands[1]) || |
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526 GET_CODE (operands[1]) == CONST_DOUBLE) && |
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527 GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
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528 useorder = little; |
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529 else if (REG_P (operands[0]) && REG_P (operands[1]) && |
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530 REGNO (operands[0]) > REGNO (operands[1]) && |
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531 REGNO (operands[0]) < REGNO (operands[1]) + words) |
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532 useorder = little; |
| 0 | 533 |
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534 /* Check for source == offset from register and dest == push of |
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535 the same register. In that case, we have to use the same |
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536 offset (the one for the low order word) for all words, because |
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537 the push increases the offset to each source word. |
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538 In theory there are other cases like this, for example dest == pop, |
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539 but those don't occur in real life so ignore those. */ |
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540 if (GET_CODE (operands[0]) == MEM |
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541 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC |
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542 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM |
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543 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) |
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544 sameoff = true; |
| 0 | 545 } |
| 546 | |
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547 /* If the caller didn't specify order, use the one we computed, |
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548 or high word first if we don't care either. If the caller did |
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549 specify, verify we don't have a problem with that order. |
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550 (If it matters to the caller, constraints need to be used to |
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551 ensure this case doesn't occur). */ |
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552 if (order == either) |
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553 order = (useorder == either) ? big : useorder; |
| 0 | 554 else |
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555 gcc_assert (useorder == either || useorder == order); |
| 0 | 556 |
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557 |
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558 for (op = 0; op < opcount; op++) |
| 0 | 559 { |
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560 /* First classify the operand. */ |
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561 if (REG_P (operands[op])) |
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562 optype = REGOP; |
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563 else if (CONSTANT_P (operands[op]) |
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564 || GET_CODE (operands[op]) == CONST_DOUBLE) |
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565 optype = CNSTOP; |
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566 else if (GET_CODE (XEXP (operands[op], 0)) == POST_INC) |
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567 optype = POPOP; |
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568 else if (GET_CODE (XEXP (operands[op], 0)) == PRE_DEC) |
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569 optype = PUSHOP; |
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570 else if (!reload_in_progress || offsettable_memref_p (operands[op])) |
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571 optype = OFFSOP; |
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572 else if (GET_CODE (operands[op]) == MEM) |
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573 optype = MEMOP; |
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574 else |
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575 optype = RNDOP; |
| 0 | 576 |
|
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577 /* Check for the cases that the operand constraints are not |
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578 supposed to allow to happen. Return failure for such cases. */ |
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579 if (optype == RNDOP) |
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580 return false; |
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581 |
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582 if (action != NULL) |
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583 action[op] = no_action; |
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584 |
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585 /* If the operand uses pre-decrement addressing but we |
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586 want to get the parts high order first, |
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587 decrement the former register explicitly |
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588 and change the operand into ordinary indexing. */ |
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589 if (optype == PUSHOP && order == big) |
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590 { |
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591 gcc_assert (action != NULL); |
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592 action[op] = dec_before; |
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593 operands[op] = gen_rtx_MEM (GET_MODE (operands[op]), |
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594 XEXP (XEXP (operands[op], 0), 0)); |
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595 optype = OFFSOP; |
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596 } |
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597 /* If the operand uses post-increment mode but we want |
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598 to get the parts low order first, change the operand |
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599 into ordinary indexing and remember to increment |
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600 the register explicitly when we're done. */ |
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601 else if (optype == POPOP && order == little) |
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602 { |
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603 gcc_assert (action != NULL); |
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604 action[op] = inc_after; |
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605 operands[op] = gen_rtx_MEM (GET_MODE (operands[op]), |
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606 XEXP (XEXP (operands[op], 0), 0)); |
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607 optype = OFFSOP; |
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608 } |
| 0 | 609 |
|
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610 if (GET_CODE (operands[op]) == CONST_DOUBLE) |
| 111 | 611 REAL_VALUE_TO_TARGET_DOUBLE |
| 612 (*CONST_DOUBLE_REAL_VALUE (operands[op]), sval); | |
|
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613 |
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614 for (i = 0; i < words; i++) |
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615 { |
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616 if (order == big) |
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617 w = i; |
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618 else if (sameoff) |
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619 w = words - 1; |
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620 else |
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621 w = words - 1 - i; |
| 0 | 622 |
|
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623 /* Set the output operand to be word "w" of the input. */ |
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624 if (optype == REGOP) |
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625 exops[i][op] = gen_rtx_REG (HImode, REGNO (operands[op]) + w); |
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626 else if (optype == OFFSOP) |
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627 exops[i][op] = adjust_address (operands[op], HImode, w * 2); |
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628 else if (optype == CNSTOP) |
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629 { |
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630 if (GET_CODE (operands[op]) == CONST_DOUBLE) |
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631 { |
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632 sh = 16 - (w & 1) * 16; |
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633 exops[i][op] = gen_rtx_CONST_INT (HImode, (sval[w / 2] >> sh) & 0xffff); |
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634 } |
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635 else |
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636 { |
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637 sh = ((words - 1 - w) * 16); |
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638 exops[i][op] = gen_rtx_CONST_INT (HImode, trunc_int_for_mode (INTVAL(operands[op]) >> sh, HImode)); |
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639 } |
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640 } |
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641 else |
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642 exops[i][op] = operands[op]; |
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643 } |
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644 } |
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645 return true; |
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646 } |
| 0 | 647 |
|
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648 /* Output assembler code to perform a multiple-word move insn |
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649 with operands OPERANDS. This moves 2 or 4 words depending |
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650 on the machine mode of the operands. */ |
| 0 | 651 |
| 652 const char * | |
|
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653 output_move_multiple (rtx *operands) |
| 0 | 654 { |
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655 rtx exops[4][2]; |
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656 pdp11_action action[2]; |
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657 int i, words; |
| 0 | 658 |
|
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659 words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; |
| 0 | 660 |
|
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661 pdp11_expand_operands (operands, exops, 2, action, either); |
| 0 | 662 |
|
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663 /* Check for explicit decrement before. */ |
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664 if (action[0] == dec_before) |
| 0 | 665 { |
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666 operands[0] = XEXP (operands[0], 0); |
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667 output_asm_insn ("sub $4,%0", operands); |
| 0 | 668 } |
|
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669 if (action[1] == dec_before) |
| 0 | 670 { |
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671 operands[1] = XEXP (operands[1], 0); |
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672 output_asm_insn ("sub $4,%1", operands); |
| 0 | 673 } |
| 674 | |
|
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675 /* Do the words. */ |
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676 for (i = 0; i < words; i++) |
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677 output_asm_insn (singlemove_string (exops[i]), exops[i]); |
| 0 | 678 |
|
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679 /* Check for increment after. */ |
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680 if (action[0] == inc_after) |
| 0 | 681 { |
|
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682 operands[0] = XEXP (operands[0], 0); |
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683 output_asm_insn ("add $4,%0", operands); |
| 0 | 684 } |
|
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685 if (action[1] == inc_after) |
| 0 | 686 { |
|
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687 operands[1] = XEXP (operands[1], 0); |
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688 output_asm_insn ("add $4,%1", operands); |
| 0 | 689 } |
| 690 | |
| 691 return ""; | |
| 692 } | |
| 693 | |
| 694 /* Output an ascii string. */ | |
| 695 void | |
| 696 output_ascii (FILE *file, const char *p, int size) | |
| 697 { | |
| 698 int i; | |
| 699 | |
| 700 /* This used to output .byte "string", which doesn't work with the UNIX | |
| 701 assembler and I think not with DEC ones either. */ | |
| 702 fprintf (file, "\t.byte "); | |
| 703 | |
| 704 for (i = 0; i < size; i++) | |
| 705 { | |
| 706 register int c = p[i]; | |
| 707 if (c < 0) | |
| 708 c += 256; | |
| 709 fprintf (file, "%#o", c); | |
| 710 if (i < size - 1) | |
| 711 putc (',', file); | |
| 712 } | |
| 713 putc ('\n', file); | |
| 714 } | |
| 715 | |
| 716 | |
|
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717 void |
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718 pdp11_asm_output_var (FILE *file, const char *name, int size, |
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719 int align, bool global) |
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720 { |
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721 if (align > 8) |
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722 fprintf (file, "\n\t.even\n"); |
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723 if (global) |
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724 { |
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725 fprintf (file, ".globl "); |
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726 assemble_name (file, name); |
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727 } |
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728 fprintf (file, "\n"); |
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729 assemble_name (file, name); |
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730 fprintf (file, ": .=.+ %#ho\n", (unsigned short)size); |
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731 } |
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732 |
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733 static void |
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734 pdp11_asm_print_operand (FILE *file, rtx x, int code) |
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735 { |
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736 long sval[2]; |
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737 |
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738 if (code == '#') |
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739 fprintf (file, "#"); |
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740 else if (code == '@') |
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741 { |
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742 if (TARGET_UNIX_ASM) |
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743 fprintf (file, "*"); |
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744 else |
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745 fprintf (file, "@"); |
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746 } |
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747 else if (GET_CODE (x) == REG) |
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748 fprintf (file, "%s", reg_names[REGNO (x)]); |
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749 else if (GET_CODE (x) == MEM) |
| 111 | 750 output_address (GET_MODE (x), XEXP (x, 0)); |
|
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751 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != SImode) |
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752 { |
| 111 | 753 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), sval); |
|
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754 fprintf (file, "$%#lo", sval[0] >> 16); |
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755 } |
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756 else |
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757 { |
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758 putc ('$', file); |
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759 output_addr_const_pdp11 (file, x); |
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760 } |
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761 } |
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762 |
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763 static bool |
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764 pdp11_asm_print_operand_punct_valid_p (unsigned char c) |
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765 { |
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766 return (c == '#' || c == '@'); |
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767 } |
| 0 | 768 |
| 769 void | |
| 770 print_operand_address (FILE *file, register rtx addr) | |
| 771 { | |
|
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|
772 register rtx breg; |
| 0 | 773 rtx offset; |
|
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774 int again = 0; |
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775 |
| 0 | 776 retry: |
| 777 | |
| 778 switch (GET_CODE (addr)) | |
| 779 { | |
| 780 case MEM: | |
| 781 if (TARGET_UNIX_ASM) | |
| 782 fprintf (file, "*"); | |
| 783 else | |
| 784 fprintf (file, "@"); | |
| 785 addr = XEXP (addr, 0); | |
|
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786 again = 1; |
| 0 | 787 goto retry; |
| 788 | |
| 789 case REG: | |
| 790 fprintf (file, "(%s)", reg_names[REGNO (addr)]); | |
| 791 break; | |
| 792 | |
| 793 case PRE_MODIFY: | |
| 794 case PRE_DEC: | |
| 795 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); | |
| 796 break; | |
| 797 | |
| 798 case POST_MODIFY: | |
| 799 case POST_INC: | |
| 800 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); | |
| 801 break; | |
| 802 | |
| 803 case PLUS: | |
|
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804 breg = 0; |
| 0 | 805 offset = 0; |
| 806 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) | |
| 807 || GET_CODE (XEXP (addr, 0)) == MEM) | |
| 808 { | |
| 809 offset = XEXP (addr, 0); | |
| 810 addr = XEXP (addr, 1); | |
| 811 } | |
| 812 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) | |
| 813 || GET_CODE (XEXP (addr, 1)) == MEM) | |
| 814 { | |
| 815 offset = XEXP (addr, 1); | |
| 816 addr = XEXP (addr, 0); | |
| 817 } | |
| 818 if (GET_CODE (addr) != PLUS) | |
| 819 ; | |
| 820 else if (GET_CODE (XEXP (addr, 0)) == REG) | |
| 821 { | |
|
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822 breg = XEXP (addr, 0); |
| 0 | 823 addr = XEXP (addr, 1); |
| 824 } | |
| 825 else if (GET_CODE (XEXP (addr, 1)) == REG) | |
| 826 { | |
|
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827 breg = XEXP (addr, 1); |
| 0 | 828 addr = XEXP (addr, 0); |
| 829 } | |
|
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830 if (GET_CODE (addr) == REG) |
| 0 | 831 { |
|
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832 gcc_assert (breg == 0); |
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833 breg = addr; |
| 0 | 834 addr = 0; |
| 835 } | |
| 836 if (offset != 0) | |
| 837 { | |
| 838 gcc_assert (addr == 0); | |
| 839 addr = offset; | |
| 840 } | |
| 841 if (addr != 0) | |
|
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842 output_addr_const_pdp11 (file, addr); |
| 0 | 843 if (breg != 0) |
| 844 { | |
| 845 gcc_assert (GET_CODE (breg) == REG); | |
| 846 fprintf (file, "(%s)", reg_names[REGNO (breg)]); | |
| 847 } | |
| 848 break; | |
| 849 | |
| 850 default: | |
|
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851 if (!again && GET_CODE (addr) == CONST_INT) |
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852 { |
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853 /* Absolute (integer number) address. */ |
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854 if (!TARGET_UNIX_ASM) |
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855 fprintf (file, "@$"); |
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856 } |
| 0 | 857 output_addr_const_pdp11 (file, addr); |
| 858 } | |
| 859 } | |
| 860 | |
| 861 /* Target hook to assemble integer objects. We need to use the | |
| 862 pdp-specific version of output_addr_const. */ | |
| 863 | |
| 864 static bool | |
| 865 pdp11_assemble_integer (rtx x, unsigned int size, int aligned_p) | |
| 866 { | |
| 867 if (aligned_p) | |
| 868 switch (size) | |
| 869 { | |
| 870 case 1: | |
| 871 fprintf (asm_out_file, "\t.byte\t"); | |
|
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872 output_addr_const_pdp11 (asm_out_file, GEN_INT (INTVAL (x) & 0xff)); |
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873 ; |
| 0 | 874 fprintf (asm_out_file, " /* char */\n"); |
| 875 return true; | |
| 876 | |
| 877 case 2: | |
| 878 fprintf (asm_out_file, TARGET_UNIX_ASM ? "\t" : "\t.word\t"); | |
| 879 output_addr_const_pdp11 (asm_out_file, x); | |
| 880 fprintf (asm_out_file, " /* short */\n"); | |
| 881 return true; | |
| 882 } | |
| 883 return default_assemble_integer (x, size, aligned_p); | |
| 884 } | |
| 885 | |
| 886 | |
| 887 /* register move costs, indexed by regs */ | |
| 888 | |
| 889 static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] = | |
| 890 { | |
| 891 /* NO MUL GEN LFPU NLFPU FPU ALL */ | |
| 892 | |
| 893 /* NO */ { 0, 0, 0, 0, 0, 0, 0}, | |
|
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894 /* MUL */ { 0, 2, 2, 22, 22, 22, 22}, |
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895 /* GEN */ { 0, 2, 2, 22, 22, 22, 22}, |
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896 /* LFPU */ { 0, 22, 22, 2, 2, 2, 22}, |
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897 /* NLFPU */ { 0, 22, 22, 2, 10, 10, 22}, |
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898 /* FPU */ { 0, 22, 22, 2, 10, 10, 22}, |
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899 /* ALL */ { 0, 22, 22, 22, 22, 22, 22} |
| 0 | 900 } ; |
| 901 | |
| 902 | |
| 903 /* -- note that some moves are tremendously expensive, | |
| 904 because they require lots of tricks! do we have to | |
| 905 charge the costs incurred by secondary reload class | |
|
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906 -- as we do here with 10 -- or not ? */ |
| 0 | 907 |
|
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908 static int |
| 111 | 909 pdp11_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
|
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910 reg_class_t c1, reg_class_t c2) |
| 0 | 911 { |
| 912 return move_costs[(int)c1][(int)c2]; | |
| 913 } | |
| 914 | |
| 915 static bool | |
| 111 | 916 pdp11_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, |
| 917 int opno ATTRIBUTE_UNUSED, int *total, | |
| 0 | 918 bool speed ATTRIBUTE_UNUSED) |
| 919 { | |
| 111 | 920 int code = GET_CODE (x); |
| 921 | |
| 0 | 922 switch (code) |
| 923 { | |
| 924 case CONST_INT: | |
| 925 if (INTVAL (x) == 0 || INTVAL (x) == -1 || INTVAL (x) == 1) | |
| 926 { | |
| 927 *total = 0; | |
| 928 return true; | |
| 929 } | |
| 930 /* FALLTHRU */ | |
| 931 | |
| 932 case CONST: | |
| 933 case LABEL_REF: | |
| 934 case SYMBOL_REF: | |
| 935 /* Twice as expensive as REG. */ | |
| 936 *total = 2; | |
| 937 return true; | |
| 938 | |
| 939 case CONST_DOUBLE: | |
| 940 /* Twice (or 4 times) as expensive as 16 bit. */ | |
| 941 *total = 4; | |
| 942 return true; | |
| 943 | |
| 944 case MULT: | |
| 945 /* ??? There is something wrong in MULT because MULT is not | |
| 946 as cheap as total = 2 even if we can shift! */ | |
| 947 /* If optimizing for size make mult etc cheap, but not 1, so when | |
| 948 in doubt the faster insn is chosen. */ | |
| 949 if (optimize_size) | |
| 950 *total = COSTS_N_INSNS (2); | |
| 951 else | |
| 952 *total = COSTS_N_INSNS (11); | |
| 953 return false; | |
| 954 | |
| 955 case DIV: | |
| 956 if (optimize_size) | |
| 957 *total = COSTS_N_INSNS (2); | |
| 958 else | |
| 959 *total = COSTS_N_INSNS (25); | |
| 960 return false; | |
| 961 | |
| 962 case MOD: | |
| 963 if (optimize_size) | |
| 964 *total = COSTS_N_INSNS (2); | |
| 965 else | |
| 966 *total = COSTS_N_INSNS (26); | |
| 967 return false; | |
| 968 | |
| 969 case ABS: | |
| 970 /* Equivalent to length, so same for optimize_size. */ | |
| 971 *total = COSTS_N_INSNS (3); | |
| 972 return false; | |
| 973 | |
| 974 case ZERO_EXTEND: | |
| 975 /* Only used for qi->hi. */ | |
| 976 *total = COSTS_N_INSNS (1); | |
| 977 return false; | |
| 978 | |
| 979 case SIGN_EXTEND: | |
| 111 | 980 if (mode == HImode) |
| 0 | 981 *total = COSTS_N_INSNS (1); |
| 111 | 982 else if (mode == SImode) |
| 0 | 983 *total = COSTS_N_INSNS (6); |
| 984 else | |
| 985 *total = COSTS_N_INSNS (2); | |
| 986 return false; | |
| 987 | |
| 988 case ASHIFT: | |
| 989 case LSHIFTRT: | |
| 990 case ASHIFTRT: | |
| 991 if (optimize_size) | |
| 992 *total = COSTS_N_INSNS (1); | |
| 111 | 993 else if (mode == QImode) |
| 0 | 994 { |
| 995 if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
| 996 *total = COSTS_N_INSNS (8); /* worst case */ | |
| 997 else | |
| 998 *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1))); | |
| 999 } | |
| 111 | 1000 else if (mode == HImode) |
| 0 | 1001 { |
| 1002 if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
| 1003 { | |
| 1004 if (abs (INTVAL (XEXP (x, 1))) == 1) | |
| 1005 *total = COSTS_N_INSNS (1); | |
| 1006 else | |
| 1007 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1))); | |
| 1008 } | |
| 1009 else | |
| 1010 *total = COSTS_N_INSNS (10); /* worst case */ | |
| 1011 } | |
| 111 | 1012 else if (mode == SImode) |
| 0 | 1013 { |
| 1014 if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
| 1015 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1))); | |
| 1016 else /* worst case */ | |
| 1017 *total = COSTS_N_INSNS (18); | |
| 1018 } | |
| 1019 return false; | |
| 1020 | |
| 1021 default: | |
| 1022 return false; | |
| 1023 } | |
| 1024 } | |
| 1025 | |
| 1026 const char * | |
|
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1027 output_jump (enum rtx_code code, int inv, int length) |
| 0 | 1028 { |
| 1029 static int x = 0; | |
| 1030 | |
| 1031 static char buf[1000]; | |
|
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1032 const char *pos, *neg; |
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1033 |
|
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1034 if (cc_prev_status.flags & CC_NO_OVERFLOW) |
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1035 { |
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1036 switch (code) |
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1037 { |
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1038 case GTU: code = GT; break; |
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1039 case LTU: code = LT; break; |
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1040 case GEU: code = GE; break; |
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1041 case LEU: code = LE; break; |
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1042 default: ; |
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1043 } |
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1044 } |
|
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1045 switch (code) |
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1046 { |
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1047 case EQ: pos = "beq", neg = "bne"; break; |
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1048 case NE: pos = "bne", neg = "beq"; break; |
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1049 case GT: pos = "bgt", neg = "ble"; break; |
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1050 case GTU: pos = "bhi", neg = "blos"; break; |
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1051 case LT: pos = "blt", neg = "bge"; break; |
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1052 case LTU: pos = "blo", neg = "bhis"; break; |
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1053 case GE: pos = "bge", neg = "blt"; break; |
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1054 case GEU: pos = "bhis", neg = "blo"; break; |
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1055 case LE: pos = "ble", neg = "bgt"; break; |
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1056 case LEU: pos = "blos", neg = "bhi"; break; |
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1057 default: gcc_unreachable (); |
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1058 } |
| 0 | 1059 |
| 1060 #if 0 | |
| 1061 /* currently we don't need this, because the tstdf and cmpdf | |
| 1062 copy the condition code immediately, and other float operations are not | |
| 1063 yet recognized as changing the FCC - if so, then the length-cost of all | |
| 1064 jump insns increases by one, because we have to potentially copy the | |
| 1065 FCC! */ | |
| 1066 if (cc_status.flags & CC_IN_FPU) | |
| 1067 output_asm_insn("cfcc", NULL); | |
| 1068 #endif | |
| 1069 | |
| 1070 switch (length) | |
| 1071 { | |
|
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1072 case 2: |
| 0 | 1073 |
|
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1074 sprintf(buf, "%s %%l1", inv ? neg : pos); |
| 0 | 1075 |
| 1076 return buf; | |
| 1077 | |
|
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1078 case 6: |
| 0 | 1079 |
|
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1080 sprintf(buf, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv ? pos : neg, x, x); |
| 0 | 1081 |
| 1082 x++; | |
| 1083 | |
| 1084 return buf; | |
| 1085 | |
| 1086 default: | |
| 1087 | |
| 1088 gcc_unreachable (); | |
| 1089 } | |
| 1090 | |
| 1091 } | |
| 1092 | |
| 1093 void | |
| 1094 notice_update_cc_on_set(rtx exp, rtx insn ATTRIBUTE_UNUSED) | |
| 1095 { | |
| 1096 if (GET_CODE (SET_DEST (exp)) == CC0) | |
| 1097 { | |
|
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1098 cc_status.flags = 0; |
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1099 cc_status.value1 = SET_DEST (exp); |
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1100 cc_status.value2 = SET_SRC (exp); |
| 0 | 1101 } |
| 1102 else if (GET_CODE (SET_SRC (exp)) == CALL) | |
| 1103 { | |
|
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1104 CC_STATUS_INIT; |
| 0 | 1105 } |
| 1106 else if (SET_DEST(exp) == pc_rtx) | |
| 1107 { | |
|
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1108 /* jump */ |
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1109 } |
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1110 else if (GET_MODE (SET_DEST(exp)) == HImode |
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1111 || GET_MODE (SET_DEST(exp)) == QImode) |
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1112 { |
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1113 cc_status.flags = GET_CODE (SET_SRC(exp)) == MINUS ? 0 : CC_NO_OVERFLOW; |
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1114 cc_status.value1 = SET_SRC (exp); |
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1115 cc_status.value2 = SET_DEST (exp); |
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1116 |
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1117 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG |
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1118 && cc_status.value2 |
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1119 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) |
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1120 cc_status.value2 = 0; |
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1121 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM |
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1122 && cc_status.value2 |
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1123 && GET_CODE (cc_status.value2) == MEM) |
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1124 cc_status.value2 = 0; |
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1125 } |
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1126 else |
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1127 { |
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1128 CC_STATUS_INIT; |
| 0 | 1129 } |
| 1130 } | |
| 1131 | |
| 1132 | |
| 1133 int | |
| 111 | 1134 simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) |
| 0 | 1135 { |
| 1136 rtx addr; | |
| 1137 | |
| 1138 /* Eliminate non-memory operations */ | |
| 1139 if (GET_CODE (op) != MEM) | |
| 1140 return FALSE; | |
| 1141 | |
| 1142 #if 0 | |
| 1143 /* dword operations really put out 2 instructions, so eliminate them. */ | |
| 1144 if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4)) | |
| 1145 return FALSE; | |
| 1146 #endif | |
| 1147 | |
| 1148 /* Decode the address now. */ | |
| 1149 | |
| 1150 indirection: | |
| 1151 | |
| 1152 addr = XEXP (op, 0); | |
| 1153 | |
| 1154 switch (GET_CODE (addr)) | |
| 1155 { | |
| 1156 case REG: | |
| 1157 /* (R0) - no extra cost */ | |
| 1158 return 1; | |
| 1159 | |
| 1160 case PRE_DEC: | |
| 1161 case POST_INC: | |
| 1162 /* -(R0), (R0)+ - cheap! */ | |
| 1163 return 0; | |
| 1164 | |
| 1165 case MEM: | |
| 1166 /* cheap - is encoded in addressing mode info! | |
| 1167 | |
| 1168 -- except for @(R0), which has to be @0(R0) !!! */ | |
| 1169 | |
| 1170 if (GET_CODE (XEXP (addr, 0)) == REG) | |
| 1171 return 0; | |
| 1172 | |
| 1173 op=addr; | |
| 1174 goto indirection; | |
| 1175 | |
| 1176 case CONST_INT: | |
| 1177 case LABEL_REF: | |
| 1178 case CONST: | |
| 1179 case SYMBOL_REF: | |
| 1180 /* @#address - extra cost */ | |
| 1181 return 0; | |
| 1182 | |
| 1183 case PLUS: | |
| 1184 /* X(R0) - extra cost */ | |
| 1185 return 0; | |
| 1186 | |
| 1187 default: | |
| 1188 break; | |
| 1189 } | |
| 1190 | |
| 1191 return FALSE; | |
| 1192 } | |
| 1193 | |
| 1194 | |
| 1195 /* | |
| 1196 * output a block move: | |
| 1197 * | |
| 1198 * operands[0] ... to | |
| 1199 * operands[1] ... from | |
| 1200 * operands[2] ... length | |
| 1201 * operands[3] ... alignment | |
| 1202 * operands[4] ... scratch register | |
| 1203 */ | |
| 1204 | |
| 1205 | |
| 1206 const char * | |
| 1207 output_block_move(rtx *operands) | |
| 1208 { | |
| 1209 static int count = 0; | |
| 1210 char buf[200]; | |
|
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1211 int unroll; |
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1212 int lastbyte = 0; |
| 0 | 1213 |
|
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1214 /* Move of zero bytes is a NOP. */ |
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1215 if (operands[2] == const0_rtx) |
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1216 return ""; |
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1217 |
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|
1218 /* Look for moves by small constant byte counts, those we'll |
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1219 expand to straight line code. */ |
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1220 if (CONSTANT_P (operands[2])) |
| 0 | 1221 { |
|
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1222 if (INTVAL (operands[2]) < 16 |
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1223 && (!optimize_size || INTVAL (operands[2]) < 5) |
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1224 && INTVAL (operands[3]) == 1) |
| 0 | 1225 { |
| 1226 register int i; | |
| 1227 | |
|
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1228 for (i = 1; i <= INTVAL (operands[2]); i++) |
| 0 | 1229 output_asm_insn("movb (%1)+, (%0)+", operands); |
| 1230 | |
| 1231 return ""; | |
| 1232 } | |
|
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1233 else if (INTVAL(operands[2]) < 32 |
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1234 && (!optimize_size || INTVAL (operands[2]) < 9) |
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1235 && INTVAL (operands[3]) >= 2) |
| 0 | 1236 { |
| 1237 register int i; | |
| 1238 | |
|
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1239 for (i = 1; i <= INTVAL (operands[2]) / 2; i++) |
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1240 output_asm_insn ("mov (%1)+, (%0)+", operands); |
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1241 if (INTVAL (operands[2]) & 1) |
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1242 output_asm_insn ("movb (%1), (%0)", operands); |
| 0 | 1243 |
| 1244 return ""; | |
| 1245 } | |
| 1246 } | |
| 1247 | |
|
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1248 /* Ideally we'd look for moves that are multiples of 4 or 8 |
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1249 bytes and handle those by unrolling the move loop. That |
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1250 makes for a lot of code if done at run time, but it's ok |
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1251 for constant counts. Also, for variable counts we have |
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1252 to worry about odd byte count with even aligned pointers. |
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1253 On 11/40 and up we handle that case; on older machines |
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1254 we don't and just use byte-wise moves all the time. */ |
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1255 |
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1256 if (CONSTANT_P (operands[2]) ) |
| 0 | 1257 { |
|
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1258 if (INTVAL (operands[3]) < 2) |
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1259 unroll = 0; |
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1260 else |
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1261 { |
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1262 lastbyte = INTVAL (operands[2]) & 1; |
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1263 |
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1264 if (optimize_size || INTVAL (operands[2]) & 2) |
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1265 unroll = 1; |
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1266 else if (INTVAL (operands[2]) & 4) |
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1267 unroll = 2; |
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1268 else |
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1269 unroll = 3; |
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1270 } |
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1271 |
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1272 /* Loop count is byte count scaled by unroll. */ |
|
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1273 operands[2] = GEN_INT (INTVAL (operands[2]) >> unroll); |
|
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1274 output_asm_insn ("mov %2, %4", operands); |
| 0 | 1275 } |
| 1276 else | |
| 1277 { | |
|
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1278 /* Variable byte count; use the input register |
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1279 as the scratch. */ |
| 0 | 1280 operands[4] = operands[2]; |
| 1281 | |
|
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1282 /* Decide whether to move by words, and check |
|
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1283 the byte count for zero. */ |
|
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1284 if (TARGET_40_PLUS && INTVAL (operands[3]) > 1) |
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1285 { |
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1286 unroll = 1; |
|
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1287 output_asm_insn ("asr %4", operands); |
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1288 } |
|
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1289 else |
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1290 { |
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1291 unroll = 0; |
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1292 output_asm_insn ("tst %4", operands); |
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1293 } |
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1294 sprintf (buf, "beq movestrhi%d", count + 1); |
|
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1295 output_asm_insn (buf, NULL); |
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1296 } |
| 0 | 1297 |
|
67
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1298 /* Output the loop label. */ |
|
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1299 sprintf (buf, "\nmovestrhi%d:", count); |
|
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1300 output_asm_insn (buf, NULL); |
|
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1301 |
|
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1302 /* Output the appropriate move instructions. */ |
|
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1303 switch (unroll) |
|
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1304 { |
|
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1305 case 0: |
|
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1306 output_asm_insn ("movb (%1)+, (%0)+", operands); |
|
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1307 break; |
| 0 | 1308 |
|
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1309 case 1: |
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1310 output_asm_insn ("mov (%1)+, (%0)+", operands); |
| 0 | 1311 break; |
| 1312 | |
| 1313 case 2: | |
|
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1314 output_asm_insn ("mov (%1)+, (%0)+", operands); |
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1315 output_asm_insn ("mov (%1)+, (%0)+", operands); |
| 0 | 1316 break; |
| 1317 | |
|
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1318 default: |
|
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1319 output_asm_insn ("mov (%1)+, (%0)+", operands); |
|
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1320 output_asm_insn ("mov (%1)+, (%0)+", operands); |
|
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1321 output_asm_insn ("mov (%1)+, (%0)+", operands); |
|
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1322 output_asm_insn ("mov (%1)+, (%0)+", operands); |
|
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1323 break; |
| 0 | 1324 } |
|
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1325 |
|
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1326 /* Output the decrement and test. */ |
|
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1327 if (TARGET_40_PLUS) |
|
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1328 { |
|
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|
1329 sprintf (buf, "sob %%4, movestrhi%d", count); |
|
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1330 output_asm_insn (buf, operands); |
|
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1331 } |
|
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1332 else |
|
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1333 { |
|
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|
1334 output_asm_insn ("dec %4", operands); |
|
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|
1335 sprintf (buf, "bgt movestrhi%d", count); |
|
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|
1336 output_asm_insn (buf, NULL); |
|
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1337 } |
|
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|
1338 count ++; |
|
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1339 |
|
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1340 /* If constant odd byte count, move the last byte. */ |
|
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|
1341 if (lastbyte) |
|
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|
1342 output_asm_insn ("movb (%1), (%0)", operands); |
|
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1343 else if (!CONSTANT_P (operands[2])) |
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1344 { |
|
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1345 /* Output the destination label for the zero byte count check. */ |
|
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|
1346 sprintf (buf, "\nmovestrhi%d:", count); |
|
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|
1347 output_asm_insn (buf, NULL); |
|
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1348 count++; |
| 0 | 1349 |
|
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1350 /* If we did word moves, check for trailing last byte. */ |
|
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1351 if (unroll) |
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1352 { |
|
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|
1353 sprintf (buf, "bcc movestrhi%d", count); |
|
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|
1354 output_asm_insn (buf, NULL); |
|
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|
1355 output_asm_insn ("movb (%1), (%0)", operands); |
|
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|
1356 sprintf (buf, "\nmovestrhi%d:", count); |
|
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|
1357 output_asm_insn (buf, NULL); |
|
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|
1358 count++; |
|
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1359 } |
|
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|
1360 } |
|
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1361 |
| 0 | 1362 return ""; |
| 1363 } | |
| 1364 | |
| 1365 /* This function checks whether a real value can be encoded as | |
| 1366 a literal, i.e., addressing mode 27. In that mode, real values | |
| 1367 are one word values, so the remaining 48 bits have to be zero. */ | |
| 1368 int | |
| 1369 legitimate_const_double_p (rtx address) | |
| 1370 { | |
| 1371 long sval[2]; | |
| 111 | 1372 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (address), sval); |
| 0 | 1373 if ((sval[0] & 0xffff) == 0 && sval[1] == 0) |
| 1374 return 1; | |
| 1375 return 0; | |
| 1376 } | |
| 1377 | |
| 111 | 1378 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */ |
| 1379 static bool | |
| 1380 pdp11_can_change_mode_class (machine_mode from, | |
| 1381 machine_mode to, | |
| 1382 reg_class_t rclass) | |
|
67
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|
1383 { |
|
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1384 /* Also, FPU registers contain a whole float value and the parts of |
|
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|
1385 it are not separately accessible. |
|
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|
1386 |
|
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|
1387 So we disallow all mode changes involving FPRs. */ |
|
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|
1388 if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to)) |
| 111 | 1389 return false; |
|
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|
1390 |
| 111 | 1391 return !reg_classes_intersect_p (FPU_REGS, rclass); |
|
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1392 } |
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1393 |
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1394 /* TARGET_PREFERRED_RELOAD_CLASS |
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1395 |
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1396 Given an rtx X being reloaded into a reg required to be |
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1397 in class CLASS, return the class of reg to actually use. |
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1398 In general this is just CLASS; but on some machines |
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1399 in some cases it is preferable to use a more restrictive class. |
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1400 |
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1401 loading is easier into LOAD_FPU_REGS than FPU_REGS! */ |
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1402 |
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1403 static reg_class_t |
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1404 pdp11_preferred_reload_class (rtx x, reg_class_t rclass) |
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1405 { |
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1406 if (rclass == FPU_REGS) |
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1407 return LOAD_FPU_REGS; |
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1408 if (rclass == ALL_REGS) |
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1409 { |
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1410 if (FLOAT_MODE_P (GET_MODE (x))) |
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1411 return LOAD_FPU_REGS; |
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1412 else |
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1413 return GENERAL_REGS; |
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1414 } |
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1415 return rclass; |
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1416 } |
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1417 |
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1418 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS |
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1419 |
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1420 Given an rtx X being reloaded into a reg required to be |
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1421 in class CLASS, return the class of reg to actually use. |
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1422 In general this is just CLASS; but on some machines |
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1423 in some cases it is preferable to use a more restrictive class. |
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1424 |
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1425 loading is easier into LOAD_FPU_REGS than FPU_REGS! */ |
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1426 |
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1427 static reg_class_t |
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1428 pdp11_preferred_output_reload_class (rtx x, reg_class_t rclass) |
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1429 { |
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1430 if (rclass == FPU_REGS) |
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1431 return LOAD_FPU_REGS; |
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1432 if (rclass == ALL_REGS) |
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1433 { |
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1434 if (FLOAT_MODE_P (GET_MODE (x))) |
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1435 return LOAD_FPU_REGS; |
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1436 else |
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1437 return GENERAL_REGS; |
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1438 } |
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1439 return rclass; |
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1440 } |
|
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1441 |
|
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1442 |
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1443 /* TARGET_SECONDARY_RELOAD. |
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1444 |
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1445 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an |
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1446 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else |
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1447 can be loade/stored directly. */ |
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|
1448 static reg_class_t |
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1449 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED, |
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1450 rtx x, |
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1451 reg_class_t reload_class, |
| 111 | 1452 machine_mode reload_mode ATTRIBUTE_UNUSED, |
|
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1453 secondary_reload_info *sri ATTRIBUTE_UNUSED) |
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1454 { |
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1455 if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG || |
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1456 REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS) |
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1457 return NO_REGS; |
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1458 |
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1459 return LOAD_FPU_REGS; |
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1460 } |
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1461 |
| 111 | 1462 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. |
|
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1463 |
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1464 The answer is yes if we're going between general register and FPU |
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1465 registers. The mode doesn't matter in making this check. |
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1466 */ |
| 111 | 1467 static bool |
| 1468 pdp11_secondary_memory_needed (machine_mode, reg_class_t c1, reg_class_t c2) | |
|
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1469 { |
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1470 int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || |
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1471 c1 == FPU_REGS); |
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1472 int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || |
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1473 c2 == FPU_REGS); |
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1474 |
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1475 return (fromfloat != tofloat); |
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1476 } |
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1477 |
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1478 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
|
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1479 that is a valid memory address for an instruction. |
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1480 The MODE argument is the machine mode for the MEM expression |
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1481 that wants to use this address. |
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1482 |
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|
1483 */ |
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1484 |
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63
diff
changeset
|
1485 static bool |
| 111 | 1486 pdp11_legitimate_address_p (machine_mode mode, |
|
67
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|
1487 rtx operand, bool strict) |
|
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|
1488 { |
|
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changeset
|
1489 rtx xfoob; |
|
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|
1490 |
|
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parents:
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|
1491 /* accept @#address */ |
|
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|
1492 if (CONSTANT_ADDRESS_P (operand)) |
|
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|
1493 return true; |
|
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|
1494 |
|
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parents:
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|
1495 switch (GET_CODE (operand)) |
|
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parents:
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|
1496 { |
|
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parents:
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diff
changeset
|
1497 case REG: |
|
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parents:
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changeset
|
1498 /* accept (R0) */ |
|
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parents:
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changeset
|
1499 return !strict || REGNO_OK_FOR_BASE_P (REGNO (operand)); |
|
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parents:
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diff
changeset
|
1500 |
|
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parents:
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diff
changeset
|
1501 case PLUS: |
|
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parents:
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|
1502 /* accept X(R0) */ |
|
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parents:
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diff
changeset
|
1503 return GET_CODE (XEXP (operand, 0)) == REG |
|
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parents:
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|
1504 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))) |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1505 && CONSTANT_ADDRESS_P (XEXP (operand, 1)); |
|
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parents:
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|
1506 |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
1507 case PRE_DEC: |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1508 /* accept -(R0) */ |
|
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|
1509 return GET_CODE (XEXP (operand, 0)) == REG |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1510 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))); |
|
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parents:
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changeset
|
1511 |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
1512 case POST_INC: |
|
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parents:
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changeset
|
1513 /* accept (R0)+ */ |
|
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parents:
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diff
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|
1514 return GET_CODE (XEXP (operand, 0)) == REG |
|
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parents:
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|
1515 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))); |
|
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parents:
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changeset
|
1516 |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1517 case PRE_MODIFY: |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1518 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */ |
|
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parents:
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|
1519 return GET_CODE (XEXP (operand, 0)) == REG |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1520 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1521 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1522 && GET_CODE (XEXP (xfoob, 0)) == REG |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1523 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1524 && CONSTANT_P (XEXP (xfoob, 1)) |
|
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parents:
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diff
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|
1525 && INTVAL (XEXP (xfoob,1)) == -2; |
|
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parents:
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diff
changeset
|
1526 |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1527 case POST_MODIFY: |
|
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parents:
63
diff
changeset
|
1528 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */ |
|
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diff
changeset
|
1529 return GET_CODE (XEXP (operand, 0)) == REG |
|
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parents:
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diff
changeset
|
1530 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1531 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1532 && GET_CODE (XEXP (xfoob, 0)) == REG |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1533 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1534 && CONSTANT_P (XEXP (xfoob, 1)) |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1535 && INTVAL (XEXP (xfoob,1)) == 2; |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1536 |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1537 case MEM: |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1538 /* handle another level of indirection ! */ |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1539 xfoob = XEXP (operand, 0); |
|
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diff
changeset
|
1540 |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1541 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1542 also forbidden for float, because we have to handle this |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1543 in output_move_double and/or output_move_quad() - we could |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1544 do it, but currently it's not worth it!!! |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1545 now that DFmode cannot go into CPU register file, |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1546 maybe I should allow float ... |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1547 but then I have to handle memory-to-memory moves in movdf ?? */ |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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63
diff
changeset
|
1548 if (GET_MODE_BITSIZE(mode) > 16) |
|
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diff
changeset
|
1549 return false; |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1550 |
|
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63
diff
changeset
|
1551 /* accept @address */ |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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63
diff
changeset
|
1552 if (CONSTANT_ADDRESS_P (xfoob)) |
|
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diff
changeset
|
1553 return true; |
|
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diff
changeset
|
1554 |
|
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diff
changeset
|
1555 switch (GET_CODE (xfoob)) |
|
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diff
changeset
|
1556 { |
|
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diff
changeset
|
1557 case REG: |
|
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diff
changeset
|
1558 /* accept @(R0) - which is @0(R0) */ |
|
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63
diff
changeset
|
1559 return !strict || REGNO_OK_FOR_BASE_P(REGNO (xfoob)); |
|
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diff
changeset
|
1560 |
|
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parents:
63
diff
changeset
|
1561 case PLUS: |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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63
diff
changeset
|
1562 /* accept @X(R0) */ |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1563 return GET_CODE (XEXP (xfoob, 0)) == REG |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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63
diff
changeset
|
1564 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))) |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1565 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1)); |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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63
diff
changeset
|
1566 |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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63
diff
changeset
|
1567 case PRE_DEC: |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1568 /* accept @-(R0) */ |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1569 return GET_CODE (XEXP (xfoob, 0)) == REG |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1570 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))); |
|
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63
diff
changeset
|
1571 |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1572 case POST_INC: |
|
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63
diff
changeset
|
1573 /* accept @(R0)+ */ |
|
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1574 return GET_CODE (XEXP (xfoob, 0)) == REG |
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1575 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))); |
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1576 |
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1577 default: |
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1578 /* anything else is invalid */ |
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1579 return false; |
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1580 } |
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1581 |
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1582 default: |
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1583 /* anything else is invalid */ |
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1584 return false; |
|
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1585 } |
|
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|
1586 } |
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|
1587 |
|
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|
1588 /* Return the class number of the smallest class containing |
|
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|
1589 reg number REGNO. */ |
|
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|
1590 enum reg_class |
|
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1591 pdp11_regno_reg_class (int regno) |
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1592 { |
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1593 if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) |
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1594 return GENERAL_REGS; |
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1595 else if (regno > AC3_REGNUM) |
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1596 return NO_LOAD_FPU_REGS; |
|
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1597 else if (regno >= AC0_REGNUM) |
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1598 return LOAD_FPU_REGS; |
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1599 else if (regno & 1) |
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1600 return MUL_REGS; |
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1601 else |
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1602 return GENERAL_REGS; |
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1603 } |
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1604 |
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1605 |
| 111 | 1606 int |
|
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1607 pdp11_sp_frame_offset (void) |
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1608 { |
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1609 int offset = 0, regno; |
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1610 offset = get_frame_size(); |
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1611 for (regno = 0; regno <= PC_REGNUM; regno++) |
| 111 | 1612 if (pdp11_saved_regno (regno)) |
|
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1613 offset += 2; |
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1614 for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++) |
| 111 | 1615 if (pdp11_saved_regno (regno)) |
|
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1616 offset += 8; |
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1617 |
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1618 return offset; |
|
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1619 } |
|
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1620 |
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1621 /* Return the offset between two registers, one to be eliminated, and the other |
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1622 its replacement, at the start of a routine. */ |
|
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1623 |
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1624 int |
|
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1625 pdp11_initial_elimination_offset (int from, int to) |
|
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1626 { |
|
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1627 int spoff; |
|
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1628 |
|
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1629 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) |
|
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1630 return 4; |
|
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1631 else if (from == FRAME_POINTER_REGNUM |
|
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1632 && to == HARD_FRAME_POINTER_REGNUM) |
|
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|
1633 return 0; |
|
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|
1634 else |
|
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|
1635 { |
|
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|
1636 gcc_assert (to == STACK_POINTER_REGNUM); |
|
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|
1637 |
|
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|
1638 /* Get the size of the register save area. */ |
|
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1639 spoff = pdp11_sp_frame_offset (); |
|
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|
1640 if (from == FRAME_POINTER_REGNUM) |
|
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|
1641 return spoff; |
|
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|
1642 |
|
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|
1643 gcc_assert (from == ARG_POINTER_REGNUM); |
|
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1644 |
|
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1645 /* If there is a frame pointer, that is saved too. */ |
|
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|
1646 if (frame_pointer_needed) |
|
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|
1647 spoff += 2; |
|
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|
1648 |
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|
1649 /* Account for the saved PC in the function call. */ |
|
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|
1650 return spoff + 2; |
|
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|
1651 } |
|
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|
1652 } |
|
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1653 |
| 0 | 1654 /* A copy of output_addr_const modified for pdp11 expression syntax. |
| 1655 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't | |
| 1656 use, and for debugging output, which we don't support with this port either. | |
| 1657 So this copy should get called whenever needed. | |
| 1658 */ | |
| 1659 void | |
| 1660 output_addr_const_pdp11 (FILE *file, rtx x) | |
| 1661 { | |
| 1662 char buf[256]; | |
|
67
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|
1663 int i; |
|
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1664 |
| 0 | 1665 restart: |
| 1666 switch (GET_CODE (x)) | |
| 1667 { | |
| 1668 case PC: | |
| 1669 gcc_assert (flag_pic); | |
| 1670 putc ('.', file); | |
| 1671 break; | |
| 1672 | |
| 1673 case SYMBOL_REF: | |
| 1674 assemble_name (file, XSTR (x, 0)); | |
| 1675 break; | |
| 1676 | |
| 1677 case LABEL_REF: | |
| 1678 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0))); | |
| 1679 assemble_name (file, buf); | |
| 1680 break; | |
| 1681 | |
| 1682 case CODE_LABEL: | |
| 1683 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); | |
| 1684 assemble_name (file, buf); | |
| 1685 break; | |
| 1686 | |
| 1687 case CONST_INT: | |
|
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|
1688 i = INTVAL (x); |
|
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|
1689 if (i < 0) |
|
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|
1690 { |
|
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|
1691 i = -i; |
|
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|
1692 fprintf (file, "-"); |
|
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|
1693 } |
|
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|
1694 fprintf (file, "%#o", i & 0xffff); |
| 0 | 1695 break; |
| 1696 | |
| 1697 case CONST: | |
| 1698 /* This used to output parentheses around the expression, | |
| 1699 but that does not work on the 386 (either ATT or BSD assembler). */ | |
| 1700 output_addr_const_pdp11 (file, XEXP (x, 0)); | |
| 1701 break; | |
| 1702 | |
| 1703 case CONST_DOUBLE: | |
| 1704 if (GET_MODE (x) == VOIDmode) | |
| 1705 { | |
| 1706 /* We can use %o if the number is one word and positive. */ | |
| 1707 gcc_assert (!CONST_DOUBLE_HIGH (x)); | |
| 1708 fprintf (file, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x)); | |
| 1709 } | |
| 1710 else | |
| 1711 /* We can't handle floating point constants; | |
| 1712 PRINT_OPERAND must handle them. */ | |
| 1713 output_operand_lossage ("floating constant misused"); | |
| 1714 break; | |
| 1715 | |
| 1716 case PLUS: | |
| 1717 /* Some assemblers need integer constants to appear last (e.g. masm). */ | |
| 1718 if (GET_CODE (XEXP (x, 0)) == CONST_INT) | |
| 1719 { | |
| 1720 output_addr_const_pdp11 (file, XEXP (x, 1)); | |
| 1721 if (INTVAL (XEXP (x, 0)) >= 0) | |
| 1722 fprintf (file, "+"); | |
| 1723 output_addr_const_pdp11 (file, XEXP (x, 0)); | |
| 1724 } | |
| 1725 else | |
| 1726 { | |
| 1727 output_addr_const_pdp11 (file, XEXP (x, 0)); | |
| 1728 if (INTVAL (XEXP (x, 1)) >= 0) | |
| 1729 fprintf (file, "+"); | |
| 1730 output_addr_const_pdp11 (file, XEXP (x, 1)); | |
| 1731 } | |
| 1732 break; | |
| 1733 | |
| 1734 case MINUS: | |
| 1735 /* Avoid outputting things like x-x or x+5-x, | |
| 1736 since some assemblers can't handle that. */ | |
| 1737 x = simplify_subtraction (x); | |
| 1738 if (GET_CODE (x) != MINUS) | |
| 1739 goto restart; | |
| 1740 | |
| 1741 output_addr_const_pdp11 (file, XEXP (x, 0)); | |
|
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1742 if (GET_CODE (XEXP (x, 1)) != CONST_INT |
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1743 || INTVAL (XEXP (x, 1)) >= 0) |
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1744 fprintf (file, "-"); |
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1745 output_addr_const_pdp11 (file, XEXP (x, 1)); |
| 0 | 1746 break; |
| 1747 | |
| 1748 case ZERO_EXTEND: | |
| 1749 case SIGN_EXTEND: | |
| 1750 output_addr_const_pdp11 (file, XEXP (x, 0)); | |
| 1751 break; | |
| 1752 | |
| 1753 default: | |
| 1754 output_operand_lossage ("invalid expression as operand"); | |
| 1755 } | |
| 1756 } | |
| 1757 | |
| 1758 /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
| 1759 | |
| 1760 static bool | |
| 1761 pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) | |
| 1762 { | |
|
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1763 /* Integers 32 bits and under, and scalar floats (if FPU), are returned |
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1764 in registers. The rest go into memory. */ |
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1765 return (TYPE_MODE (type) == DImode |
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1766 || (FLOAT_MODE_P (TYPE_MODE (type)) && ! TARGET_AC0) |
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1767 || TREE_CODE (type) == VECTOR_TYPE |
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1768 || COMPLEX_MODE_P (TYPE_MODE (type))); |
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1769 } |
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1770 |
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1771 /* Worker function for TARGET_FUNCTION_VALUE. |
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1772 |
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1773 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */ |
| 0 | 1774 |
|
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1775 static rtx |
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1776 pdp11_function_value (const_tree valtype, |
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1777 const_tree fntype_or_decl ATTRIBUTE_UNUSED, |
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1778 bool outgoing ATTRIBUTE_UNUSED) |
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1779 { |
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1780 return gen_rtx_REG (TYPE_MODE (valtype), |
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1781 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype))); |
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1782 } |
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1783 |
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1784 /* Worker function for TARGET_LIBCALL_VALUE. */ |
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1785 |
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1786 static rtx |
| 111 | 1787 pdp11_libcall_value (machine_mode mode, |
|
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1788 const_rtx fun ATTRIBUTE_UNUSED) |
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1789 { |
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1790 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG(mode)); |
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1791 } |
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1792 |
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1793 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. |
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1794 |
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1795 On the pdp, the first "output" reg is the only register thus used. |
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1796 |
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1797 maybe ac0 ? - as option someday! */ |
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1798 |
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1799 static bool |
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1800 pdp11_function_value_regno_p (const unsigned int regno) |
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1801 { |
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1802 return (regno == RETVAL_REGNUM) || (TARGET_AC0 && (regno == AC0_REGNUM)); |
| 0 | 1803 } |
|
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1804 |
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1805 /* Worker function for TARGET_TRAMPOLINE_INIT. |
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1806 |
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1807 trampoline - how should i do it in separate i+d ? |
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1808 have some allocate_trampoline magic??? |
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1809 |
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1810 the following should work for shared I/D: |
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1811 |
|
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1812 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM |
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1813 JMP @#FUNCTION 000137 0x0000 <- FUNCTION |
|
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1814 */ |
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1815 |
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1816 static void |
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1817 pdp11_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) |
|
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1818 { |
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1819 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
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1820 rtx mem; |
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1821 |
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1822 gcc_assert (!TARGET_SPLIT); |
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1823 |
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1824 mem = adjust_address (m_tramp, HImode, 0); |
|
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1825 emit_move_insn (mem, GEN_INT (012700+STATIC_CHAIN_REGNUM)); |
|
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1826 mem = adjust_address (m_tramp, HImode, 2); |
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1827 emit_move_insn (mem, chain_value); |
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1828 mem = adjust_address (m_tramp, HImode, 4); |
|
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1829 emit_move_insn (mem, GEN_INT (000137)); |
|
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1830 emit_move_insn (mem, fnaddr); |
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1831 } |
|
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1832 |
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1833 /* Worker function for TARGET_FUNCTION_ARG. |
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1834 |
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1835 Determine where to put an argument to a function. |
|
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1836 Value is zero to push the argument on the stack, |
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1837 or a hard register in which to store the argument. |
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1838 |
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1839 MODE is the argument's machine mode. |
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1840 TYPE is the data type of the argument (as a tree). |
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1841 This is null for libcalls where that information may |
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1842 not be available. |
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1843 CUM is a variable of type CUMULATIVE_ARGS which gives info about |
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1844 the preceding args and about the function being called. |
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1845 NAMED is nonzero if this argument is a named parameter |
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1846 (otherwise it is an extra parameter matching an ellipsis). */ |
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1847 |
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1848 static rtx |
| 111 | 1849 pdp11_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED, |
| 1850 machine_mode mode ATTRIBUTE_UNUSED, | |
|
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1851 const_tree type ATTRIBUTE_UNUSED, |
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1852 bool named ATTRIBUTE_UNUSED) |
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1853 { |
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1854 return NULL_RTX; |
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1855 } |
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1856 |
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1857 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. |
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1858 |
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1859 Update the data in CUM to advance over an argument of mode MODE and |
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1860 data type TYPE. (TYPE is null for libcalls where that information |
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1861 may not be available.) */ |
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1862 |
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1863 static void |
| 111 | 1864 pdp11_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, |
|
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1865 const_tree type, bool named ATTRIBUTE_UNUSED) |
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1866 { |
| 111 | 1867 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
| 1868 | |
|
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1869 *cum += (mode != BLKmode |
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1870 ? GET_MODE_SIZE (mode) |
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1871 : int_size_in_bytes (type)); |
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1872 } |
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1873 |
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1874 /* Make sure everything's fine if we *don't* have an FPU. |
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1875 This assumes that putting a register in fixed_regs will keep the |
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1876 compiler's mitts completely off it. We don't bother to zero it out |
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1877 of register classes. Also fix incompatible register naming with |
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1878 the UNIX assembler. */ |
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1879 |
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1880 static void |
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1881 pdp11_conditional_register_usage (void) |
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1882 { |
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1883 int i; |
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1884 HARD_REG_SET x; |
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1885 if (!TARGET_FPU) |
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1886 { |
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1887 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); |
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1888 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) |
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1889 if (TEST_HARD_REG_BIT (x, i)) |
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1890 fixed_regs[i] = call_used_regs[i] = 1; |
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1891 } |
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1892 |
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1893 if (TARGET_AC0) |
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1894 call_used_regs[AC0_REGNUM] = 1; |
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1895 if (TARGET_UNIX_ASM) |
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1896 { |
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1897 /* Change names of FPU registers for the UNIX assembler. */ |
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1898 reg_names[8] = "fr0"; |
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1899 reg_names[9] = "fr1"; |
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1900 reg_names[10] = "fr2"; |
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1901 reg_names[11] = "fr3"; |
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1902 reg_names[12] = "fr4"; |
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1903 reg_names[13] = "fr5"; |
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1904 } |
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1905 } |
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1906 |
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1907 static section * |
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1908 pdp11_function_section (tree decl ATTRIBUTE_UNUSED, |
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1909 enum node_frequency freq ATTRIBUTE_UNUSED, |
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1910 bool startup ATTRIBUTE_UNUSED, |
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1911 bool exit ATTRIBUTE_UNUSED) |
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1912 { |
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1913 return NULL; |
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1914 } |
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1915 |
| 111 | 1916 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ |
| 1917 | |
| 1918 static bool | |
| 1919 pdp11_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
| 1920 { | |
| 1921 return GET_CODE (x) != CONST_DOUBLE || legitimate_const_double_p (x); | |
| 1922 } | |
| 1923 | |
| 1924 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ | |
| 1925 | |
| 1926 static bool | |
| 1927 pdp11_scalar_mode_supported_p (scalar_mode mode) | |
| 1928 { | |
| 1929 /* Support SFmode even with -mfloat64. */ | |
| 1930 if (mode == SFmode) | |
| 1931 return true; | |
| 1932 return default_scalar_mode_supported_p (mode); | |
| 1933 } | |
| 1934 | |
| 1935 int | |
| 1936 pdp11_branch_cost () | |
| 1937 { | |
| 1938 return (TARGET_BRANCH_CHEAP ? 0 : 1); | |
| 1939 } | |
| 1940 | |
| 1941 /* Implement TARGET_HARD_REGNO_NREGS. */ | |
| 1942 | |
| 1943 static unsigned int | |
| 1944 pdp11_hard_regno_nregs (unsigned int regno, machine_mode mode) | |
| 1945 { | |
| 1946 if (regno <= PC_REGNUM) | |
| 1947 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); | |
| 1948 return 1; | |
| 1949 } | |
| 1950 | |
| 1951 /* Implement TARGET_HARD_REGNO_MODE_OK. On the pdp, the cpu registers | |
| 1952 can hold any mode other than float (because otherwise we may end up | |
| 1953 being asked to move from CPU to FPU register, which isn't a valid | |
| 1954 operation on the PDP11). For CPU registers, check alignment. | |
| 1955 | |
| 1956 FPU accepts SF and DF but actually holds a DF - simplifies life! */ | |
| 1957 | |
| 1958 static bool | |
| 1959 pdp11_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
| 1960 { | |
| 1961 if (regno <= PC_REGNUM) | |
| 1962 return (GET_MODE_BITSIZE (mode) <= 16 | |
| 1963 || (GET_MODE_BITSIZE (mode) >= 32 | |
| 1964 && !(regno & 1) | |
| 1965 && !FLOAT_MODE_P (mode))); | |
| 1966 | |
| 1967 return FLOAT_MODE_P (mode); | |
| 1968 } | |
| 1969 | |
| 1970 /* Implement TARGET_MODES_TIEABLE_P. */ | |
| 1971 | |
| 1972 static bool | |
| 1973 pdp11_modes_tieable_p (machine_mode, machine_mode) | |
| 1974 { | |
| 1975 return false; | |
| 1976 } | |
| 1977 | |
|
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1978 struct gcc_target targetm = TARGET_INITIALIZER; |