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1 ;; Constraint definitions for RS6000
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2 ;; Copyright (C) 2006-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Available constraint letters: e k q t u A B C D S T
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21
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22 ;; Register constraints
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23
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24 (define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]"
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25 "@internal")
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26
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27 (define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]"
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28 "@internal")
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29
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30 (define_register_constraint "b" "BASE_REGS"
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31 "@internal")
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32
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33 (define_register_constraint "h" "SPECIAL_REGS"
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34 "@internal")
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35
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36 (define_register_constraint "c" "CTR_REGS"
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37 "@internal")
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38
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39 (define_register_constraint "l" "LINK_REGS"
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40 "@internal")
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41
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42 (define_register_constraint "v" "ALTIVEC_REGS"
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43 "@internal")
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44
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45 (define_register_constraint "x" "CR0_REGS"
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46 "@internal")
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47
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48 (define_register_constraint "y" "CR_REGS"
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49 "@internal")
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50
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51 (define_register_constraint "z" "CA_REGS"
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52 "@internal")
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53
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54 ;; Use w as a prefix to add VSX modes
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55 ;; any VSX register
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56 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
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57 "Any VSX register if the -mvsx option was used or NO_REGS.")
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58
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59 (define_register_constraint "wb" "rs6000_constraints[RS6000_CONSTRAINT_wb]"
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60 "Altivec register if the -mpower9-dform option was used or NO_REGS.")
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61
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62 ;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits.
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63 ;; It is currently used for that purpose in LLVM.
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64
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65 (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"
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66 "VSX vector register to hold vector double data or NO_REGS.")
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67
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68 (define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
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69 "VSX register if the -mpower9-vector -m64 options were used or NO_REGS.")
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70
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71 (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
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72 "VSX vector register to hold vector float data or NO_REGS.")
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73
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74 (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
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75 "If -mmfpgpr was used, a floating point register or NO_REGS.")
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76
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77 (define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]"
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78 "Floating point register if direct moves are available, or NO_REGS.")
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79
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80 (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
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81 "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
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82
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83 (define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
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84 "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
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85
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86 (define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
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87 "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
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88
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89 (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
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90 "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
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91
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92 (define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"
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93 "VSX register if direct move instructions are enabled, or NO_REGS.")
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94
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95 ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
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96 ;; direct move directly, and movsf can't to move between the register sets.
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97 ;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
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98 (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
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99
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100 (define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]"
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101 "VSX register if the -mpower9-vector option was used or NO_REGS.")
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102
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103 (define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]"
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104 "VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.")
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105
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106 (define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]"
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107 "VSX register to use for IEEE 128-bit fp KFmode, or NO_REGS.")
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108
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109 (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
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110 "General purpose register if 64-bit instructions are enabled or NO_REGS.")
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111
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112 (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
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113 "VSX vector register to hold scalar double values or NO_REGS.")
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114
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115 (define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
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116 "VSX vector register to hold 128 bit integer or NO_REGS.")
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117
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118 (define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"
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119 "Altivec register to use for float/32-bit int loads/stores or NO_REGS.")
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120
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121 (define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
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122 "Altivec register to use for double loads/stores or NO_REGS.")
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123
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124 (define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
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125 "FP or VSX register to perform float operations under -mvsx or NO_REGS.")
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126
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127 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
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128 "Floating point register if the STFIWX instruction is enabled or NO_REGS.")
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129
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130 (define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
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131 "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.")
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132
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133 (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
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134 "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
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135
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136 (define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]"
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137 "BASE_REGS if 64-bit instructions are enabled or NO_REGS.")
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138
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139 ;; wB needs ISA 2.07 VUPKHSW
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140 (define_constraint "wB"
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141 "Signed 5-bit constant integer that can be loaded into an altivec register."
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142 (and (match_code "const_int")
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143 (and (match_test "TARGET_P8_VECTOR")
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144 (match_operand 0 "s5bit_cint_operand"))))
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145
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146 (define_constraint "wD"
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147 "Int constant that is the element number of the 64-bit scalar in a vector."
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148 (and (match_code "const_int")
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149 (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)")))
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150
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151 (define_constraint "wE"
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152 "Vector constant that can be loaded with the XXSPLTIB instruction."
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153 (match_test "xxspltib_constant_nosplit (op, mode)"))
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154
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155 ;; Extended fusion store
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156 (define_memory_constraint "wF"
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157 "Memory operand suitable for power9 fusion load/stores"
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158 (match_operand 0 "fusion_addis_mem_combo_load"))
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159
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160 ;; Fusion gpr load.
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161 (define_memory_constraint "wG"
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162 "Memory operand suitable for TOC fusion memory references"
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163 (match_operand 0 "toc_fusion_mem_wrapped"))
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164
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165 (define_register_constraint "wH" "rs6000_constraints[RS6000_CONSTRAINT_wH]"
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166 "Altivec register to hold 32-bit integers or NO_REGS.")
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167
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168 (define_register_constraint "wI" "rs6000_constraints[RS6000_CONSTRAINT_wI]"
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169 "FPR register to hold 32-bit integers or NO_REGS.")
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170
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171 (define_register_constraint "wJ" "rs6000_constraints[RS6000_CONSTRAINT_wJ]"
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172 "FPR register to hold 8/16-bit integers or NO_REGS.")
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173
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174 (define_register_constraint "wK" "rs6000_constraints[RS6000_CONSTRAINT_wK]"
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175 "Altivec register to hold 8/16-bit integers or NO_REGS.")
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176
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177 (define_constraint "wL"
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178 "Int constant that is the element number mfvsrld accesses in a vector."
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179 (and (match_code "const_int")
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180 (and (match_test "TARGET_DIRECT_MOVE_128")
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181 (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)"))))
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182
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183 ;; Generate the XXORC instruction to set a register to all 1's
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184 (define_constraint "wM"
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185 "Match vector constant with all 1's if the XXLORC instruction is available"
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186 (and (match_test "TARGET_P8_VECTOR")
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187 (match_operand 0 "all_ones_constant")))
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188
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189 ;; ISA 3.0 vector d-form addresses
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190 (define_memory_constraint "wO"
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191 "Memory operand suitable for the ISA 3.0 vector d-form instructions."
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192 (match_operand 0 "vsx_quad_dform_memory_operand"))
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193
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194 ;; Lq/stq validates the address for load/store quad
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195 (define_memory_constraint "wQ"
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196 "Memory operand suitable for the load/store quad instructions"
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197 (match_operand 0 "quad_memory_operand"))
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198
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199 (define_constraint "wS"
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200 "Vector constant that can be loaded with XXSPLTIB & sign extension."
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201 (match_test "xxspltib_constant_split (op, mode)"))
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202
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203 ;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form.
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204 ;; Used by LXSD/STXSD/LXSSP/STXSSP. In contrast to "Y", the multiple-of-four
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205 ;; offset is enforced for 32-bit too.
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206 (define_memory_constraint "wY"
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207 "Offsettable memory operand, with bottom 2 bits 0"
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208 (and (match_code "mem")
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209 (not (match_test "update_address_mem (op, mode)"))
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210 (match_test "mem_operand_ds_form (op, mode)")))
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211
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212 ;; Altivec style load/store that ignores the bottom bits of the address
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213 (define_memory_constraint "wZ"
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214 "Indexed or indirect memory operand, ignoring the bottom 4 bits"
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215 (match_operand 0 "altivec_indexed_or_indirect_operand"))
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216
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217 ;; Integer constraints
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218
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219 (define_constraint "I"
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220 "A signed 16-bit constant"
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221 (and (match_code "const_int")
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222 (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000")))
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223
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224 (define_constraint "J"
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225 "high-order 16 bits nonzero"
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226 (and (match_code "const_int")
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227 (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0")))
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228
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229 (define_constraint "K"
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230 "low-order 16 bits nonzero"
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231 (and (match_code "const_int")
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232 (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0")))
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233
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234 (define_constraint "L"
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235 "signed 16-bit constant shifted left 16 bits"
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236 (and (match_code "const_int")
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237 (match_test "((ival & 0xffff) == 0
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238 && (ival >> 31 == -1 || ival >> 31 == 0))")))
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239
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240 (define_constraint "M"
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241 "constant greater than 31"
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242 (and (match_code "const_int")
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243 (match_test "ival > 31")))
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244
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245 (define_constraint "N"
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246 "positive constant that is an exact power of two"
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247 (and (match_code "const_int")
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248 (match_test "ival > 0 && exact_log2 (ival) >= 0")))
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249
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250 (define_constraint "O"
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251 "constant zero"
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252 (and (match_code "const_int")
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253 (match_test "ival == 0")))
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254
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255 (define_constraint "P"
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256 "constant whose negation is signed 16-bit constant"
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257 (and (match_code "const_int")
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258 (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
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259
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260 ;; Floating-point constraints
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261
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262 (define_constraint "G"
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263 "Constant that can be copied into GPR with two insns for DF/DI
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264 and one for SF."
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265 (and (match_code "const_double")
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266 (match_test "num_insns_constant (op, mode)
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267 == (mode == SFmode ? 1 : 2)")))
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268
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269 (define_constraint "H"
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270 "DF/DI constant that takes three insns."
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271 (and (match_code "const_double")
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272 (match_test "num_insns_constant (op, mode) == 3")))
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273
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274 ;; Memory constraints
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275
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276 (define_memory_constraint "es"
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277 "A ``stable'' memory operand; that is, one which does not include any
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278 automodification of the base register. Unlike @samp{m}, this constraint
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279 can be used in @code{asm} statements that might access the operand
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280 several times, or that might not access it at all."
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281 (and (match_code "mem")
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282 (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
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283
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284 (define_memory_constraint "Q"
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285 "Memory operand that is an offset from a register (it is usually better
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286 to use @samp{m} or @samp{es} in @code{asm} statements)"
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287 (and (match_code "mem")
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288 (match_test "GET_CODE (XEXP (op, 0)) == REG")))
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289
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290 (define_memory_constraint "Y"
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291 "memory operand for 8 byte and 16 byte gpr load/store"
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292 (and (match_code "mem")
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293 (match_test "mem_operand_gpr (op, mode)")))
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294
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295 (define_memory_constraint "Z"
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296 "Memory operand that is an indexed or indirect from a register (it is
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297 usually better to use @samp{m} or @samp{es} in @code{asm} statements)"
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298 (match_operand 0 "indexed_or_indirect_operand"))
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299
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300 ;; Address constraints
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301
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302 (define_address_constraint "a"
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303 "Indexed or indirect address operand"
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304 (match_operand 0 "indexed_or_indirect_address"))
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305
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306 (define_constraint "R"
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307 "AIX TOC entry"
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308 (match_test "legitimate_constant_pool_address_p (op, QImode, false)"))
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309
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310 ;; General constraints
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311
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312 (define_constraint "U"
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313 "V.4 small data reference"
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314 (and (match_test "DEFAULT_ABI == ABI_V4")
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315 (match_test "small_data_operand (op, mode)")))
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316
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317 (define_constraint "W"
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318 "vector constant that does not require memory"
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319 (match_operand 0 "easy_vector_constant"))
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320
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321 (define_constraint "j"
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322 "Zero vector constant"
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323 (match_test "op == const0_rtx || op == CONST0_RTX (mode)"))
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