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111
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1 ; Options for the rs6000 port of the compiler
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2 ;
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3 ; Copyright (C) 2005-2017 Free Software Foundation, Inc.
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4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
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5 ;
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6 ; This file is part of GCC.
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7 ;
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8 ; GCC is free software; you can redistribute it and/or modify it under
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9 ; the terms of the GNU General Public License as published by the Free
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10 ; Software Foundation; either version 3, or (at your option) any later
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11 ; version.
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12 ;
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13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ; License for more details.
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17 ;
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18 ; You should have received a copy of the GNU General Public License
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19 ; along with GCC; see the file COPYING3. If not see
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20 ; <http://www.gnu.org/licenses/>.
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21
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22 HeaderInclude
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23 config/powerpcspe/powerpcspe-opts.h
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24
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25 ;; ISA flag bits (on/off)
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26 Variable
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27 HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
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28
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29 TargetSave
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30 HOST_WIDE_INT x_rs6000_isa_flags
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31
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32 ;; Miscellaneous flag bits that were set explicitly by the user
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33 Variable
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34 HOST_WIDE_INT rs6000_isa_flags_explicit
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35
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36 TargetSave
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37 HOST_WIDE_INT x_rs6000_isa_flags_explicit
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38
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39 ;; Current processor
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40 TargetVariable
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41 enum processor_type rs6000_cpu = PROCESSOR_PPC603
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42
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43 ;; Always emit branch hint bits.
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44 TargetVariable
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45 unsigned char rs6000_always_hint
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46
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47 ;; Schedule instructions for group formation.
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48 TargetVariable
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49 unsigned char rs6000_sched_groups
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50
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51 ;; Align branch targets.
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52 TargetVariable
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53 unsigned char rs6000_align_branch_targets
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54
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55 ;; Support for -msched-costly-dep option.
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56 TargetVariable
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57 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
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58
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59 ;; Support for -minsert-sched-nops option.
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60 TargetVariable
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61 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
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62
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63 ;; Non-zero to allow overriding loop alignment.
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64 TargetVariable
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65 unsigned char can_override_loop_align
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66
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67 ;; Which small data model to use (for System V targets only)
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68 TargetVariable
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69 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
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70
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71 ;; Bit size of immediate TLS offsets and string from which it is decoded.
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72 TargetVariable
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73 int rs6000_tls_size = 32
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74
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75 ;; ABI enumeration available for subtarget to use.
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76 TargetVariable
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77 enum rs6000_abi rs6000_current_abi = ABI_NONE
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78
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79 ;; Type of traceback to use.
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80 TargetVariable
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81 enum rs6000_traceback_type rs6000_traceback = traceback_default
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82
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83 ;; Control alignment for fields within structures.
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84 TargetVariable
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85 unsigned char rs6000_alignment_flags
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86
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87 ;; Code model for 64-bit linux.
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88 TargetVariable
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89 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
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90
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91 ;; What type of reciprocal estimation instructions to generate
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92 TargetVariable
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93 unsigned int rs6000_recip_control
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94
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95 ;; Mask of what builtin functions are allowed
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96 TargetVariable
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97 HOST_WIDE_INT rs6000_builtin_mask
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98
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99 ;; Debug flags
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100 TargetVariable
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101 unsigned int rs6000_debug
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102
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103 ;; This option existed in the past, but now is always on.
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104 mpowerpc
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105 Target RejectNegative Undocumented Ignore
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106
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107 mpowerpc64
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108 Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
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109 Use PowerPC-64 instruction set.
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110
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111 mpowerpc-gpopt
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112 Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
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113 Use PowerPC General Purpose group optional instructions.
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114
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115 mpowerpc-gfxopt
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116 Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
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117 Use PowerPC Graphics group optional instructions.
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118
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119 mmfcrf
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120 Target Report Mask(MFCRF) Var(rs6000_isa_flags)
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121 Use PowerPC V2.01 single field mfcr instruction.
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122
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123 mpopcntb
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124 Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
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125 Use PowerPC V2.02 popcntb instruction.
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126
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127 mfprnd
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128 Target Report Mask(FPRND) Var(rs6000_isa_flags)
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129 Use PowerPC V2.02 floating point rounding instructions.
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130
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131 mcmpb
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132 Target Report Mask(CMPB) Var(rs6000_isa_flags)
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133 Use PowerPC V2.05 compare bytes instruction.
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134
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135 mmfpgpr
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136 Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
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137 Use extended PowerPC V2.05 move floating point to/from GPR instructions.
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138
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139 maltivec
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140 Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
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141 Use AltiVec instructions.
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142
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143 maltivec=le
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144 Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
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145 Generate AltiVec instructions using little-endian element order.
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146
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147 maltivec=be
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148 Target Report RejectNegative Var(rs6000_altivec_element_order, 2)
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149 Generate AltiVec instructions using big-endian element order.
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150
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151 mhard-dfp
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152 Target Report Mask(DFP) Var(rs6000_isa_flags)
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153 Use decimal floating point instructions.
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154
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155 mmulhw
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156 Target Report Mask(MULHW) Var(rs6000_isa_flags)
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157 Use 4xx half-word multiply instructions.
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158
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159 mdlmzb
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160 Target Report Mask(DLMZB) Var(rs6000_isa_flags)
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161 Use 4xx string-search dlmzb instruction.
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162
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163 mmultiple
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164 Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
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165 Generate load/store multiple instructions.
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166
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167 mstring
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168 Target Report Mask(STRING) Var(rs6000_isa_flags)
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169 Generate string instructions for block moves.
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170
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171 msoft-float
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172 Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
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173 Do not use hardware floating point.
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174
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175 mhard-float
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176 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
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177 Use hardware floating point.
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178
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179 mpopcntd
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180 Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
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181 Use PowerPC V2.06 popcntd instruction.
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182
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183 mfriz
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184 Target Report Var(TARGET_FRIZ) Init(-1) Save
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185 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
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186
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187 mveclibabi=
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188 Target RejectNegative Joined Var(rs6000_veclibabi_name)
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189 Vector library ABI to use.
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190
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191 mvsx
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192 Target Report Mask(VSX) Var(rs6000_isa_flags)
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193 Use vector/scalar (VSX) instructions.
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194
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195 mvsx-scalar-float
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196 Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1)
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197 ; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default)
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198
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199 mvsx-scalar-double
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200 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
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201 ; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)
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202
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203 mvsx-scalar-memory
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204 Target Undocumented Report Alias(mupper-regs-df)
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205
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206 mvsx-align-128
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207 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
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208 ; If -mvsx, set alignment to 128 bits instead of 32/64
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209
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210 mallow-movmisalign
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211 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
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212 ; Allow the movmisalign in DF/DI vectors
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213
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214 mefficient-unaligned-vsx
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215 Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
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216 ; Consider unaligned VSX vector and fp accesses to be efficient
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217
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218 mallow-df-permute
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219 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save
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220 ; Allow permutation of DF/DI vectors
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221
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222 msched-groups
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223 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
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224 ; Explicitly set rs6000_sched_groups
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225
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226 malways-hint
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227 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
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228 ; Explicitly set rs6000_always_hint
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229
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230 malign-branch-targets
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231 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
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232 ; Explicitly set rs6000_align_branch_targets
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233
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234 mvectorize-builtins
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235 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save
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236 ; Explicitly control whether we vectorize the builtins or not.
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237
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238 mno-update
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239 Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
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240 Do not generate load/store with update instructions.
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241
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242 mupdate
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243 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
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244 Generate load/store with update instructions.
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245
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246 msingle-pic-base
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247 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
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248 Do not load the PIC register in function prologues.
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249
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250 mavoid-indexed-addresses
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251 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
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252 Avoid generation of indexed load/store instructions when possible.
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253
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254 mtls-markers
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255 Target Report Var(tls_markers) Init(1) Save
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256 Mark __tls_get_addr calls with argument info.
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257
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258 msched-epilog
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259 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
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260
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261 msched-prolog
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262 Target Report Var(TARGET_SCHED_PROLOG) Save
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263 Schedule the start and end of the procedure.
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264
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265 maix-struct-return
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266 Target Report RejectNegative Var(aix_struct_return) Save
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267 Return all structures in memory (AIX default).
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268
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269 msvr4-struct-return
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270 Target Report RejectNegative Var(aix_struct_return,0) Save
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271 Return small structures in registers (SVR4 default).
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272
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273 mxl-compat
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274 Target Report Var(TARGET_XL_COMPAT) Save
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275 Conform more closely to IBM XLC semantics.
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276
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277 mrecip
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278 Target Report
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279 Generate software reciprocal divide and square root for better throughput.
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280
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281 mrecip=
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282 Target Report RejectNegative Joined Var(rs6000_recip_name)
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283 Generate software reciprocal divide and square root for better throughput.
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284
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285 mrecip-precision
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286 Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
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287 Assume that the reciprocal estimate instructions provide more accuracy.
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288
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289 mno-fp-in-toc
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290 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
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291 Do not place floating point constants in TOC.
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292
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293 mfp-in-toc
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294 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
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295 Place floating point constants in TOC.
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296
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297 mno-sum-in-toc
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298 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
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299 Do not place symbol+offset constants in TOC.
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300
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301 msum-in-toc
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302 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
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303 Place symbol+offset constants in TOC.
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304
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305 ; Output only one TOC entry per module. Normally linking fails if
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306 ; there are more than 16K unique variables/constants in an executable. With
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307 ; this option, linking fails only if there are more than 16K modules, or
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308 ; if there are more than 16K unique variables/constant in a single module.
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309 ;
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310 ; This is at the cost of having 2 extra loads and one extra store per
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311 ; function, and one less allocable register.
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312 mminimal-toc
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313 Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
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314 Use only one TOC entry per procedure.
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315
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316 mfull-toc
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317 Target Report
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318 Put everything in the regular TOC.
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319
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320 mvrsave
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321 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
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322 Generate VRSAVE instructions when generating AltiVec code.
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323
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324 mvrsave=no
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325 Target RejectNegative Alias(mvrsave) NegativeAlias
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326 Deprecated option. Use -mno-vrsave instead.
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327
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328 mvrsave=yes
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329 Target RejectNegative Alias(mvrsave)
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330 Deprecated option. Use -mvrsave instead.
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331
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332 mblock-move-inline-limit=
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333 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
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334 Specify how many bytes should be moved inline before calling out to memcpy/memmove.
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335
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336 mblock-compare-inline-limit=
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337 Target Report Var(rs6000_block_compare_inline_limit) Init(5) RejectNegative Joined UInteger Save
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338 Specify the maximum number pairs of load instructions that should be generated inline for the compare. If the number needed exceeds the limit, a call to memcmp will be generated instead.
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339
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340 mstring-compare-inline-limit=
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341 Target Report Var(rs6000_string_compare_inline_limit) Init(8) RejectNegative Joined UInteger Save
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342 Specify the maximum number pairs of load instructions that should be generated inline for the compare. If the number needed exceeds the limit, a call to strncmp will be generated instead.
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343
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344 misel
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345 Target Report Mask(ISEL) Var(rs6000_isa_flags)
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346 Generate isel instructions.
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347
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348 misel=no
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349 Target RejectNegative Alias(misel) NegativeAlias
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350 Deprecated option. Use -mno-isel instead.
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351
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352 misel=yes
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353 Target RejectNegative Alias(misel)
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354 Deprecated option. Use -misel instead.
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355
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356 mspe
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357 Target Var(rs6000_spe) Save
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358 Generate SPE SIMD instructions on E500.
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359
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360 mpaired
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361 Target Var(rs6000_paired_float) Save
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362 Generate PPC750CL paired-single instructions.
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363
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364 mspe=no
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365 Target RejectNegative Alias(mspe) NegativeAlias
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366 Deprecated option. Use -mno-spe instead.
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367
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368 mspe=yes
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369 Target RejectNegative Alias(mspe)
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370 Deprecated option. Use -mspe instead.
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371
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372 mdebug=
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373 Target RejectNegative Joined
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374 -mdebug= Enable debug output.
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375
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376 mabi=altivec
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377 Target RejectNegative Var(rs6000_altivec_abi) Save
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378 Use the AltiVec ABI extensions.
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379
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380 mabi=no-altivec
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381 Target RejectNegative Var(rs6000_altivec_abi, 0)
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382 Do not use the AltiVec ABI extensions.
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383
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384 mabi=spe
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385 Target RejectNegative Var(rs6000_spe_abi) Save
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386 Use the SPE ABI extensions.
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387
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388 mabi=no-spe
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389 Target RejectNegative Var(rs6000_spe_abi, 0)
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390 Do not use the SPE ABI extensions.
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391
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392 mabi=elfv1
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393 Target RejectNegative Var(rs6000_elf_abi, 1) Save
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394 Use the ELFv1 ABI.
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395
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396 mabi=elfv2
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397 Target RejectNegative Var(rs6000_elf_abi, 2)
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398 Use the ELFv2 ABI.
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399
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400 ; These are here for testing during development only, do not document
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401 ; in the manual please.
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402
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403 ; If we want Darwin's struct-by-value-in-regs ABI.
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404 mabi=d64
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405 Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
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406
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407 mabi=d32
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408 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
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409
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410 mabi=ieeelongdouble
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411 Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save
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412
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413 mabi=ibmlongdouble
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414 Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0)
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415
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416 mcpu=
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417 Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
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418 -mcpu= Use features of and schedule code for given CPU.
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419
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420 mtune=
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421 Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
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422 -mtune= Schedule code for given CPU.
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423
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424 mtraceback=
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425 Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
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426 -mtraceback= Select full, part, or no traceback table.
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427
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428 Enum
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429 Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
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430
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431 EnumValue
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432 Enum(rs6000_traceback_type) String(full) Value(traceback_full)
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433
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434 EnumValue
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435 Enum(rs6000_traceback_type) String(part) Value(traceback_part)
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436
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437 EnumValue
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438 Enum(rs6000_traceback_type) String(no) Value(traceback_none)
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439
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440 mlongcall
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441 Target Report Var(rs6000_default_long_calls) Save
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442 Avoid all range limits on call instructions.
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443
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444 mgen-cell-microcode
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445 Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
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446 Generate Cell microcode.
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447
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448 mwarn-cell-microcode
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449 Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
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450 Warn when a Cell microcoded instruction is emitted.
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451
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452 mwarn-altivec-long
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453 Target Var(rs6000_warn_altivec_long) Init(1) Save
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454 Warn about deprecated 'vector long ...' AltiVec type usage.
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455
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456 mfloat-gprs=
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457 Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save
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458 -mfloat-gprs= Select GPR floating point method.
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459
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460 Enum
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461 Name(rs6000_float_gprs) Type(unsigned char)
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|
|
462 Valid arguments to -mfloat-gprs=:
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463
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464 EnumValue
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465 Enum(rs6000_float_gprs) String(yes) Value(1)
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466
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467 EnumValue
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468 Enum(rs6000_float_gprs) String(single) Value(1)
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469
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470 EnumValue
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471 Enum(rs6000_float_gprs) String(double) Value(2)
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472
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473 EnumValue
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474 Enum(rs6000_float_gprs) String(no) Value(0)
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|
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475
|
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476 mlong-double-
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477 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
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478 -mlong-double-<n> Specify size of long double (64 or 128 bits).
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479
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480 mlra
|
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481 Target Report Mask(LRA) Var(rs6000_isa_flags)
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482 Enable Local Register Allocation.
|
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483
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|
484 msched-costly-dep=
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485 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
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|
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486 Determine which dependences between insns are considered costly.
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487
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488 minsert-sched-nops=
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489 Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
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490 Specify which post scheduling nop insertion scheme to apply.
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491
|
|
|
492 malign-
|
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493 Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
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494 Specify alignment of structure fields default/natural.
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495
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496 Enum
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497 Name(rs6000_alignment_flags) Type(unsigned char)
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498 Valid arguments to -malign-:
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499
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500 EnumValue
|
|
|
501 Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
|
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502
|
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|
503 EnumValue
|
|
|
504 Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
|
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505
|
|
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506 mprioritize-restricted-insns=
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|
|
507 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
|
|
|
508 Specify scheduling priority for dispatch slot restricted insns.
|
|
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509
|
|
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510 msingle-float
|
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|
511 Target RejectNegative Var(rs6000_single_float) Save
|
|
|
512 Single-precision floating point unit.
|
|
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513
|
|
|
514 mdouble-float
|
|
|
515 Target RejectNegative Var(rs6000_double_float) Save
|
|
|
516 Double-precision floating point unit.
|
|
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517
|
|
|
518 msimple-fpu
|
|
|
519 Target RejectNegative Var(rs6000_simple_fpu) Save
|
|
|
520 Floating point unit does not support divide & sqrt.
|
|
|
521
|
|
|
522 mfpu=
|
|
|
523 Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
|
|
|
524 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu).
|
|
|
525
|
|
|
526 Enum
|
|
|
527 Name(fpu_type_t) Type(enum fpu_type_t)
|
|
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528
|
|
|
529 EnumValue
|
|
|
530 Enum(fpu_type_t) String(none) Value(FPU_NONE)
|
|
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531
|
|
|
532 EnumValue
|
|
|
533 Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
|
|
|
534
|
|
|
535 EnumValue
|
|
|
536 Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
|
|
|
537
|
|
|
538 EnumValue
|
|
|
539 Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
|
|
|
540
|
|
|
541 EnumValue
|
|
|
542 Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
|
|
|
543
|
|
|
544 mxilinx-fpu
|
|
|
545 Target Var(rs6000_xilinx_fpu) Save
|
|
|
546 Specify Xilinx FPU.
|
|
|
547
|
|
|
548 mpointers-to-nested-functions
|
|
|
549 Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
|
|
|
550 Use r11 to hold the static link in calls to functions via pointers.
|
|
|
551
|
|
|
552 msave-toc-indirect
|
|
|
553 Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
|
|
|
554 Save the TOC in the prologue for indirect calls rather than inline.
|
|
|
555
|
|
|
556 mvsx-timode
|
|
|
557 Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)
|
|
|
558 Allow 128-bit integers in VSX registers.
|
|
|
559
|
|
|
560 mpower8-fusion
|
|
|
561 Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
|
|
|
562 Fuse certain integer operations together for better performance on power8.
|
|
|
563
|
|
|
564 mpower8-fusion-sign
|
|
|
565 Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
|
|
|
566 Allow sign extension in fusion operations.
|
|
|
567
|
|
|
568 mpower8-vector
|
|
|
569 Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
|
|
|
570 Use vector and scalar instructions added in ISA 2.07.
|
|
|
571
|
|
|
572 mcrypto
|
|
|
573 Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
|
|
|
574 Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
|
|
|
575
|
|
|
576 mdirect-move
|
|
|
577 Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)
|
|
|
578 Use ISA 2.07 direct move between GPR & VSX register instructions.
|
|
|
579
|
|
|
580 mhtm
|
|
|
581 Target Report Mask(HTM) Var(rs6000_isa_flags)
|
|
|
582 Use ISA 2.07 transactional memory (HTM) instructions.
|
|
|
583
|
|
|
584 mquad-memory
|
|
|
585 Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
|
|
|
586 Generate the quad word memory instructions (lq/stq).
|
|
|
587
|
|
|
588 mquad-memory-atomic
|
|
|
589 Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
|
|
|
590 Generate the quad word memory atomic instructions (lqarx/stqcx).
|
|
|
591
|
|
|
592 mcompat-align-parm
|
|
|
593 Target Report Var(rs6000_compat_align_parm) Init(0) Save
|
|
|
594 Generate aggregate parameter passing code with at most 64-bit alignment.
|
|
|
595
|
|
|
596 mupper-regs-df
|
|
|
597 Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
|
|
|
598 Allow double variables in upper registers with -mcpu=power7 or -mvsx.
|
|
|
599
|
|
|
600 mupper-regs-sf
|
|
|
601 Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
|
|
|
602 Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector.
|
|
|
603
|
|
|
604 mupper-regs
|
|
|
605 Target Report Var(TARGET_UPPER_REGS) Init(-1) Save
|
|
|
606 Allow float/double variables in upper registers if cpu allows it.
|
|
|
607
|
|
|
608 mupper-regs-di
|
|
|
609 Target Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags)
|
|
|
610 Allow 64-bit integer variables in upper registers with -mcpu=power7 or -mvsx.
|
|
|
611
|
|
|
612 moptimize-swaps
|
|
|
613 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
|
|
|
614 Analyze and remove doubleword swaps from VSX computations.
|
|
|
615
|
|
|
616 mpower9-fusion
|
|
|
617 Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
|
|
|
618 Fuse certain operations together for better performance on power9.
|
|
|
619
|
|
|
620 mpower9-misc
|
|
|
621 Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
|
|
|
622 Use certain scalar instructions added in ISA 3.0.
|
|
|
623
|
|
|
624 mpower9-vector
|
|
|
625 Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
|
|
|
626 Use vector instructions added in ISA 3.0.
|
|
|
627
|
|
|
628 mpower9-dform-scalar
|
|
|
629 Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags)
|
|
|
630 Use scalar register+offset memory instructions added in ISA 3.0.
|
|
|
631
|
|
|
632 mpower9-dform-vector
|
|
|
633 Target Undocumented Mask(P9_DFORM_VECTOR) Var(rs6000_isa_flags)
|
|
|
634 Use vector register+offset memory instructions added in ISA 3.0.
|
|
|
635
|
|
|
636 mpower9-dform
|
|
|
637 Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
|
|
|
638 Use register+offset memory instructions added in ISA 3.0.
|
|
|
639
|
|
|
640 mpower9-minmax
|
|
|
641 Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
|
|
|
642 Use the new min/max instructions defined in ISA 3.0.
|
|
|
643
|
|
|
644 mtoc-fusion
|
|
|
645 Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
|
|
|
646 Fuse medium/large code model toc references with the memory instruction.
|
|
|
647
|
|
|
648 mmodulo
|
|
|
649 Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
|
|
|
650 Generate the integer modulo instructions.
|
|
|
651
|
|
|
652 ; We want to enable the internal support for the IEEE 128-bit floating point
|
|
|
653 ; type without necessarily enabling the __float128 keyword. This is to allow
|
|
|
654 ; Boost and other libraries that know about __float128 to work until the
|
|
|
655 ; official library support is finished.
|
|
|
656 mfloat128-type
|
|
|
657 Target Undocumented Mask(FLOAT128_TYPE) Var(rs6000_isa_flags)
|
|
|
658 Allow the IEEE 128-bit types without requiring the __float128 keyword.
|
|
|
659
|
|
|
660 mfloat128
|
|
|
661 Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
|
|
|
662 Enable IEEE 128-bit floating point via the __float128 keyword.
|
|
|
663
|
|
|
664 mfloat128-hardware
|
|
|
665 Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
|
|
|
666 Enable using IEEE 128-bit floating point instructions.
|
|
|
667
|
|
|
668 mfloat128-convert
|
|
|
669 Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
|
|
|
670 Enable default conversions between __float128 & long double.
|
|
|
671
|
|
|
672 mvsx-small-integer
|
|
|
673 Target Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags)
|
|
|
674 Enable small integers to be in VSX registers.
|
|
|
675
|
|
|
676 mstack-protector-guard=
|
|
|
677 Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
|
|
|
678 Use given stack-protector guard.
|
|
|
679
|
|
|
680 Enum
|
|
|
681 Name(stack_protector_guard) Type(enum stack_protector_guard)
|
|
|
682 Valid arguments to -mstack-protector-guard=:
|
|
|
683
|
|
|
684 EnumValue
|
|
|
685 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
|
|
|
686
|
|
|
687 EnumValue
|
|
|
688 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
|
|
|
689
|
|
|
690 mstack-protector-guard-reg=
|
|
|
691 Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
|
|
|
692 Use the given base register for addressing the stack-protector guard.
|
|
|
693
|
|
|
694 TargetVariable
|
|
|
695 int rs6000_stack_protector_guard_reg = 0
|
|
|
696
|
|
|
697 mstack-protector-guard-offset=
|
|
|
698 Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
|
|
|
699 Use the given offset for addressing the stack-protector guard.
|
|
|
700
|
|
|
701 TargetVariable
|
|
|
702 long rs6000_stack_protector_guard_offset = 0
|
