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111
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1 /* Definition of RISC-V target for GNU compiler.
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2 Copyright (C) 2011-2017 Free Software Foundation, Inc.
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3 Contributed by Andrew Waterman (andrew@sifive.com).
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4 Based on MIPS target for GNU compiler.
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5
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6 This file is part of GCC.
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7
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8 GCC is free software; you can redistribute it and/or modify
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9 it under the terms of the GNU General Public License as published by
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10 the Free Software Foundation; either version 3, or (at your option)
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11 any later version.
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12
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13 GCC is distributed in the hope that it will be useful,
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14 but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 GNU General Public License for more details.
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17
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18 You should have received a copy of the GNU General Public License
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19 along with GCC; see the file COPYING3. If not see
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20 <http://www.gnu.org/licenses/>. */
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21
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22 #ifndef GCC_RISCV_H
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23 #define GCC_RISCV_H
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24
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25 #include "config/riscv/riscv-opts.h"
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26
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27 /* Target CPU builtins. */
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28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
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29
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30 /* Default target_flags if no switches are specified */
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31
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32 #ifndef TARGET_DEFAULT
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33 #define TARGET_DEFAULT 0
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34 #endif
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35
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36 #ifndef RISCV_TUNE_STRING_DEFAULT
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37 #define RISCV_TUNE_STRING_DEFAULT "rocket"
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38 #endif
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39
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40 /* Support for a compile-time default CPU, et cetera. The rules are:
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41 --with-arch is ignored if -march is specified.
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42 --with-abi is ignored if -mabi is specified.
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43 --with-tune is ignored if -mtune is specified. */
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44 #define OPTION_DEFAULT_SPECS \
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45 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
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46 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
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47 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
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48
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49 #ifdef IN_LIBGCC2
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50 #undef TARGET_64BIT
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51 /* Make this compile time constant for libgcc2 */
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52 #define TARGET_64BIT (__riscv_xlen == 64)
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53 #endif /* IN_LIBGCC2 */
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54
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55 #undef ASM_SPEC
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56 #define ASM_SPEC "\
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57 %(subtarget_asm_debugging_spec) \
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58 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
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59 %{march=*} \
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60 %{mabi=*} \
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61 %(subtarget_asm_spec)"
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62
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63 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
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64
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65 #define LOCAL_LABEL_PREFIX "."
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66 #define USER_LABEL_PREFIX ""
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67
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68 /* Offsets recorded in opcodes are a multiple of this alignment factor.
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69 The default for this in 64-bit mode is 8, which causes problems with
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70 SFmode register saves. */
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71 #define DWARF_CIE_DATA_ALIGNMENT -4
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72
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73 /* The mapping from gcc register number to DWARF 2 CFA column number. */
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74 #define DWARF_FRAME_REGNUM(REGNO) \
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75 (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
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76
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77 /* The DWARF 2 CFA column which tracks the return address. */
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78 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
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79 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
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80
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81 /* Describe how we implement __builtin_eh_return. */
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82 #define EH_RETURN_DATA_REGNO(N) \
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83 ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
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84
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85 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
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86
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87 /* Target machine storage layout */
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88
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89 #define BITS_BIG_ENDIAN 0
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90 #define BYTES_BIG_ENDIAN 0
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91 #define WORDS_BIG_ENDIAN 0
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92
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93 #define MAX_BITS_PER_WORD 64
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94
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95 /* Width of a word, in units (bytes). */
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96 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
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97 #ifndef IN_LIBGCC2
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98 #define MIN_UNITS_PER_WORD 4
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99 #endif
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100
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101 /* The `Q' extension is not yet supported. */
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102 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
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103
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104 /* The largest type that can be passed in floating-point registers. */
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105 #define UNITS_PER_FP_ARG \
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106 (riscv_abi == ABI_ILP32 || riscv_abi == ABI_LP64 ? 0 : \
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107 riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F ? 4 : 8) \
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108
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109 /* Set the sizes of the core types. */
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110 #define SHORT_TYPE_SIZE 16
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111 #define INT_TYPE_SIZE 32
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112 #define LONG_LONG_TYPE_SIZE 64
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113 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
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114 #define LONG_TYPE_SIZE POINTER_SIZE
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115
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116 #define FLOAT_TYPE_SIZE 32
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117 #define DOUBLE_TYPE_SIZE 64
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118 #define LONG_DOUBLE_TYPE_SIZE 128
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119
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120 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
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121 #define PARM_BOUNDARY BITS_PER_WORD
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122
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123 /* Allocation boundary (in *bits*) for the code of a function. */
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124 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
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125
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126 /* There is no point aligning anything to a rounder boundary than this. */
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127 #define BIGGEST_ALIGNMENT 128
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128
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129 /* The user-level ISA permits unaligned accesses, but they are not required
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130 of the privileged architecture. */
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131 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
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132
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133 /* Define this if you wish to imitate the way many other C compilers
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134 handle alignment of bitfields and the structures that contain
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135 them.
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136
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137 The behavior is that the type written for a bit-field (`int',
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138 `short', or other integer type) imposes an alignment for the
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139 entire structure, as if the structure really did contain an
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140 ordinary field of that type. In addition, the bit-field is placed
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141 within the structure so that it would fit within such a field,
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142 not crossing a boundary for it.
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143
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144 Thus, on most machines, a bit-field whose type is written as `int'
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145 would not cross a four-byte boundary, and would force four-byte
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146 alignment for the whole structure. (The alignment used may not
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147 be four bytes; it is controlled by the other alignment
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148 parameters.)
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149
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150 If the macro is defined, its definition should be a C expression;
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151 a nonzero value for the expression enables this behavior. */
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152
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153 #define PCC_BITFIELD_TYPE_MATTERS 1
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154
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155 /* If defined, a C expression to compute the alignment for a static
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156 variable. TYPE is the data type, and ALIGN is the alignment that
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157 the object would ordinarily have. The value of this macro is used
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158 instead of that alignment to align the object.
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159
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160 If this macro is not defined, then ALIGN is used.
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161
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162 One use of this macro is to increase alignment of medium-size
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163 data to make it all fit in fewer cache lines. Another is to
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164 cause character arrays to be word-aligned so that `strcpy' calls
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165 that copy constants to character arrays can be done inline. */
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166
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167 #define DATA_ALIGNMENT(TYPE, ALIGN) \
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168 ((((ALIGN) < BITS_PER_WORD) \
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169 && (TREE_CODE (TYPE) == ARRAY_TYPE \
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170 || TREE_CODE (TYPE) == UNION_TYPE \
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171 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
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172
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173 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
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174 character arrays to be word-aligned so that `strcpy' calls that copy
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175 constants to character arrays can be done inline, and 'strcmp' can be
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176 optimised to use word loads. */
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177 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
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178 DATA_ALIGNMENT (TYPE, ALIGN)
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179
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180 /* Define if operations between registers always perform the operation
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181 on the full register even if a narrower mode is specified. */
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182 #define WORD_REGISTER_OPERATIONS 1
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183
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184 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
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185 moves. All other references are zero extended. */
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186 #define LOAD_EXTEND_OP(MODE) \
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187 (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
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188
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189 /* Define this macro if it is advisable to hold scalars in registers
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190 in a wider mode than that declared by the program. In such cases,
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191 the value is constrained to be within the bounds of the declared
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192 type, but kept valid in the wider mode. The signedness of the
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193 extension may differ from that of the type. */
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194
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195 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
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196 if (GET_MODE_CLASS (MODE) == MODE_INT \
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197 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
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198 { \
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199 if ((MODE) == SImode) \
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200 (UNSIGNEDP) = 0; \
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201 (MODE) = word_mode; \
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202 }
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203
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204 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
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205 Extensions of pointers to word_mode must be signed. */
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206 #define POINTERS_EXTEND_UNSIGNED false
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207
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208 /* Define if loading short immediate values into registers sign extends. */
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209 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
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210
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211 /* Standard register usage. */
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212
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213 /* Number of hardware registers. We have:
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214
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215 - 32 integer registers
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216 - 32 floating point registers
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217 - 2 fake registers:
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218 - ARG_POINTER_REGNUM
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219 - FRAME_POINTER_REGNUM */
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220
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221 #define FIRST_PSEUDO_REGISTER 66
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222
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223 /* x0, sp, gp, and tp are fixed. */
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224
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225 #define FIXED_REGISTERS \
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226 { /* General registers. */ \
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227 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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229 /* Floating-point registers. */ \
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230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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232 /* Others. */ \
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233 1, 1 \
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234 }
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235
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236 /* a0-a7, t0-a6, fa0-fa7, and ft0-ft11 are volatile across calls.
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237 The call RTLs themselves clobber ra. */
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238
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239 #define CALL_USED_REGISTERS \
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240 { /* General registers. */ \
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241 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
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242 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
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243 /* Floating-point registers. */ \
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244 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
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245 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
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246 /* Others. */ \
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247 1, 1 \
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248 }
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249
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250 /* Internal macros to classify an ISA register's type. */
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251
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252 #define GP_REG_FIRST 0
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253 #define GP_REG_LAST 31
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254 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
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255
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256 #define FP_REG_FIRST 32
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257 #define FP_REG_LAST 63
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258 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
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259
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260 /* The DWARF 2 CFA column which tracks the return address from a
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261 signal handler context. This means that to maintain backwards
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262 compatibility, no hard register can be assigned this column if it
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263 would need to be handled by the DWARF unwinder. */
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264 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
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265
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266 #define GP_REG_P(REGNO) \
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267 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
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268 #define FP_REG_P(REGNO) \
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269 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
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270
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271 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
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272
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273 /* Use s0 as the frame pointer if it is so requested. */
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274 #define HARD_FRAME_POINTER_REGNUM 8
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275 #define STACK_POINTER_REGNUM 2
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276 #define THREAD_POINTER_REGNUM 4
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277
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278 /* These two registers don't really exist: they get eliminated to either
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279 the stack or hard frame pointer. */
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280 #define ARG_POINTER_REGNUM 64
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281 #define FRAME_POINTER_REGNUM 65
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282
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283 /* Register in which static-chain is passed to a function. */
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284 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
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285
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286 /* Registers used as temporaries in prologue/epilogue code.
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287
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288 The prologue registers mustn't conflict with any
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289 incoming arguments, the static chain pointer, or the frame pointer.
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290 The epilogue temporary mustn't conflict with the return registers,
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291 the frame pointer, the EH stack adjustment, or the EH data registers. */
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292
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293 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
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294 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
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295
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296 #define MCOUNT_NAME "_mcount"
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297
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298 #define NO_PROFILE_COUNTERS 1
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299
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300 /* Emit rtl for profiling. Output assembler code to FILE
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301 to call "_mcount" for profiling a function entry. */
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302 #define PROFILE_HOOK(LABEL) \
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303 { \
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304 rtx fun, ra; \
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305 ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \
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306 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
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307 emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \
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308 }
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309
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310 /* All the work done in PROFILE_HOOK, but still required. */
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311 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
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312
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313 /* Define this macro if it is as good or better to call a constant
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314 function address than to call an address kept in a register. */
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315 #define NO_FUNCTION_CSE 1
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316
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317 /* Define the classes of registers for register constraints in the
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318 machine description. Also define ranges of constants.
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319
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320 One of the classes must always be named ALL_REGS and include all hard regs.
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321 If there is more than one class, another class must be named NO_REGS
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322 and contain no registers.
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323
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324 The name GENERAL_REGS must be the name of a class (or an alias for
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325 another name such as ALL_REGS). This is the class of registers
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326 that is allowed by "g" or "r" in a register constraint.
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327 Also, registers outside this class are allocated only when
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328 instructions express preferences for them.
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329
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330 The classes must be numbered in nondecreasing order; that is,
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331 a larger-numbered class must never be contained completely
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332 in a smaller-numbered class.
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333
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334 For any two classes, it is very desirable that there be another
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335 class that represents their union. */
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336
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337 enum reg_class
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338 {
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339 NO_REGS, /* no registers in set */
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340 SIBCALL_REGS, /* registers used by indirect sibcalls */
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341 JALR_REGS, /* registers used by indirect calls */
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342 GR_REGS, /* integer registers */
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343 FP_REGS, /* floating-point registers */
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344 FRAME_REGS, /* arg pointer and frame pointer */
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345 ALL_REGS, /* all registers */
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346 LIM_REG_CLASSES /* max value + 1 */
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347 };
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348
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349 #define N_REG_CLASSES (int) LIM_REG_CLASSES
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350
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351 #define GENERAL_REGS GR_REGS
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352
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353 /* An initializer containing the names of the register classes as C
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354 string constants. These names are used in writing some of the
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355 debugging dumps. */
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356
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357 #define REG_CLASS_NAMES \
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358 { \
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359 "NO_REGS", \
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360 "SIBCALL_REGS", \
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361 "JALR_REGS", \
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362 "GR_REGS", \
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363 "FP_REGS", \
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364 "FRAME_REGS", \
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365 "ALL_REGS" \
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366 }
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367
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368 /* An initializer containing the contents of the register classes,
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369 as integers which are bit masks. The Nth integer specifies the
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370 contents of class N. The way the integer MASK is interpreted is
|
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|
371 that register R is in the class if `MASK & (1 << R)' is 1.
|
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372
|
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373 When the machine has more than 32 registers, an integer does not
|
|
|
374 suffice. Then the integers are replaced by sub-initializers,
|
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|
375 braced groupings containing several integers. Each
|
|
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376 sub-initializer must be suitable as an initializer for the type
|
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377 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
|
|
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378
|
|
|
379 #define REG_CLASS_CONTENTS \
|
|
|
380 { \
|
|
|
381 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
|
|
|
382 { 0xf00000c0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
|
|
|
383 { 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \
|
|
|
384 { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \
|
|
|
385 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
|
|
|
386 { 0x00000000, 0x00000000, 0x00000003 }, /* FRAME_REGS */ \
|
|
|
387 { 0xffffffff, 0xffffffff, 0x00000003 } /* ALL_REGS */ \
|
|
|
388 }
|
|
|
389
|
|
|
390 /* A C expression whose value is a register class containing hard
|
|
|
391 register REGNO. In general there is more that one such class;
|
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|
392 choose a class which is "minimal", meaning that no smaller class
|
|
|
393 also contains the register. */
|
|
|
394
|
|
|
395 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
|
|
|
396
|
|
|
397 /* A macro whose definition is the name of the class to which a
|
|
|
398 valid base register must belong. A base register is one used in
|
|
|
399 an address which is the register value plus a displacement. */
|
|
|
400
|
|
|
401 #define BASE_REG_CLASS GR_REGS
|
|
|
402
|
|
|
403 /* A macro whose definition is the name of the class to which a
|
|
|
404 valid index register must belong. An index register is one used
|
|
|
405 in an address where its value is either multiplied by a scale
|
|
|
406 factor or added to another register (as well as added to a
|
|
|
407 displacement). */
|
|
|
408
|
|
|
409 #define INDEX_REG_CLASS NO_REGS
|
|
|
410
|
|
|
411 /* We generally want to put call-clobbered registers ahead of
|
|
|
412 call-saved ones. (IRA expects this.) */
|
|
|
413
|
|
|
414 #define REG_ALLOC_ORDER \
|
|
|
415 { \
|
|
|
416 /* Call-clobbered GPRs. */ \
|
|
|
417 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \
|
|
|
418 /* Call-saved GPRs. */ \
|
|
|
419 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
|
|
|
420 /* GPRs that can never be exposed to the register allocator. */ \
|
|
|
421 0, 2, 3, 4, \
|
|
|
422 /* Call-clobbered FPRs. */ \
|
|
|
423 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \
|
|
|
424 60, 61, 62, 63, \
|
|
|
425 /* Call-saved FPRs. */ \
|
|
|
426 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
|
|
|
427 /* None of the remaining classes have defined call-saved \
|
|
|
428 registers. */ \
|
|
|
429 64, 65 \
|
|
|
430 }
|
|
|
431
|
|
|
432 /* True if VALUE is a signed 12-bit number. */
|
|
|
433
|
|
|
434 #define SMALL_OPERAND(VALUE) \
|
|
|
435 ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
|
|
|
436
|
|
|
437 /* True if VALUE can be loaded into a register using LUI. */
|
|
|
438
|
|
|
439 #define LUI_OPERAND(VALUE) \
|
|
|
440 (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \
|
|
|
441 || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
|
|
|
442
|
|
|
443 /* Stack layout; function entry, exit and calling. */
|
|
|
444
|
|
|
445 #define STACK_GROWS_DOWNWARD 1
|
|
|
446
|
|
|
447 #define FRAME_GROWS_DOWNWARD 1
|
|
|
448
|
|
|
449 #define RETURN_ADDR_RTX riscv_return_addr
|
|
|
450
|
|
|
451 #define ELIMINABLE_REGS \
|
|
|
452 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
|
|
453 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
|
|
454 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
|
|
455 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
|
|
|
456
|
|
|
457 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
|
|
458 (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
|
|
|
459
|
|
|
460 /* Allocate stack space for arguments at the beginning of each function. */
|
|
|
461 #define ACCUMULATE_OUTGOING_ARGS 1
|
|
|
462
|
|
|
463 /* The argument pointer always points to the first argument. */
|
|
|
464 #define FIRST_PARM_OFFSET(FNDECL) 0
|
|
|
465
|
|
|
466 #define REG_PARM_STACK_SPACE(FNDECL) 0
|
|
|
467
|
|
|
468 /* Define this if it is the responsibility of the caller to
|
|
|
469 allocate the area reserved for arguments passed in registers.
|
|
|
470 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
|
|
|
471 of this macro is to determine whether the space is included in
|
|
|
472 `crtl->outgoing_args_size'. */
|
|
|
473 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
|
|
|
474
|
|
|
475 #define STACK_BOUNDARY 128
|
|
|
476
|
|
|
477 /* Symbolic macros for the registers used to return integer and floating
|
|
|
478 point values. */
|
|
|
479
|
|
|
480 #define GP_RETURN GP_ARG_FIRST
|
|
|
481 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
|
|
|
482
|
|
|
483 #define MAX_ARGS_IN_REGISTERS 8
|
|
|
484
|
|
|
485 /* Symbolic macros for the first/last argument registers. */
|
|
|
486
|
|
|
487 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
|
|
|
488 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
|
|
|
489 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
|
|
|
490 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
|
|
|
491 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
|
|
|
492
|
|
|
493 #define CALLEE_SAVED_REG_NUMBER(REGNO) \
|
|
|
494 ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \
|
|
|
495 (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
|
|
|
496
|
|
|
497 #define LIBCALL_VALUE(MODE) \
|
|
|
498 riscv_function_value (NULL_TREE, NULL_TREE, MODE)
|
|
|
499
|
|
|
500 #define FUNCTION_VALUE(VALTYPE, FUNC) \
|
|
|
501 riscv_function_value (VALTYPE, FUNC, VOIDmode)
|
|
|
502
|
|
|
503 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
|
|
|
504
|
|
|
505 /* 1 if N is a possible register number for function argument passing.
|
|
|
506 We have no FP argument registers when soft-float. When FP registers
|
|
|
507 are 32 bits, we can't directly reference the odd numbered ones. */
|
|
|
508
|
|
|
509 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */
|
|
|
510 #define FUNCTION_ARG_REGNO_P(N) \
|
|
|
511 (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \
|
|
|
512 || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
|
|
|
513
|
|
|
514 typedef struct {
|
|
|
515 /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
|
|
|
516 unsigned int num_gprs;
|
|
|
517
|
|
|
518 /* Number of floating-point registers used so far, likewise. */
|
|
|
519 unsigned int num_fprs;
|
|
|
520 } CUMULATIVE_ARGS;
|
|
|
521
|
|
|
522 /* Initialize a variable CUM of type CUMULATIVE_ARGS
|
|
|
523 for a call to a function whose data type is FNTYPE.
|
|
|
524 For a library call, FNTYPE is 0. */
|
|
|
525
|
|
|
526 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
|
|
527 memset (&(CUM), 0, sizeof (CUM))
|
|
|
528
|
|
|
529 #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_ADDR_REGNUM)
|
|
|
530
|
|
|
531 /* ABI requires 16-byte alignment, even on RV32. */
|
|
|
532 #define RISCV_STACK_ALIGN(LOC) (((LOC) + 15) & -16)
|
|
|
533
|
|
|
534 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
|
|
535 the stack pointer does not matter. The value is tested only in
|
|
|
536 functions that have frame pointers.
|
|
|
537 No definition is equivalent to always zero. */
|
|
|
538
|
|
|
539 #define EXIT_IGNORE_STACK 1
|
|
|
540
|
|
|
541
|
|
|
542 /* Trampolines are a block of code followed by two pointers. */
|
|
|
543
|
|
|
544 #define TRAMPOLINE_CODE_SIZE 16
|
|
|
545 #define TRAMPOLINE_SIZE \
|
|
|
546 ((Pmode == SImode) \
|
|
|
547 ? TRAMPOLINE_CODE_SIZE \
|
|
|
548 : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
|
|
|
549 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
|
|
|
550
|
|
|
551 /* Addressing modes, and classification of registers for them. */
|
|
|
552
|
|
|
553 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
|
|
|
554 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
|
|
|
555 riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
|
|
|
556
|
|
|
557 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
|
|
558 and check its validity for a certain class.
|
|
|
559 We have two alternate definitions for each of them.
|
|
|
560 The usual definition accepts all pseudo regs; the other rejects them all.
|
|
|
561 The symbol REG_OK_STRICT causes the latter definition to be used.
|
|
|
562
|
|
|
563 Most source files want to accept pseudo regs in the hope that
|
|
|
564 they will get allocated to the class that the insn wants them to be in.
|
|
|
565 Some source files that are used after register allocation
|
|
|
566 need to be strict. */
|
|
|
567
|
|
|
568 #ifndef REG_OK_STRICT
|
|
|
569 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
|
|
570 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
|
|
|
571 #else
|
|
|
572 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
|
|
573 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
|
|
|
574 #endif
|
|
|
575
|
|
|
576 #define REG_OK_FOR_INDEX_P(X) 0
|
|
|
577
|
|
|
578 /* Maximum number of registers that can appear in a valid memory address. */
|
|
|
579
|
|
|
580 #define MAX_REGS_PER_ADDRESS 1
|
|
|
581
|
|
|
582 #define CONSTANT_ADDRESS_P(X) \
|
|
|
583 (CONSTANT_P (X) && memory_address_p (SImode, X))
|
|
|
584
|
|
|
585 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
|
|
|
586 'the start of the function that this code is output in'. */
|
|
|
587
|
|
|
588 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
|
|
|
589 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
|
|
|
590 asm_fprintf ((FILE), "%U%s", \
|
|
|
591 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
|
|
|
592 else \
|
|
|
593 asm_fprintf ((FILE), "%U%s", (NAME))
|
|
|
594
|
|
|
595 #define JUMP_TABLES_IN_TEXT_SECTION 0
|
|
|
596 #define CASE_VECTOR_MODE SImode
|
|
|
597 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
|
|
|
598
|
|
|
599 /* The load-address macro is used for PC-relative addressing of symbols
|
|
|
600 that bind locally. Don't use it for symbols that should be addressed
|
|
|
601 via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing
|
|
|
602 currently results in more opportunities for linker relaxation. */
|
|
|
603 #define USE_LOAD_ADDRESS_MACRO(sym) \
|
|
|
604 (!TARGET_EXPLICIT_RELOCS && \
|
|
|
605 ((flag_pic \
|
|
|
606 && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \
|
|
|
607 || ((GET_CODE (sym) == CONST) \
|
|
|
608 && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \
|
|
|
609 && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))) \
|
|
|
610 || riscv_cmodel == CM_MEDANY))
|
|
|
611
|
|
|
612 /* Define this as 1 if `char' should by default be signed; else as 0. */
|
|
|
613 #define DEFAULT_SIGNED_CHAR 0
|
|
|
614
|
|
|
615 #define MOVE_MAX UNITS_PER_WORD
|
|
|
616 #define MAX_MOVE_MAX 8
|
|
|
617
|
|
|
618 #define SLOW_BYTE_ACCESS 0
|
|
|
619
|
|
|
620 #define SHIFT_COUNT_TRUNCATED 1
|
|
|
621
|
|
|
622 /* Specify the machine mode that pointers have.
|
|
|
623 After generation of rtl, the compiler makes no further distinction
|
|
|
624 between pointers and any other objects of this machine mode. */
|
|
|
625
|
|
|
626 #define Pmode word_mode
|
|
|
627
|
|
|
628 /* Give call MEMs SImode since it is the "most permissive" mode
|
|
|
629 for both 32-bit and 64-bit targets. */
|
|
|
630
|
|
|
631 #define FUNCTION_MODE SImode
|
|
|
632
|
|
|
633 /* A C expression for the cost of a branch instruction. A value of 2
|
|
|
634 seems to minimize code size. */
|
|
|
635
|
|
|
636 #define BRANCH_COST(speed_p, predictable_p) \
|
|
|
637 ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
|
|
|
638
|
|
|
639 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
|
|
|
640
|
|
|
641 /* Control the assembler format that we output. */
|
|
|
642
|
|
|
643 /* Output to assembler file text saying following lines
|
|
|
644 may contain character constants, extra white space, comments, etc. */
|
|
|
645
|
|
|
646 #ifndef ASM_APP_ON
|
|
|
647 #define ASM_APP_ON " #APP\n"
|
|
|
648 #endif
|
|
|
649
|
|
|
650 /* Output to assembler file text saying following lines
|
|
|
651 no longer contain unusual constructs. */
|
|
|
652
|
|
|
653 #ifndef ASM_APP_OFF
|
|
|
654 #define ASM_APP_OFF " #NO_APP\n"
|
|
|
655 #endif
|
|
|
656
|
|
|
657 #define REGISTER_NAMES \
|
|
|
658 { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \
|
|
|
659 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \
|
|
|
660 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \
|
|
|
661 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \
|
|
|
662 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \
|
|
|
663 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \
|
|
|
664 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \
|
|
|
665 "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \
|
|
|
666 "arg", "frame", }
|
|
|
667
|
|
|
668 #define ADDITIONAL_REGISTER_NAMES \
|
|
|
669 { \
|
|
|
670 { "x0", 0 + GP_REG_FIRST }, \
|
|
|
671 { "x1", 1 + GP_REG_FIRST }, \
|
|
|
672 { "x2", 2 + GP_REG_FIRST }, \
|
|
|
673 { "x3", 3 + GP_REG_FIRST }, \
|
|
|
674 { "x4", 4 + GP_REG_FIRST }, \
|
|
|
675 { "x5", 5 + GP_REG_FIRST }, \
|
|
|
676 { "x6", 6 + GP_REG_FIRST }, \
|
|
|
677 { "x7", 7 + GP_REG_FIRST }, \
|
|
|
678 { "x8", 8 + GP_REG_FIRST }, \
|
|
|
679 { "x9", 9 + GP_REG_FIRST }, \
|
|
|
680 { "x10", 10 + GP_REG_FIRST }, \
|
|
|
681 { "x11", 11 + GP_REG_FIRST }, \
|
|
|
682 { "x12", 12 + GP_REG_FIRST }, \
|
|
|
683 { "x13", 13 + GP_REG_FIRST }, \
|
|
|
684 { "x14", 14 + GP_REG_FIRST }, \
|
|
|
685 { "x15", 15 + GP_REG_FIRST }, \
|
|
|
686 { "x16", 16 + GP_REG_FIRST }, \
|
|
|
687 { "x17", 17 + GP_REG_FIRST }, \
|
|
|
688 { "x18", 18 + GP_REG_FIRST }, \
|
|
|
689 { "x19", 19 + GP_REG_FIRST }, \
|
|
|
690 { "x20", 20 + GP_REG_FIRST }, \
|
|
|
691 { "x21", 21 + GP_REG_FIRST }, \
|
|
|
692 { "x22", 22 + GP_REG_FIRST }, \
|
|
|
693 { "x23", 23 + GP_REG_FIRST }, \
|
|
|
694 { "x24", 24 + GP_REG_FIRST }, \
|
|
|
695 { "x25", 25 + GP_REG_FIRST }, \
|
|
|
696 { "x26", 26 + GP_REG_FIRST }, \
|
|
|
697 { "x27", 27 + GP_REG_FIRST }, \
|
|
|
698 { "x28", 28 + GP_REG_FIRST }, \
|
|
|
699 { "x29", 29 + GP_REG_FIRST }, \
|
|
|
700 { "x30", 30 + GP_REG_FIRST }, \
|
|
|
701 { "x31", 31 + GP_REG_FIRST }, \
|
|
|
702 { "f0", 0 + FP_REG_FIRST }, \
|
|
|
703 { "f1", 1 + FP_REG_FIRST }, \
|
|
|
704 { "f2", 2 + FP_REG_FIRST }, \
|
|
|
705 { "f3", 3 + FP_REG_FIRST }, \
|
|
|
706 { "f4", 4 + FP_REG_FIRST }, \
|
|
|
707 { "f5", 5 + FP_REG_FIRST }, \
|
|
|
708 { "f6", 6 + FP_REG_FIRST }, \
|
|
|
709 { "f7", 7 + FP_REG_FIRST }, \
|
|
|
710 { "f8", 8 + FP_REG_FIRST }, \
|
|
|
711 { "f9", 9 + FP_REG_FIRST }, \
|
|
|
712 { "f10", 10 + FP_REG_FIRST }, \
|
|
|
713 { "f11", 11 + FP_REG_FIRST }, \
|
|
|
714 { "f12", 12 + FP_REG_FIRST }, \
|
|
|
715 { "f13", 13 + FP_REG_FIRST }, \
|
|
|
716 { "f14", 14 + FP_REG_FIRST }, \
|
|
|
717 { "f15", 15 + FP_REG_FIRST }, \
|
|
|
718 { "f16", 16 + FP_REG_FIRST }, \
|
|
|
719 { "f17", 17 + FP_REG_FIRST }, \
|
|
|
720 { "f18", 18 + FP_REG_FIRST }, \
|
|
|
721 { "f19", 19 + FP_REG_FIRST }, \
|
|
|
722 { "f20", 20 + FP_REG_FIRST }, \
|
|
|
723 { "f21", 21 + FP_REG_FIRST }, \
|
|
|
724 { "f22", 22 + FP_REG_FIRST }, \
|
|
|
725 { "f23", 23 + FP_REG_FIRST }, \
|
|
|
726 { "f24", 24 + FP_REG_FIRST }, \
|
|
|
727 { "f25", 25 + FP_REG_FIRST }, \
|
|
|
728 { "f26", 26 + FP_REG_FIRST }, \
|
|
|
729 { "f27", 27 + FP_REG_FIRST }, \
|
|
|
730 { "f28", 28 + FP_REG_FIRST }, \
|
|
|
731 { "f29", 29 + FP_REG_FIRST }, \
|
|
|
732 { "f30", 30 + FP_REG_FIRST }, \
|
|
|
733 { "f31", 31 + FP_REG_FIRST }, \
|
|
|
734 }
|
|
|
735
|
|
|
736 /* Globalizing directive for a label. */
|
|
|
737 #define GLOBAL_ASM_OP "\t.globl\t"
|
|
|
738
|
|
|
739 /* This is how to store into the string LABEL
|
|
|
740 the symbol_ref name of an internal numbered label where
|
|
|
741 PREFIX is the class of label and NUM is the number within the class.
|
|
|
742 This is suitable for output with `assemble_name'. */
|
|
|
743
|
|
|
744 #undef ASM_GENERATE_INTERNAL_LABEL
|
|
|
745 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
|
|
|
746 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
|
|
|
747
|
|
|
748 /* This is how to output an element of a case-vector that is absolute. */
|
|
|
749
|
|
|
750 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
|
|
|
751 fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
|
|
|
752
|
|
|
753 /* This is how to output an element of a PIC case-vector. */
|
|
|
754
|
|
|
755 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
|
|
|
756 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
|
|
|
757 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
|
|
|
758
|
|
|
759 /* This is how to output an assembler line
|
|
|
760 that says to advance the location counter
|
|
|
761 to a multiple of 2**LOG bytes. */
|
|
|
762
|
|
|
763 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
|
|
|
764 fprintf (STREAM, "\t.align\t%d\n", (LOG))
|
|
|
765
|
|
|
766 /* Define the strings to put out for each section in the object file. */
|
|
|
767 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
|
|
|
768 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
|
|
|
769 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata"
|
|
|
770 #define BSS_SECTION_ASM_OP "\t.bss"
|
|
|
771 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits"
|
|
|
772 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits"
|
|
|
773
|
|
|
774 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
|
|
|
775 do \
|
|
|
776 { \
|
|
|
777 fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
|
|
|
778 reg_names[STACK_POINTER_REGNUM], \
|
|
|
779 reg_names[STACK_POINTER_REGNUM], \
|
|
|
780 TARGET_64BIT ? "sd" : "sw", \
|
|
|
781 reg_names[REGNO], \
|
|
|
782 reg_names[STACK_POINTER_REGNUM]); \
|
|
|
783 } \
|
|
|
784 while (0)
|
|
|
785
|
|
|
786 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
|
|
|
787 do \
|
|
|
788 { \
|
|
|
789 fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \
|
|
|
790 TARGET_64BIT ? "ld" : "lw", \
|
|
|
791 reg_names[REGNO], \
|
|
|
792 reg_names[STACK_POINTER_REGNUM], \
|
|
|
793 reg_names[STACK_POINTER_REGNUM], \
|
|
|
794 reg_names[STACK_POINTER_REGNUM]); \
|
|
|
795 } \
|
|
|
796 while (0)
|
|
|
797
|
|
|
798 #define ASM_COMMENT_START "#"
|
|
|
799
|
|
|
800 #undef SIZE_TYPE
|
|
|
801 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
|
|
|
802
|
|
|
803 #undef PTRDIFF_TYPE
|
|
|
804 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
|
|
|
805
|
|
|
806 /* If a memory-to-memory move would take MOVE_RATIO or more simple
|
|
|
807 move-instruction pairs, we will do a movmem or libcall instead. */
|
|
|
808
|
|
|
809 #define MOVE_RATIO(speed) (CLEAR_RATIO (speed) / 2)
|
|
|
810
|
|
|
811 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
|
|
|
812 of the length of a memset call, but use the default otherwise. */
|
|
|
813
|
|
|
814 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
|
|
|
815
|
|
|
816 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
|
|
|
817 optimizing for size adjust the ratio to account for the overhead of
|
|
|
818 loading the constant and replicating it across the word. */
|
|
|
819
|
|
|
820 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
|
|
|
821
|
|
|
822 #ifndef USED_FOR_TARGET
|
|
|
823 extern const enum reg_class riscv_regno_to_class[];
|
|
|
824 #endif
|
|
|
825
|
|
|
826 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
|
|
|
827 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
|
|
|
828
|
|
|
829 #define XLEN_SPEC \
|
|
|
830 "%{march=rv32*:32}" \
|
|
|
831 "%{march=rv64*:64}" \
|
|
|
832
|
|
|
833 #define ABI_SPEC \
|
|
|
834 "%{mabi=ilp32:ilp32}" \
|
|
|
835 "%{mabi=ilp32f:ilp32f}" \
|
|
|
836 "%{mabi=ilp32d:ilp32d}" \
|
|
|
837 "%{mabi=lp64:lp64}" \
|
|
|
838 "%{mabi=lp64f:lp64f}" \
|
|
|
839 "%{mabi=lp64d:lp64d}" \
|
|
|
840
|
|
|
841 #define STARTFILE_PREFIX_SPEC \
|
|
|
842 "/lib" XLEN_SPEC "/" ABI_SPEC "/ " \
|
|
|
843 "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ " \
|
|
|
844 "/lib/ " \
|
|
|
845 "/usr/lib/ "
|
|
|
846
|
|
|
847 /* ISA constants needed for code generation. */
|
|
|
848 #define OPCODE_LW 0x2003
|
|
|
849 #define OPCODE_LD 0x3003
|
|
|
850 #define OPCODE_AUIPC 0x17
|
|
|
851 #define OPCODE_JALR 0x67
|
|
|
852 #define OPCODE_LUI 0x37
|
|
|
853 #define OPCODE_ADDI 0x13
|
|
|
854 #define SHIFT_RD 7
|
|
|
855 #define SHIFT_RS1 15
|
|
|
856 #define SHIFT_IMM 20
|
|
|
857 #define IMM_BITS 12
|
|
|
858
|
|
|
859 #define IMM_REACH (1LL << IMM_BITS)
|
|
|
860 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
|
|
|
861 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
|
|
|
862
|
|
|
863 #endif /* ! GCC_RISCV_H */
|
